* [PATCH 04/12] dt-bindings: riscv: Add T-HEAD C920 compatibles
@ 2023-09-15 7:23 Wang Chen
2023-09-15 14:11 ` Conor Dooley
0 siblings, 1 reply; 4+ messages in thread
From: Wang Chen @ 2023-09-15 7:23 UTC (permalink / raw)
To: linux-riscv, conor, aou, krzysztof.kozlowski+dt, palmer,
paul.walmsley, robh+dt
Cc: devicetree, linux-kernel, jszhang, guoren, chao.wei,
xiaoguang.xing, Wang Chen
The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C920 core is used in the SOPHGO SG2042 SoC.
Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 38c0b5213736..185a0191bad6 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -47,6 +47,7 @@ properties:
- sifive,u74-mc
- thead,c906
- thead,c910
+ - thead,c920
- const: riscv
- items:
- enum:
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 04/12] dt-bindings: riscv: Add T-HEAD C920 compatibles
2023-09-15 7:23 [PATCH 04/12] dt-bindings: riscv: Add T-HEAD C920 compatibles Wang Chen
@ 2023-09-15 14:11 ` Conor Dooley
2023-09-15 15:03 ` Rob Herring
0 siblings, 1 reply; 4+ messages in thread
From: Conor Dooley @ 2023-09-15 14:11 UTC (permalink / raw)
To: Wang Chen
Cc: linux-riscv, aou, krzysztof.kozlowski+dt, palmer, paul.walmsley,
robh+dt, devicetree, linux-kernel, jszhang, guoren, chao.wei,
xiaoguang.xing, Wang Chen
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On Fri, Sep 15, 2023 at 03:23:33PM +0800, Wang Chen wrote:
> The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
> Notably, the C920 core is used in the SOPHGO SG2042 SoC.
>
> Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
> Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
I figure this is missing a From: or Co-developed-by line.
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 38c0b5213736..185a0191bad6 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -47,6 +47,7 @@ properties:
> - sifive,u74-mc
> - thead,c906
> - thead,c910
> + - thead,c920
> - const: riscv
> - items:
> - enum:
> --
> 2.25.1
>
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 04/12] dt-bindings: riscv: Add T-HEAD C920 compatibles
2023-09-15 14:11 ` Conor Dooley
@ 2023-09-15 15:03 ` Rob Herring
2023-09-16 0:46 ` Chen Wang
0 siblings, 1 reply; 4+ messages in thread
From: Rob Herring @ 2023-09-15 15:03 UTC (permalink / raw)
To: Conor Dooley
Cc: Wang Chen, linux-riscv, aou, krzysztof.kozlowski+dt, palmer,
paul.walmsley, devicetree, linux-kernel, jszhang, guoren,
chao.wei, xiaoguang.xing, Wang Chen
On Fri, Sep 15, 2023 at 03:11:43PM +0100, Conor Dooley wrote:
> On Fri, Sep 15, 2023 at 03:23:33PM +0800, Wang Chen wrote:
> > The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
> > Notably, the C920 core is used in the SOPHGO SG2042 SoC.
> >
> > Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
> > Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
>
> I figure this is missing a From: or Co-developed-by line.
From: (author) as 2 authors for 1 line change is questionable.
The sender's email should be the last S-o-b. So like this:
From: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
...
Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
>
> > ---
> > Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index 38c0b5213736..185a0191bad6 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -47,6 +47,7 @@ properties:
> > - sifive,u74-mc
> > - thead,c906
> > - thead,c910
> > + - thead,c920
> > - const: riscv
> > - items:
> > - enum:
> > --
> > 2.25.1
> >
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 04/12] dt-bindings: riscv: Add T-HEAD C920 compatibles
2023-09-15 15:03 ` Rob Herring
@ 2023-09-16 0:46 ` Chen Wang
0 siblings, 0 replies; 4+ messages in thread
From: Chen Wang @ 2023-09-16 0:46 UTC (permalink / raw)
To: Rob Herring
Cc: Conor Dooley, linux-riscv, aou, krzysztof.kozlowski+dt, palmer,
paul.walmsley, devicetree, linux-kernel, jszhang, guoren,
chao.wei, xiaoguang.xing, Wang Chen
Thanks for your detailed clarification, Rob. I'll pay attention next time.
Regards,
unicornx
Rob Herring <robh@kernel.org> 于2023年9月15日周五 23:03写道：
>
> On Fri, Sep 15, 2023 at 03:11:43PM +0100, Conor Dooley wrote:
> > On Fri, Sep 15, 2023 at 03:23:33PM +0800, Wang Chen wrote:
> > > The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
> > > Notably, the C920 core is used in the SOPHGO SG2042 SoC.
> > >
> > > Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
> > > Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> >
> > I figure this is missing a From: or Co-developed-by line.
>
> From: (author) as 2 authors for 1 line change is questionable.
>
> The sender's email should be the last S-o-b. So like this:
>
> From: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
>
> ...
>
> Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
>
>
> >
> > > ---
> > > Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > index 38c0b5213736..185a0191bad6 100644
> > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > @@ -47,6 +47,7 @@ properties:
> > > - sifive,u74-mc
> > > - thead,c906
> > > - thead,c910
> > > + - thead,c920
> > > - const: riscv
> > > - items:
> > > - enum:
> > > --
> > > 2.25.1
> > >
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-09-15 7:23 [PATCH 04/12] dt-bindings: riscv: Add T-HEAD C920 compatibles Wang Chen
2023-09-15 14:11 ` Conor Dooley
2023-09-15 15:03 ` Rob Herring
2023-09-16 0:46 ` Chen Wang
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