[PATCH 1/2] arm64: dts: imx8mp: Fix SDMA2/3 clocks

[PATCH 1/2] arm64: dts: imx8mp: Fix SDMA2/3 clocks

[Adam Ford]

A previous patch to remove the Audio clocks from the main clock node
was intended to force people to setup the audio PLL clocks per board
instead of having a common set of rates since not all boards may use
the various audio PLL clocks for audio devices.

Unfortunately, with this parenting removed, the SDMA2 and SDMA3
clocks were slowed to 24MHz because the SDMA2/3 clocks are controlled
via the audio_blk_ctrl which is clocked from IMX8MP_CLK_AUDIO_ROOT,
and that clock is enabled by pgc_audio.

Per the TRM, "The SDMA2/3 target frequency is 400MHz IPG and 400MHz
AHB, always 1:1 mode, to make sure there is enough throughput for all
the audio use cases."

Instead of cluttering the clock node, place the clock rate and parent
information into the pgc_audio node.

With the parenting and clock rates restored for  IMX8MP_CLK_AUDIO_AHB,
and IMX8MP_CLK_AUDIO_AXI_SRC, it appears the SDMA2 and SDMA3 run at
400MHz again.

Fixes: 16c984524862 ("arm64: dts: imx8mp: don't initialize audio clocks from CCM node")
Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 6f2f50e1639c..408b0c4ec4f8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -790,6 +790,12 @@ pgc_audio: power-domain@5 {
 						reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
 						clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
 							 <&clk IMX8MP_CLK_AUDIO_AXI>;
+						assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
+								  <&clk IMX8MP_CLK_AUDIO_AXI_SRC>;
+						assigned-clock-parents =  <&clk IMX8MP_SYS_PLL1_800M>,
+									  <&clk IMX8MP_SYS_PLL1_800M>;
+						assigned-clock-rates = <400000000>,
+								       <800000000>;
 					};
 
 					pgc_gpu2d: power-domain@6 {
-- 
2.39.2

[PATCH 2/2] arm64: dts: imx8mp-beacon-kit: Fix audio_pll2 clock

[Adam Ford]

A previous patch removed the audio PLL configuration from the clk
node, which resulted in an incorrect clock rate when attempting
to playback audio.  Fix this by setting the AUDIO_PLL2 rate inside
the SAI3 node since it's the SAI3 that needs it.

Fixes: 16c984524862 ("arm64: dts: imx8mp: don't initialize audio clocks from CCM node")
Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
index 06e91297fb16..acd265d8b58e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
@@ -381,9 +381,10 @@ &pcie_phy {
 &sai3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_sai3>;
-	assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
+	assigned-clocks = <&clk IMX8MP_CLK_SAI3>,
+			  <&clk IMX8MP_AUDIO_PLL2> ;
 	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
-	assigned-clock-rates = <12288000>;
+	assigned-clock-rates = <12288000>, <361267200>;
 	fsl,sai-mclk-direction-output;
 	status = "okay";
 };
-- 
2.39.2

Re: [PATCH 1/2] arm64: dts: imx8mp: Fix SDMA2/3 clocks

[Lucas Stach]

Am Sonntag, dem 13.08.2023 um 11:29 -0500 schrieb Adam Ford:
> A previous patch to remove the Audio clocks from the main clock node
> was intended to force people to setup the audio PLL clocks per board
> instead of having a common set of rates since not all boards may use
> the various audio PLL clocks for audio devices.
> 
> Unfortunately, with this parenting removed, the SDMA2 and SDMA3
> clocks were slowed to 24MHz because the SDMA2/3 clocks are controlled
> via the audio_blk_ctrl which is clocked from IMX8MP_CLK_AUDIO_ROOT,
> and that clock is enabled by pgc_audio.
> 
> Per the TRM, "The SDMA2/3 target frequency is 400MHz IPG and 400MHz
> AHB, always 1:1 mode, to make sure there is enough throughput for all
> the audio use cases."
> 
> Instead of cluttering the clock node, place the clock rate and parent
> information into the pgc_audio node.
> 
> With the parenting and clock rates restored for  IMX8MP_CLK_AUDIO_AHB,
> and IMX8MP_CLK_AUDIO_AXI_SRC, it appears the SDMA2 and SDMA3 run at
> 400MHz again.
> 
Note that 800MHz for the AXI clock is overdrive mode for the chip. For
other i.MX8M* chips we tried to have the nominal drive rates as
assigned rates in DT. With the i.MX8MP it's currently a wild mix and
most of the AXI clocks are set to OD rates, so I won't reject this
patch based on this.

Most boards run the DRAM at DDR4-4000, which already requires OD
voltages, so there isn't much point in trying to stick to ND rates on
those boards. We should probably do some consolidation here and come up
with a proper policy for the i.MX8MP soon.

> Fixes: 16c984524862 ("arm64: dts: imx8mp: don't initialize audio clocks from CCM node")
> Signed-off-by: Adam Ford <aford173@gmail.com>

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index 6f2f50e1639c..408b0c4ec4f8 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -790,6 +790,12 @@ pgc_audio: power-domain@5 {
>  						reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
>  						clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
>  							 <&clk IMX8MP_CLK_AUDIO_AXI>;
> +						assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
> +								  <&clk IMX8MP_CLK_AUDIO_AXI_SRC>;
> +						assigned-clock-parents =  <&clk IMX8MP_SYS_PLL1_800M>,
> +									  <&clk IMX8MP_SYS_PLL1_800M>;
> +						assigned-clock-rates = <400000000>,
> +								       <800000000>;
>  					};
>  
>  					pgc_gpu2d: power-domain@6 {

Re: [PATCH 2/2] arm64: dts: imx8mp-beacon-kit: Fix audio_pll2 clock

[Lucas Stach]

Am Sonntag, dem 13.08.2023 um 11:29 -0500 schrieb Adam Ford:
> A previous patch removed the audio PLL configuration from the clk
> node, which resulted in an incorrect clock rate when attempting
> to playback audio.  Fix this by setting the AUDIO_PLL2 rate inside
> the SAI3 node since it's the SAI3 that needs it.
> 
> Fixes: 16c984524862 ("arm64: dts: imx8mp: don't initialize audio clocks from CCM node")
> Signed-off-by: Adam Ford <aford173@gmail.com>

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
> index 06e91297fb16..acd265d8b58e 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
> @@ -381,9 +381,10 @@ &pcie_phy {
>  &sai3 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_sai3>;
> -	assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
> +	assigned-clocks = <&clk IMX8MP_CLK_SAI3>,
> +			  <&clk IMX8MP_AUDIO_PLL2> ;
>  	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
> -	assigned-clock-rates = <12288000>;
> +	assigned-clock-rates = <12288000>, <361267200>;
>  	fsl,sai-mclk-direction-output;
>  	status = "okay";
>  };

Re: [PATCH 1/2] arm64: dts: imx8mp: Fix SDMA2/3 clocks

[Adam Ford]

On Mon, Aug 14, 2023 at 3:22 AM Lucas Stach <l.stach@pengutronix.de> wrote:
>
> Am Sonntag, dem 13.08.2023 um 11:29 -0500 schrieb Adam Ford:
> > A previous patch to remove the Audio clocks from the main clock node
> > was intended to force people to setup the audio PLL clocks per board
> > instead of having a common set of rates since not all boards may use
> > the various audio PLL clocks for audio devices.
> >
> > Unfortunately, with this parenting removed, the SDMA2 and SDMA3
> > clocks were slowed to 24MHz because the SDMA2/3 clocks are controlled
> > via the audio_blk_ctrl which is clocked from IMX8MP_CLK_AUDIO_ROOT,
> > and that clock is enabled by pgc_audio.
> >
> > Per the TRM, "The SDMA2/3 target frequency is 400MHz IPG and 400MHz
> > AHB, always 1:1 mode, to make sure there is enough throughput for all
> > the audio use cases."
> >
> > Instead of cluttering the clock node, place the clock rate and parent
> > information into the pgc_audio node.
> >
> > With the parenting and clock rates restored for  IMX8MP_CLK_AUDIO_AHB,
> > and IMX8MP_CLK_AUDIO_AXI_SRC, it appears the SDMA2 and SDMA3 run at
> > 400MHz again.
> >
> Note that 800MHz for the AXI clock is overdrive mode for the chip. For
> other i.MX8M* chips we tried to have the nominal drive rates as
> assigned rates in DT. With the i.MX8MP it's currently a wild mix and
> most of the AXI clocks are set to OD rates, so I won't reject this
> patch based on this.
>
> Most boards run the DRAM at DDR4-4000, which already requires OD
> voltages, so there isn't much point in trying to stick to ND rates on
> those boards. We should probably do some consolidation here and come up
> with a proper policy for the i.MX8MP soon.

I didn't realize 800MHz was OD.  I just set it to the rate that it was
before the previous patch.  I think the defaults should be ND, and let
boards who need OD set them.  Unless someone objects, I'll submit a
V2.

adam
>
> > Fixes: 16c984524862 ("arm64: dts: imx8mp: don't initialize audio clocks from CCM node")
> > Signed-off-by: Adam Ford <aford173@gmail.com>
>
> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
>
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > index 6f2f50e1639c..408b0c4ec4f8 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > @@ -790,6 +790,12 @@ pgc_audio: power-domain@5 {
> >                                               reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
> >                                               clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
> >                                                        <&clk IMX8MP_CLK_AUDIO_AXI>;
> > +                                             assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
> > +                                                               <&clk IMX8MP_CLK_AUDIO_AXI_SRC>;
> > +                                             assigned-clock-parents =  <&clk IMX8MP_SYS_PLL1_800M>,
> > +                                                                       <&clk IMX8MP_SYS_PLL1_800M>;
> > +                                             assigned-clock-rates = <400000000>,
> > +                                                                    <800000000>;
> >                                       };
> >
> >                                       pgc_gpu2d: power-domain@6 {
>