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Tue, 12 Jul 2022 05:11:49 -0700 (PDT) MIME-Version: 1.0 References: <20220712082146.1192215-1-peng.fan@oss.nxp.com> <20220712082146.1192215-3-peng.fan@oss.nxp.com> In-Reply-To: <20220712082146.1192215-3-peng.fan@oss.nxp.com> From: Adam Ford Date: Tue, 12 Jul 2022 07:11:38 -0500 Message-ID: Subject: Re: [PATCH 2/6] dt-bindings: soc: imx: add i.MX8MP vpu blk ctrl To: "Peng Fan (OSS)" Cc: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Lucas Stach , Sascha Hauer , Fabio Estevam , NXP Linux Team , Laurent Pinchart , Marek Vasut , paul.elder@ideasonboard.com, Markus.Niebel@ew.tq-group.com, Alexander Stein , devicetree , arm-soc , Linux Kernel Mailing List , Aisheng Dong , Peng Fan Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Jul 12, 2022 at 3:20 AM Peng Fan (OSS) wrote: > > From: Peng Fan > > i.MX8MP VPU blk ctrl module has similar design as i.MX8MM, so reuse > the i.MX8MM VPU blk ctrl yaml file. > > Signed-off-by: Peng Fan > --- > .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml | 17 ++++++++++++++--- > include/dt-bindings/power/imx8mp-power.h | 4 ++++ > 2 files changed, 18 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml > index 26487daa64d9..edbd267cdd67 100644 > --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml > +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml > @@ -4,20 +4,22 @@ > $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml# > $schema: http://devicetree.org/meta-schemas/core.yaml# > > -title: NXP i.MX8MM VPU blk-ctrl > +title: NXP i.MX8MM/P VPU blk-ctrl > > maintainers: > - Lucas Stach > > description: > - The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to > + The i.MX8MM/P VPU blk-ctrl is a top-level peripheral providing access to > the NoC and ensuring proper power sequencing of the VPU peripherals > located in the VPU domain of the SoC. > > properties: > compatible: > items: > - - const: fsl,imx8mm-vpu-blk-ctrl > + - enum: > + - fsl,imx8mm-vpu-blk-ctrl > + - fsl,imx8mp-vpu-blk-ctrl > - const: syscon > > reg: > @@ -47,6 +49,15 @@ properties: > - const: g2 > - const: h1 > > + interconnects: > + maxItems: 3 > + > + interconnect-names: > + items: > + - const: g1 > + - const: g2 > + - const: h1 > + > required: > - compatible > - reg > diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h > index 14b9c5ac9c82..11d43fc7a18e 100644 > --- a/include/dt-bindings/power/imx8mp-power.h > +++ b/include/dt-bindings/power/imx8mp-power.h > @@ -52,4 +52,8 @@ > #define IMX8MP_HDMIBLK_PD_HDCP 7 > #define IMX8MP_HDMIBLK_PD_HRV 8 > > +#define IMX8MP_VPUBLK_PD_G1 0 > +#define IMX8MP_VPUBLK_PD_G2 1 > +#define IMX8MP_VPUBLK_PD_H1 2 Is H1 even correct for 8MP? The TRM calls the encoder a VC800E. Since the Encoder on the 8MM is a Hantro H1, this might add confusion if people start thinking they are the same. > + > #endif > -- > 2.25.1 >