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From: Andy Shevchenko <andy.shevchenko@gmail.com>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Marcus Folkesson <marcus.folkesson@gmail.com>,
	Bartosz Golaszewski <brgl@bgdev.pl>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Maxime Ripard <mripard@kernel.org>,
	"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
	devicetree <devicetree@vger.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/2] gpio: gpio-74x164: add support for CDx4HC4094
Date: Mon, 25 Jul 2022 22:48:23 +0200	[thread overview]
Message-ID: <CAHp75VfaExrFYto7LWa5Vnbm6JbiAqtutKmk0HzfeHmmi3PwOg@mail.gmail.com> (raw)
In-Reply-To: <CACRpkdaczrU1tM5Yt7P-Q2h+ge8STOi6HvvYeTM-g+JwS8_gZw@mail.gmail.com>

On Mon, Jul 25, 2022 at 3:54 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> On Mon, Jul 25, 2022 at 11:32 AM Andy Shevchenko
> <andy.shevchenko@gmail.com> wrote:
> > On Thu, Jul 21, 2022 at 11:32 AM Marcus Folkesson
> > <marcus.folkesson@gmail.com> wrote:

...

> > Sorry for my absence of understanding, but why?
> > SPI has MOSI, CLK, CS, where the last one is exactly for that. No?
>
> Forgive me if I misunderstand, but if you use CS that
> way, the way that the SPI framework works is to assert
> CS then transfer a few chunks over SPI (MOSI/CLK)
> then de-assert CS.

No, CS here is used exactly for what it is designed for ("tell that
this message is *for me*"). Yes, hardware implementation here is a
latch register. Because otherwise ALL messages are "for me" which is
wrong. Is it wrong interpretation of the hardware and SPI?

> If CS is used for strobe, it is constantly asserted
> during transfer and the sequence will be latched
> out immediately as you write the SPI transfers and
> the data is clocked through the register, making the
> whole train of zeroes and ones flash across the
> output pins before they stabilize after the SPI
> transfer is finished.

I'm not sure I understand the stabilization issue here. It's how SPI
normally works and we have a lot of delays here and there related to
the phase of the CS in comparison to clock and data. We have a lot of
time to stabilize the outputs of the shift register before latching
it. Did I miss anything?


> If you first do the SPI transfer, then strobe after
> finished, this will not happen.

I have hardware, I have tested it and I understand what you mean by
"stabilizing", but finishing transfer _is_ CS toggling for _this_
chip. No?

> Then it should be a separate pin, so this doesn't
> happen, right?

I think no, you don't need it. I.o.w. either I'm missing something
very interesting about both this kind of chips and SPI basics (shame
on me in this case) or...?


-- 
With Best Regards,
Andy Shevchenko

  parent reply	other threads:[~2022-07-25 20:49 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-21  9:34 [PATCH 1/2] gpio: gpio-74x164: add support for CDx4HC4094 Marcus Folkesson
2022-07-21  9:34 ` [PATCH 2/2] dt-bindings: gpio: fairchild,74hc595: add strobe-gpios property Marcus Folkesson
2022-07-21 10:03   ` Krzysztof Kozlowski
2022-07-26  7:48   ` Linus Walleij
2022-07-21 11:53 ` [PATCH 1/2] gpio: gpio-74x164: add support for CDx4HC4094 Alexander Dahl
2022-07-25  9:32 ` Andy Shevchenko
2022-07-25  9:34   ` Andy Shevchenko
2022-07-25 11:24   ` Marcus Folkesson
2022-07-25 13:54   ` Linus Walleij
2022-07-25 20:41     ` Andy Shevchenko
2022-07-25 20:48     ` Andy Shevchenko [this message]
2022-07-25 22:22       ` Linus Walleij
2022-07-26  6:54         ` Andy Shevchenko
2022-07-26  7:00           ` Andy Shevchenko
2022-07-26  7:02             ` Andy Shevchenko
2022-07-26  7:23           ` Linus Walleij
2022-07-26  7:30             ` Andy Shevchenko
2022-07-26  8:28               ` Linus Walleij
2022-07-26  9:03                 ` Andy Shevchenko

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