* Re: [RFC PATCH v2 2/3] arm64: dts: imx8mm: Add MIPI DSI pipeline
[not found] ` <20211111101456.584061-3-jagan@amarulasolutions.com>
@ 2021-11-12 0:36 ` Tim Harvey
0 siblings, 0 replies; 2+ messages in thread
From: Tim Harvey @ 2021-11-12 0:36 UTC (permalink / raw)
To: Jagan Teki
Cc: Adam Ford, Fabio Estevam, Lucas Stach, Peng Fan, Shawn Guo,
Marek Vasut, Frieder Schrempf, NXP Linux Team,
Linux ARM Mailing List, DRI mailing list, linux-amarula,
Matteo Lisi, Device Tree Mailing List
On Thu, Nov 11, 2021 at 2:15 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> Add MIPI DSI pipeline for i.MX8MM.
>
> Video pipeline start from eLCDIF to MIPI DSI and respective
> Panel or Bridge on the backend side.
>
> Add support for it.
Jagan,
Thanks for your continued work on IMX8MM DSI support!
It doesn't look like you sent this to the Device Tree mainling list so
I added that to cc.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 55 +++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index caeb93313413..eddf3a467fd2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -188,6 +188,12 @@ clk_ext4: clock-ext4 {
> clock-output-names = "clk_ext4";
> };
>
> + mipi_phy: mipi-video-phy {
> + compatible = "fsl,imx8mm-mipi-video-phy";
> + syscon = <&disp_blk_ctrl>;
> + #phy-cells = <1>;
> + };
> +
> psci {
> compatible = "arm,psci-1.0";
> method = "smc";
> @@ -1085,6 +1091,55 @@ lcdif: lcdif@32e00000 {
> interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
> status = "disabled";
> +
> + port {
> + lcdif_out_dsi: endpoint {
> + remote-endpoint = <&dsi_in_lcdif>;
> + };
> + };
> + };
> +
> + dsi: dsi@32e10000 {
I wonder if this should this be 'mipi_dsi' like the CSI bindings
Adam's submitted here:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20211106155427.753197-2-aford173@gmail.com/
> + compatible = "fsl,imx8mm-mipi-dsim";
> + reg = <0x32e10000 0x400>;
> + clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> + <&clk IMX8MM_CLK_DSI_PHY_REF>;
> + clock-names = "bus_clk", "sclk_mipi";
> + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> + <&clk IMX8MM_VIDEO_PLL1_OUT>,
> + <&clk IMX8MM_CLK_DSI_PHY_REF>;
> + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
> + <&clk IMX8MM_VIDEO_PLL1_BYPASS>,
> + <&clk IMX8MM_VIDEO_PLL1_OUT>;
> + assigned-clock-rates = <266000000>, <594000000>, <27000000>;
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&mipi_phy 0>;
> + phy-names = "dsim";
> + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
> + samsung,burst-clock-frequency = <891000000>;
> + samsung,esc-clock-frequency = <54000000>;
> + samsung,pll-clock-frequency = <27000000>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
I don't think the '#address-cells' and '#size-cells' are needed here
but I defer to the dt experts!
> +
> + dsi_in_lcdif: endpoint@0 {
> + reg = <0>;
Per Adam's comment to my posting this should be just "port {" and we
can get rid of the @0 and the "reg=0"
Best regards,
Tim
> + remote-endpoint = <&lcdif_out_dsi>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> };
>
> disp_blk_ctrl: blk-ctrl@32e28000 {
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [RFC PATCH v2 1/3] arm64: dts: imx8mm: Add eLCDIF node support
[not found] ` <20211111101456.584061-2-jagan@amarulasolutions.com>
@ 2021-11-12 0:38 ` Tim Harvey
0 siblings, 0 replies; 2+ messages in thread
From: Tim Harvey @ 2021-11-12 0:38 UTC (permalink / raw)
To: Jagan Teki
Cc: Adam Ford, Fabio Estevam, Lucas Stach, Peng Fan, Shawn Guo,
Marek Vasut, Frieder Schrempf, NXP Linux Team,
Linux ARM Mailing List, DRI mailing list, linux-amarula,
Matteo Lisi, Device Tree Mailing List
On Thu, Nov 11, 2021 at 2:15 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> Add eLCDIF controller node for i.MX8MM.
>
Jagan,
It doesn't look like you sent this to the Device Tree mainling list so
I added that to cc.
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index c2f3f118f82e..caeb93313413 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1068,6 +1068,25 @@ aips4: bus@32c00000 {
> #size-cells = <1>;
> ranges = <0x32c00000 0x32c00000 0x400000>;
>
> + lcdif: lcdif@32e00000 {
> + compatible = "fsl,imx28-lcdif";
> + reg = <0x32e00000 0x10000>;
> + clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
> + <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
> + <&clk IMX8MM_CLK_DISP_APB_ROOT>;
> + clock-names = "pix", "disp_axi", "axi";
> + assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
> + <&clk IMX8MM_CLK_DISP_AXI>,
> + <&clk IMX8MM_CLK_DISP_APB>;
> + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
> + <&clk IMX8MM_SYS_PLL2_1000M>,
> + <&clk IMX8MM_SYS_PLL1_800M>;
> + assigned-clock-rate = <594000000>, <500000000>, <200000000>;
> + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
> + status = "disabled";
> + };
> +
> disp_blk_ctrl: blk-ctrl@32e28000 {
> compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
> reg = <0x32e28000 0x100>;
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 2+ messages in thread
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[not found] ` <20211111101456.584061-3-jagan@amarulasolutions.com>
2021-11-12 0:36 ` [RFC PATCH v2 2/3] arm64: dts: imx8mm: Add MIPI DSI pipeline Tim Harvey
[not found] ` <20211111101456.584061-2-jagan@amarulasolutions.com>
2021-11-12 0:38 ` [RFC PATCH v2 1/3] arm64: dts: imx8mm: Add eLCDIF node support Tim Harvey
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