From: Guo Ren <guoren@kernel.org>
To: Xu Lu <luxu.kernel@bytedance.com>
Cc: corbet@lwn.net, paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, will@kernel.org,
peterz@infradead.org, boqun.feng@gmail.com,
mark.rutland@arm.com, anup@brainfault.org,
atish.patra@linux.dev, pbonzini@redhat.com, shuah@kernel.org,
parri.andrea@gmail.com, ajones@ventanamicro.com,
brs@rivosinc.com, linux-doc@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
apw@canonical.com, joe@perches.com, lukas.bulwahn@gmail.com
Subject: Re: [PATCH v4 04/10] riscv: Introduce Zalasr instructions
Date: Mon, 20 Oct 2025 21:34:27 +0800 [thread overview]
Message-ID: <CAJF2gTRyXPxtw1mvMEAt2NLMUecu++DyN8n+HxmcpbPPF_KB3Q@mail.gmail.com> (raw)
In-Reply-To: <20251020042056.30283-5-luxu.kernel@bytedance.com>
On Mon, Oct 20, 2025 at 12:21 PM Xu Lu <luxu.kernel@bytedance.com> wrote:
>
> Introduce l{b|h|w|d}.{aq|aqrl} and s{b|h|w|d}.{rl|aqrl} instruction
> encodings.
>
> Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
> ---
> arch/riscv/include/asm/insn-def.h | 79 +++++++++++++++++++++++++++++++
> 1 file changed, 79 insertions(+)
>
> diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h
> index d5adbaec1d010..3fec7e66ce50f 100644
> --- a/arch/riscv/include/asm/insn-def.h
> +++ b/arch/riscv/include/asm/insn-def.h
> @@ -179,6 +179,7 @@
> #define RV___RS1(v) __RV_REG(v)
> #define RV___RS2(v) __RV_REG(v)
>
> +#define RV_OPCODE_AMO RV_OPCODE(47)
> #define RV_OPCODE_MISC_MEM RV_OPCODE(15)
> #define RV_OPCODE_OP_IMM RV_OPCODE(19)
> #define RV_OPCODE_SYSTEM RV_OPCODE(115)
> @@ -208,6 +209,84 @@
> __ASM_STR(.error "hlv.d requires 64-bit support")
> #endif
>
> +#define LB_AQ(dest, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(26), \
> + RD(dest), RS1(addr), __RS2(0))
> +
> +#define LB_AQRL(dest, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(27), \
> + RD(dest), RS1(addr), __RS2(0))
> +
> +#define LH_AQ(dest, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(26), \
> + RD(dest), RS1(addr), __RS2(0))
> +
> +#define LH_AQRL(dest, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(27), \
> + RD(dest), RS1(addr), __RS2(0))
> +
> +#define LW_AQ(dest, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(26), \
> + RD(dest), RS1(addr), __RS2(0))
> +
> +#define LW_AQRL(dest, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(27), \
> + RD(dest), RS1(addr), __RS2(0))
> +
> +#define SB_RL(src, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(29), \
> + __RD(0), RS1(addr), RS2(src))
> +
> +#define SB_AQRL(src, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(31), \
> + __RD(0), RS1(addr), RS2(src))
> +
> +#define SH_RL(src, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(29), \
> + __RD(0), RS1(addr), RS2(src))
> +
> +#define SH_AQRL(src, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(31), \
> + __RD(0), RS1(addr), RS2(src))
> +
> +#define SW_RL(src, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(29), \
> + __RD(0), RS1(addr), RS2(src))
> +
> +#define SW_AQRL(src, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(31), \
> + __RD(0), RS1(addr), RS2(src))
> +
> +#ifdef CONFIG_64BIT
> +#define LD_AQ(dest, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(26), \
> + RD(dest), RS1(addr), __RS2(0))
> +
> +#define LD_AQRL(dest, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(27), \
> + RD(dest), RS1(addr), __RS2(0))
> +
> +#define SD_RL(src, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(29), \
> + __RD(0), RS1(addr), RS2(src))
> +
> +#define SD_AQRL(src, addr) \
> + INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(31), \
> + __RD(0), RS1(addr), RS2(src))
> +#else
> +#define LD_AQ(dest, addr) \
> + __ASM_STR(.error "ld.aq requires 64-bit support")
> +
> +#define LD_AQRL(dest, addr) \
> + __ASM_STR(.error "ld.aqrl requires 64-bit support")
> +
> +#define SD_RL(dest, addr) \
> + __ASM_STR(.error "sd.rl requires 64-bit support")
> +
> +#define SD_AQRL(dest, addr) \
> + __ASM_STR(.error "sd.aqrl requires 64-bit support")
> +#endif
> +
> #define SINVAL_VMA(vaddr, asid) \
> INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(11), \
> __RD(0), RS1(vaddr), RS2(asid))
> --
> 2.20.1
>
I didn't find problem.
Reviewed-by: Guo Ren <guoren@kernel.org>
--
Best Regards
Guo Ren
next prev parent reply other threads:[~2025-10-20 13:34 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-20 4:20 [PATCH v4 00/10] riscv: Add Zalasr ISA extension support Xu Lu
2025-10-20 4:20 ` [PATCH v4 01/10] riscv: Add ISA extension parsing for Zalasr Xu Lu
2025-10-20 4:20 ` [PATCH v4 02/10] dt-bindings: riscv: Add Zalasr ISA extension description Xu Lu
2025-10-20 17:21 ` Conor Dooley
2025-10-20 4:20 ` [PATCH v4 03/10] riscv: hwprobe: Export Zalasr extension Xu Lu
2025-10-20 13:46 ` Guo Ren
2025-10-20 4:20 ` [PATCH v4 04/10] riscv: Introduce Zalasr instructions Xu Lu
2025-10-20 13:34 ` Guo Ren [this message]
2025-10-20 4:34 ` [PATCH v4 00/10] riscv: Add Zalasr ISA extension support Xu Lu
2025-10-24 21:47 ` Andrea Parri
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAJF2gTRyXPxtw1mvMEAt2NLMUecu++DyN8n+HxmcpbPPF_KB3Q@mail.gmail.com \
--to=guoren@kernel.org \
--cc=ajones@ventanamicro.com \
--cc=alex@ghiti.fr \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=apw@canonical.com \
--cc=atish.patra@linux.dev \
--cc=boqun.feng@gmail.com \
--cc=brs@rivosinc.com \
--cc=conor+dt@kernel.org \
--cc=corbet@lwn.net \
--cc=devicetree@vger.kernel.org \
--cc=joe@perches.com \
--cc=krzk+dt@kernel.org \
--cc=kvm-riscv@lists.infradead.org \
--cc=kvm@vger.kernel.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-kselftest@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=lukas.bulwahn@gmail.com \
--cc=luxu.kernel@bytedance.com \
--cc=mark.rutland@arm.com \
--cc=palmer@dabbelt.com \
--cc=parri.andrea@gmail.com \
--cc=paul.walmsley@sifive.com \
--cc=pbonzini@redhat.com \
--cc=peterz@infradead.org \
--cc=robh@kernel.org \
--cc=shuah@kernel.org \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).