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Mon, 20 Oct 2025 06:34:44 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCVqcdIhdI5P7h7nBNq/GjTfNxrNMdOwan47goyB2T5qms1njS8wd6yKYxV5i/7xld6r6ecBW3f0f4yT@vger.kernel.org X-Gm-Message-State: AOJu0YxLWVS0J1lyuRdSF50dh1tRpyfUvu9SD7jcF7x39oFp5vgV3PQN YrZzl9Bd4GUXO8qhzUW/mAF9wxG2X/sXnUkEZ4a4XkYq96UWiL+PCnRYcKHjXREiw8DyF3A7nQA V+nxMolPeQBKaG8FR7x0G6xbEFYQ28/M= X-Google-Smtp-Source: AGHT+IFQwlCf7FjnCPutO24ZzoIvXCKxA8V6xzsVKhuniPH312m1I40LeS2q7hRVe9Mx5ZgcbJzBUyetjP4FtY8fo7s= X-Received: by 2002:a05:6000:2c0c:b0:427:928:78a0 with SMTP id ffacd0b85a97d-42709287a50mr7648478f8f.63.1760967283331; Mon, 20 Oct 2025 06:34:43 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20251020042056.30283-1-luxu.kernel@bytedance.com> <20251020042056.30283-5-luxu.kernel@bytedance.com> In-Reply-To: <20251020042056.30283-5-luxu.kernel@bytedance.com> From: Guo Ren Date: Mon, 20 Oct 2025 21:34:27 +0800 X-Gmail-Original-Message-ID: X-Gm-Features: AS18NWDpy2g1Qp1BbuHJudf6VVHWVv_M97q7whwhpvd314t5p96b7PWN5zNzj08 Message-ID: Subject: Re: [PATCH v4 04/10] riscv: Introduce Zalasr instructions To: Xu Lu Cc: corbet@lwn.net, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, will@kernel.org, peterz@infradead.org, boqun.feng@gmail.com, mark.rutland@arm.com, anup@brainfault.org, atish.patra@linux.dev, pbonzini@redhat.com, shuah@kernel.org, parri.andrea@gmail.com, ajones@ventanamicro.com, brs@rivosinc.com, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, apw@canonical.com, joe@perches.com, lukas.bulwahn@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, Oct 20, 2025 at 12:21=E2=80=AFPM Xu Lu = wrote: > > Introduce l{b|h|w|d}.{aq|aqrl} and s{b|h|w|d}.{rl|aqrl} instruction > encodings. > > Signed-off-by: Xu Lu > --- > arch/riscv/include/asm/insn-def.h | 79 +++++++++++++++++++++++++++++++ > 1 file changed, 79 insertions(+) > > diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/i= nsn-def.h > index d5adbaec1d010..3fec7e66ce50f 100644 > --- a/arch/riscv/include/asm/insn-def.h > +++ b/arch/riscv/include/asm/insn-def.h > @@ -179,6 +179,7 @@ > #define RV___RS1(v) __RV_REG(v) > #define RV___RS2(v) __RV_REG(v) > > +#define RV_OPCODE_AMO RV_OPCODE(47) > #define RV_OPCODE_MISC_MEM RV_OPCODE(15) > #define RV_OPCODE_OP_IMM RV_OPCODE(19) > #define RV_OPCODE_SYSTEM RV_OPCODE(115) > @@ -208,6 +209,84 @@ > __ASM_STR(.error "hlv.d requires 64-bit support") > #endif > > +#define LB_AQ(dest, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(26), \ > + RD(dest), RS1(addr), __RS2(0)) > + > +#define LB_AQRL(dest, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(27), \ > + RD(dest), RS1(addr), __RS2(0)) > + > +#define LH_AQ(dest, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(26), \ > + RD(dest), RS1(addr), __RS2(0)) > + > +#define LH_AQRL(dest, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(27), \ > + RD(dest), RS1(addr), __RS2(0)) > + > +#define LW_AQ(dest, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(26), \ > + RD(dest), RS1(addr), __RS2(0)) > + > +#define LW_AQRL(dest, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(27), \ > + RD(dest), RS1(addr), __RS2(0)) > + > +#define SB_RL(src, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(29), \ > + __RD(0), RS1(addr), RS2(src)) > + > +#define SB_AQRL(src, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(31), \ > + __RD(0), RS1(addr), RS2(src)) > + > +#define SH_RL(src, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(29), \ > + __RD(0), RS1(addr), RS2(src)) > + > +#define SH_AQRL(src, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(31), \ > + __RD(0), RS1(addr), RS2(src)) > + > +#define SW_RL(src, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(29), \ > + __RD(0), RS1(addr), RS2(src)) > + > +#define SW_AQRL(src, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(31), \ > + __RD(0), RS1(addr), RS2(src)) > + > +#ifdef CONFIG_64BIT > +#define LD_AQ(dest, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(26), \ > + RD(dest), RS1(addr), __RS2(0)) > + > +#define LD_AQRL(dest, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(27), \ > + RD(dest), RS1(addr), __RS2(0)) > + > +#define SD_RL(src, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(29), \ > + __RD(0), RS1(addr), RS2(src)) > + > +#define SD_AQRL(src, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(31), \ > + __RD(0), RS1(addr), RS2(src)) > +#else > +#define LD_AQ(dest, addr) \ > + __ASM_STR(.error "ld.aq requires 64-bit support") > + > +#define LD_AQRL(dest, addr) \ > + __ASM_STR(.error "ld.aqrl requires 64-bit support") > + > +#define SD_RL(dest, addr) \ > + __ASM_STR(.error "sd.rl requires 64-bit support") > + > +#define SD_AQRL(dest, addr) \ > + __ASM_STR(.error "sd.aqrl requires 64-bit support") > +#endif > + > #define SINVAL_VMA(vaddr, asid) \ > INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(11), \ > __RD(0), RS1(vaddr), RS2(asid)) > -- > 2.20.1 > I didn't find problem. Reviewed-by: Guo Ren --=20 Best Regards Guo Ren