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AJvYcCWnZ7HPN+yQ+ROO8r0X8OPGn+F/lSb1KhBxRx59Qg4nVEfjSEE7KO44tQ55iJgXrinFltQTb7DxF1nf@vger.kernel.org X-Gm-Message-State: AOJu0YwCsOz8Qd8Bs/Ck939BJKDiBIVkLljj/tG8ZpSihSpEgCMdoqD3 7O3ycBwAWzulSqs23Fo+sl3aBFvUFXo5jRIZ97pbYyzmvPSmm03r62a4ISHwPe94JgUkLAHTtYZ bahdc6JJxNoV3af6acxEhsmMHNhfsPAw= X-Gm-Gg: ASbGncs3/4UE8604e6ARuXv6yoAhlaMwE1iawUK4+4gu5Q02VJkS0/XgbAt0JUUWPLL OOGvl8iFUST2bnB3VuRKc7nUaImKRtKMx9KPMJarWp//WdQ1BbLTHUOnG/wWjBQixE5ymyuiS9B XIKU45/IjR2RobAoTOho6y3xTOvRc55NF+a8bQVS9s7VhYAmgEb2b8WiKpCr6phSXgRjIuNFKlI HAE6CT2tUALKYKXYfkDMWENoMxsejtv2ovKwzykxkmaa+CB X-Google-Smtp-Source: AGHT+IGscpAzAZePJIei4M74SY6t3g5clNF77QW53FQZcP/FV0TyOxZ6EHRVDKib2OHnN3hszfUnxw4zg4b0WsneSec= X-Received: by 2002:a17:903:8c8:b0:267:f099:c687 with SMTP id d9443c01a7336-27ed4a29e1bmr33522235ad.1.1758788677041; Thu, 25 Sep 2025 01:24:37 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250924-knp-dts-v1-0-3fdbc4b9e1b1@oss.qualcomm.com> <20250924-knp-dts-v1-6-3fdbc4b9e1b1@oss.qualcomm.com> <53d63dd6-a022-4e80-a317-3218976a7474@oss.qualcomm.com> In-Reply-To: <53d63dd6-a022-4e80-a317-3218976a7474@oss.qualcomm.com> From: =?UTF-8?Q?Krzysztof_Koz=C5=82owski?= Date: Thu, 25 Sep 2025 17:24:24 +0900 X-Gm-Features: AS18NWBrs_SxQohXhwS32-u616VxPcXUdBxvUwQGruDi4ncYM81jJN8M3_KFGEM Message-ID: Subject: Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC To: "Aiqun(Maria) Yu" Cc: Jingyi Wang , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, Ronak Raheja Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, 25 Sept 2025 at 16:39, Aiqun(Maria) Yu wrote: > > On 9/25/2025 9:50 AM, Krzysztof Koz=C5=82owski wrote: > > On Thu, 25 Sept 2025 at 09:17, Jingyi Wang wrote: > >> > >> From: Ronak Raheja > >> > >> Add the base USB devicetree definitions for Kaanapali platform. The ov= erall > >> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY > >> (rev. v8) and M31 eUSB2 PHY. > >> > >> Signed-off-by: Ronak Raheja > >> Signed-off-by: Jingyi Wang > >> --- > >> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 +++++++++++++++++++++++= +++++++++ > >> 1 file changed, 155 insertions(+) > >> > > > > > > Second try, without HTML: > > > > I really don't understand why you created such huge patchset. Year > > ago, two years ago, we were discussing it already and explained that's > > just inflating the patchset without reason. > > > > New Soc is one logical change. Maybe two. Not 18! > > It was previously squashed into the base soc dtsi patch and mark like: > Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja > (added USB), Manish Pandey(added SDHCI), Gaurav Kashyap(added crypto), > Manaf Meethalavalappu Pallikunhi(added tsens), Qiang Yu(added PCIE) and > Jinlong Mao(added coresight). > > While it is over 4000+ lines when we squash it together. > Also as offline reviewed with Bjorn, he suggested us to split out the > USB and other parts. > > > > > Not one patch per node or feature. > > > > This hides big picture, makes difficult to review everything, > > difficult to test. Your patch count for LWN stats doesn't matter to > > us. > > With the current splitting, the different author as each co-developer > can get the meaningful LWN stats.> > > NAK and I'm really disappointed I have to repeat the same review . > Currently, there are 10 SoC DTSI patches sent, structured as follows: > > SoC initial > Base MTP board > SoC PCIe0 > SoC SDC2 > SoC USB > SoC remoteproc > SoC SPMI bus, TSENS, RNG, QCrypto, and Coresight > SoC additional features > SoC audio > SoC CAMSS > SoC video > > Which parts would you prefer to squash into pls? > > -- > Thx and BRs, > Aiqun(Maria) Yu