* [PATCH 01/20] dt-bindings: arm: qcom: Document Kaanapali SoC and its reference boards
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-10-06 9:54 ` Krzysztof Kozlowski
2025-09-25 0:17 ` [PATCH 02/20] arm64: dts: qcom: Introduce Kaanapali SoC Jingyi Wang
` (21 subsequent siblings)
22 siblings, 1 reply; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang
Document the Kaanapali SoC binding and the boards which use it.
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 838e3d4bb24a..0e84220e835c 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -321,6 +321,12 @@ properties:
- qcom,ipq9574-ap-al02-c9
- const: qcom,ipq9574
+ - items:
+ - enum:
+ - qcom,kaanapali-mtp
+ - qcom,kaanapali-qrd
+ - const: qcom,kaanapali
+
- description: Sierra Wireless MangOH Green with WP8548 Module
items:
- const: swir,mangoh-green-wp8548
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* Re: [PATCH 01/20] dt-bindings: arm: qcom: Document Kaanapali SoC and its reference boards
2025-09-25 0:17 ` [PATCH 01/20] dt-bindings: arm: qcom: Document Kaanapali SoC and its reference boards Jingyi Wang
@ 2025-10-06 9:54 ` Krzysztof Kozlowski
2025-10-06 10:24 ` Krzysztof Kozlowski
0 siblings, 1 reply; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-06 9:54 UTC (permalink / raw)
To: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang
On 25/09/2025 09:17, Jingyi Wang wrote:
> Document the Kaanapali SoC binding and the boards which use it.
>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index 838e3d4bb24a..0e84220e835c 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> @@ -321,6 +321,12 @@ properties:
> - qcom,ipq9574-ap-al02-c9
> - const: qcom,ipq9574
>
> + - items:
> + - enum:
> + - qcom,kaanapali-mtp
> + - qcom,kaanapali-qrd
> + - const: qcom,kaanapali
This will fail testing, just like Glymur did. I fixed up Glymur, but it
was rather one time.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 01/20] dt-bindings: arm: qcom: Document Kaanapali SoC and its reference boards
2025-10-06 9:54 ` Krzysztof Kozlowski
@ 2025-10-06 10:24 ` Krzysztof Kozlowski
2025-10-14 5:13 ` Jingyi Wang
0 siblings, 1 reply; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-06 10:24 UTC (permalink / raw)
To: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang
On 06/10/2025 18:54, Krzysztof Kozlowski wrote:
> On 25/09/2025 09:17, Jingyi Wang wrote:
>> Document the Kaanapali SoC binding and the boards which use it.
>>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>> index 838e3d4bb24a..0e84220e835c 100644
>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>> @@ -321,6 +321,12 @@ properties:
>> - qcom,ipq9574-ap-al02-c9
>> - const: qcom,ipq9574
>>
>> + - items:
>> + - enum:
>> + - qcom,kaanapali-mtp
>> + - qcom,kaanapali-qrd
>> + - const: qcom,kaanapali
>
> This will fail testing, just like Glymur did. I fixed up Glymur, but it
> was rather one time.
Ah, this will not fail testing because Qualcomm switched to code names
from obvious model names, making existing patterns non-effective.
Not sure if this can be reliably improved now, ehh....
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 01/20] dt-bindings: arm: qcom: Document Kaanapali SoC and its reference boards
2025-10-06 10:24 ` Krzysztof Kozlowski
@ 2025-10-14 5:13 ` Jingyi Wang
0 siblings, 0 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-10-14 5:13 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang
On 10/6/2025 6:24 PM, Krzysztof Kozlowski wrote:
> On 06/10/2025 18:54, Krzysztof Kozlowski wrote:
>> On 25/09/2025 09:17, Jingyi Wang wrote:
>>> Document the Kaanapali SoC binding and the boards which use it.
>>>
>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>>> ---
>>> Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
>>> 1 file changed, 6 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>>> index 838e3d4bb24a..0e84220e835c 100644
>>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>>> @@ -321,6 +321,12 @@ properties:
>>> - qcom,ipq9574-ap-al02-c9
>>> - const: qcom,ipq9574
>>>
>>> + - items:
>>> + - enum:
>>> + - qcom,kaanapali-mtp
>>> + - qcom,kaanapali-qrd
>>> + - const: qcom,kaanapali
>>
>> This will fail testing, just like Glymur did. I fixed up Glymur, but it
>> was rather one time.
>
>
> Ah, this will not fail testing because Qualcomm switched to code names
> from obvious model names, making existing patterns non-effective.
>
> Not sure if this can be reliably improved now, ehh....
>
> Best regards,
> Krzysztof
yes. I didn't find it fail the test. However, do you need me add patch like this?
https://lore.kernel.org/all/20250716162412.27471-2-krzysztof.kozlowski@linaro.org/
Thanks,
Jingyi
^ permalink raw reply [flat|nested] 135+ messages in thread
* [PATCH 02/20] arm64: dts: qcom: Introduce Kaanapali SoC
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
2025-09-25 0:17 ` [PATCH 01/20] dt-bindings: arm: qcom: Document Kaanapali SoC and its reference boards Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-09-25 3:22 ` Dmitry Baryshkov
` (2 more replies)
2025-09-25 0:17 ` [PATCH 03/20] arm64: dts: qcom: kaanapali: Add base MTP board Jingyi Wang
` (20 subsequent siblings)
22 siblings, 3 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang, Tengfei Fan
Kaanapali is Snapdragon SoC from Qualcomm.
Features added in this patch:
- CPUs with PSCI idle states and cpufreq
- Interrupt-controller with PDC wakeup support
- Timers, TCSR Clock Controllers
- Reserved Shared memory
- GCC and RPMHCC
- TLMM
- Interconnect with CPU BWMONs
- QuP with uart
- SMMU
- RPMHPD
- UFS with Inline Crypto Engine
- LLCC
- Watchdog
Written with help from Raviteja Laggyshetty(added interconnect nodes),
Taniya Das(added Clock Controllers and cpufreq), Jishnu Prakash
(added rpmhpd), Nitin Rawat(added ufs) and Gaurav Kashyap(added ICE).
Co-developed-by: Tengfei Fan <tengfei.fan@oss.qualcomm.com>
Signed-off-by: Tengfei Fan <tengfei.fan@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1320 +++++++++++++++++++++++++++++++
1 file changed, 1320 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
new file mode 100644
index 000000000000..b385b4642883
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -0,0 +1,1320 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/clock/qcom,kaanapali-gcc.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
+#include <dt-bindings/firmware/qcom,scm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd0>;
+ power-domain-names = "psci";
+ clocks = <&pdp_scmi_perf 0>;
+
+ l2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd1>;
+ power-domain-names = "psci";
+ clocks = <&pdp_scmi_perf 0>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd2>;
+ power-domain-names = "psci";
+ clocks = <&pdp_scmi_perf 0>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd3>;
+ power-domain-names = "psci";
+ clocks = <&pdp_scmi_perf 0>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd4>;
+ power-domain-names = "psci";
+ clocks = <&pdp_scmi_perf 0>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd5>;
+ power-domain-names = "psci";
+ clocks = <&pdp_scmi_perf 0>;
+ };
+
+ cpu6: cpu@10000 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x10000>;
+ enable-method = "psci";
+ next-level-cache = <&l2_1>;
+ power-domains = <&cpu_pd6>;
+ power-domain-names = "psci";
+ clocks = <&pdp_scmi_perf 1>;
+
+ l2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ cpu7: cpu@10100 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x10100>;
+ enable-method = "psci";
+ next-level-cache = <&l2_1>;
+ power-domains = <&cpu_pd7>;
+ power-domain-names = "psci";
+ clocks = <&pdp_scmi_perf 1>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+
+ core4 {
+ cpu = <&cpu4>;
+ };
+
+ core5 {
+ cpu = <&cpu5>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu6>;
+ };
+
+ core1 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ cluster0_c4: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "retention";
+ arm,psci-suspend-param = <0x00000004>;
+ entry-latency-us = <93>;
+ exit-latency-us = <129>;
+ min-residency-us = <560>;
+ };
+
+ cluster1_c4: cpu-sleep-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "retention";
+ arm,psci-suspend-param = <0x00000004>;
+ entry-latency-us = <172>;
+ exit-latency-us = <130>;
+ min-residency-us = <686>;
+ };
+ };
+
+ domain-idle-states {
+ cluster_cl5: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x01000054>;
+ entry-latency-us = <2150>;
+ exit-latency-us = <1983>;
+ min-residency-us = <9144>;
+ };
+
+ domain_ss3: domain-sleep-0 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x0200c354>;
+ entry-latency-us = <2800>;
+ exit-latency-us = <4400>;
+ min-residency-us = <10150>;
+ };
+ };
+ };
+
+ firmware {
+ scm: scm {
+ compatible = "qcom,scm-kaanapali", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x19000>;
+ };
+
+ scmi: scmi {
+ compatible = "arm,scmi";
+ mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>;
+ mbox-names = "tx", "rx";
+ shmem = <&pdp_tx>, <&pdp_rx>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pdp_scmi_perf: protocol@13 {
+ reg = <0x13>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+
+ clk_virt: interconnect-0 {
+ compatible = "qcom,kaanapali-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect-1 {
+ compatible = "qcom,kaanapali-mc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ memory@a0000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0xa0000000 0x0 0x0>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ cpu_pd0: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster0_c4>;
+ };
+
+ cpu_pd1: power-domain-cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster0_c4>;
+ };
+
+ cpu_pd2: power-domain-cpu2 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster0_c4>;
+ };
+
+ cpu_pd3: power-domain-cpu3 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster0_c4>;
+ };
+
+ cpu_pd4: power-domain-cpu4 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster0_c4>;
+ };
+
+ cpu_pd5: power-domain-cpu5 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster0_c4>;
+ };
+
+ cpu_pd6: power-domain-cpu6 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster1_c4>;
+ };
+
+ cpu_pd7: power-domain-cpu7 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster1_c4>;
+ };
+
+ cluster_pd: power-domain-cluster {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cluster_cl5>;
+ power-domains = <&system_pd>;
+ };
+
+ system_pd: power-domain-system {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&domain_ss3>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ pdp_mem: pdp_region@81300000 {
+ reg = <0x0 0x81300000 0x0 0x100000>;
+ no-map;
+ };
+
+ aop_cmd_db_mem: aop-cmd-db@81c60000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x81c60000 0x0 0x20000>;
+ no-map;
+ };
+
+ smem_mem: smem@81d00000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x81d00000 0x0 0x200000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
+ };
+
+ pdp_ns_shared_mem: pdp_ns_shared_region@81f00000 {
+ reg = <0x0 0x81f00000 0x0 0x100000>;
+ no-map;
+ };
+
+ dsm_partition_1_mem: dsm-partition-1@84a00000 {
+ reg = <0x0 0x84a00000 0x0 0x5500000>;
+ no-map;
+ };
+
+ dsm_partition_2_mem: dsm-partition-2@89f00000 {
+ reg = <0x0 0x89f00000 0x0 0xa80000>;
+ no-map;
+ };
+
+ mpss_mem: mpss@8aa00000 {
+ reg = <0x0 0x8aa00000 0x0 0xeb00000>;
+ no-map;
+ };
+
+ q6_mpss_dtb_mem: q6-mpss-dtb@99500000 {
+ reg = <0x0 0x99500000 0x0 0x80000>;
+ no-map;
+ };
+
+ ipa_fw_mem: ipa-fw@99580000 {
+ reg = <0x0 0x99580000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi@99590000 {
+ reg = <0x0 0x99590000 0x0 0xa000>;
+ no-map;
+ };
+
+ gpu_microcode_mem: gpu-microcode@9959a000 {
+ reg = <0x0 0x9959a000 0x0 0x2000>;
+ no-map;
+ };
+
+ camera_mem: camera@99600000 {
+ reg = <0x0 0x99600000 0x0 0x800000>;
+ no-map;
+ };
+
+ camera_2_mem: camera-2@99e00000 {
+ reg = <0x0 0x99e00000 0x0 0x800000>;
+ no-map;
+ };
+
+ video_mem: video@9a600000 {
+ reg = <0x0 0x9a600000 0x0 0x800000>;
+ no-map;
+ };
+
+ cvp_mem: cvp@9ae00000 {
+ reg = <0x0 0x9ae00000 0x0 0x700000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp@9b500000 {
+ reg = <0x0 0x9b500000 0x0 0x1900000>;
+ no-map;
+ };
+
+ q6_cdsp_dtb_mem: q6-cdsp-dtb@9ce00000 {
+ reg = <0x0 0x9ce00000 0x0 0x80000>;
+ no-map;
+ };
+
+ soccp_mem: soccp@a03d0000 {
+ reg = <0x0 0xa03d0000 0x0 0x500000>;
+ no-map;
+ };
+
+ soccp_dtb_mem: soccp-dtb@a08d0000 {
+ reg = <0x0 0xa08d0000 0x0 0x40000>;
+ no-map;
+ };
+
+ q6_adsp_dtb_mem: q6-adsp-dtb@a1380000 {
+ reg = <0x0 0xa1380000 0x0 0x80000>;
+ no-map;
+ };
+
+ adspslpi_mem: adspslpi@a1400000 {
+ reg = <0x0 0xa1400000 0x0 0x4c00000>;
+ no-map;
+ };
+
+ rmtfs_mem: rmtfs@d7c00000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0 0xd7c00000 0 0x400000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
+ };
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0 0 0 0 0x10 0>;
+ ranges = <0 0 0 0 0x10 0>;
+
+ gcc: clock-controller@100000 {
+ compatible = "qcom,kaanapali-gcc";
+ reg = <0x0 0x00100000 0x0 0x1f4200>;
+
+ clocks = <&bi_tcxo_div2>,
+ <0>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ qupv3_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x00ac0000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AXI_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ iommus = <&apps_smmu 0xa3 0x0>;
+
+ dma-coherent;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ uart7: serial@a9c000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x00a9c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart7_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+ };
+
+ ipcc: mailbox@1106000 {
+ compatible = "qcom,kaanapali-ipcc", "qcom,ipcc";
+ reg = <0x0 0x01106000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ #mbox-cells = <2>;
+ };
+
+ cnoc_main: interconnect@1500000 {
+ compatible = "qcom,kaanapali-cnoc-main";
+ reg = <0x0 0x01500000 0x0 0x1a080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ config_noc: interconnect@1600000 {
+ compatible = "qcom,kaanapali-cnoc-cfg";
+ reg = <0x0 0x01600000 0x0 0x6200>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ system_noc: interconnect@1680000 {
+ compatible = "qcom,kaanapali-system-noc";
+ reg = <0x0 0x01680000 0x0 0x1f080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ pcie_noc: interconnect@16c0000 {
+ compatible = "qcom,kaanapali-pcie-anoc";
+ reg = <0x0 0x016c0000 0x0 0x11400>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
+ };
+
+ aggre_noc: interconnect@16e0000 {
+ compatible = "qcom,kaanapali-aggre-noc";
+ reg = <0x0 0x016e0000 0x0 0x42400>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&rpmhcc RPMH_IPA_CLK>;
+ };
+
+ mmss_noc: interconnect@1780000 {
+ compatible = "qcom,kaanapali-mmss-noc";
+ reg = <0x0 0x01780000 0x0 0x5b800>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ ufs_mem_phy: phy@1d80000 {
+ compatible = "qcom,kaanapali-qmp-ufs-phy", "qcom,sm8750-qmp-ufs-phy";
+ reg = <0x0 0x01d80000 0x0 0x2000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&tcsrcc TCSR_UFS_CLKREF_EN>;
+
+ clock-names = "ref",
+ "ref_aux",
+ "qref";
+
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+
+ power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ ufs_mem_hc: ufs@1d84000 {
+ compatible = "qcom,kaanapali-ufshc",
+ "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0x0 0x01d84000 0x0 0x3000>;
+
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_LN_BB_CLK3>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ clock-names = "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+
+ operating-points-v2 = <&ufs_opp_table>;
+
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ interconnects = <&aggre_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "ufs-ddr",
+ "cpu-ufs";
+
+ power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ iommus = <&apps_smmu 0x60 0x0>;
+ dma-coherent;
+
+ lanes-per-direction = <2>;
+ qcom,ice = <&ice>;
+
+ phys = <&ufs_mem_phy>;
+ phy-names = "ufsphy";
+
+ #reset-cells = <1>;
+
+ status = "disabled";
+
+ ufs_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <75000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <100000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-403000000 {
+ opp-hz = /bits/ 64 <403000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <403000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ ice: crypto@1d88000 {
+ compatible = "qcom,kaanapali-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0x0 0x01d88000 0x0 0x18000>;
+
+ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x0 0x01f40000 0x0 0x20000>;
+ #hwlock-cells = <1>;
+ };
+
+ tcsr: syscon@1fc0000 {
+ compatible = "qcom,tcsr-kaanapali", "syscon";
+ reg = <0x0 0x1fc0000 0x0 0x30000>;
+ };
+
+ tcsrcc: clock-controller@1fd5044 {
+ compatible = "qcom,kaanapali-tcsr", "syscon";
+ reg = <0x0 0x01fd5044 0x0 0x1c>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ lpass_lpiaon_noc: interconnect@7400000 {
+ compatible = "qcom,kaanapali-lpass-lpiaon-noc";
+ reg = <0x0 0x07400000 0x0 0x19080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ lpass_lpicx_noc: interconnect@7420000 {
+ compatible = "qcom,kaanapali-lpass-lpicx-noc";
+ reg = <0x0 0x07420000 0x0 0x44080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ lpass_ag_noc: interconnect@7f40000 {
+ compatible = "qcom,kaanapali-lpass-ag-noc";
+ reg = <0x0 0x07f40000 0x0 0xe080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,kaanapali-pdc", "qcom,pdc";
+ reg = <0x0 0x0b220000 0x0 0x10000>,
+ <0x0 0x179600f0 0x0 0xf4>;
+
+ qcom,pdc-ranges = <0 745 38>,
+ <40 785 11>,
+ <51 527 4>,
+ <58 534 2>,
+ <61 537 20>,
+ <84 559 14>,
+ <98 609 32>,
+ <130 717 12>,
+ <142 251 5>,
+ <147 796 16>,
+ <163 783 2>,
+ <165 531 2>,
+ <167 536 1>,
+ <168 557 2>,
+ <170 415 1>,
+ <171 438 1>,
+ <172 579 1>,
+ <173 703 1>,
+ <174 708 1>,
+ <175 714 1>,
+ <176 68 1>,
+ <177 86 1>,
+ <178 96 1>,
+ <179 249 1>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ aoss_qmp: power-management@c300000 {
+ compatible = "qcom,kaanapali-aoss-qmp", "qcom,aoss-qmp";
+ reg = <0x0 0x0c300000 0x0 0x400>;
+
+ interrupts-extended = <&ipcc IPCC_MPROC_AOP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_MPROC_AOP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ #clock-cells = <0>;
+ };
+
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,kaanapali-tlmm";
+ reg = <0x0 0x0f100000 0x0 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 218>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ wakeup-parent = <&pdc>;
+
+ qup_uart7_default: qup-uart7-state {
+ /* TX, RX */
+ pins = "gpio62", "gpio63";
+ function = "qup1_se7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ sram@14680000 {
+ compatible = "qcom,kaanapali-imem", "syscon", "simple-mfd";
+ reg = <0x0 0x14680000 0x0 0x1000>;
+ ranges = <0 0 0x14680000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pil-reloc@94c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x94c 0xc8>;
+ };
+ };
+
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,kaanapali-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x15000000 0x0 0x100000>;
+
+ interrupts =<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>;
+
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+
+ dma-coherent;
+ };
+
+ intc: interrupt-controller@17000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x17000000 0x0 0x10000>,
+ <0x0 0x17080000 0x0 0x200000>;
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ #interrupt-cells = <3>;
+ interrupt-controller;
+
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x40000>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic_its: msi-controller@17040000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x17040000 0x0 0x20000>;
+
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ watchdog@17600000 {
+ compatible = "qcom,apss-wdt-kaanapali", "qcom,kpss-wdt";
+ reg = <0x0 0x17600000 0x0 0x1000>;
+ clocks = <&sleep_clk>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pdp0_mbox: mailbox@17610000 {
+ compatible = "qcom,kaanapali-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
+ reg = <0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ };
+
+ timer@17810000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0 0x17810000 0x0 0x1000>;
+
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0 0x20000000>;
+
+ frame@17811000 {
+ reg = <0x0 0x17811000 0x1000>,
+ <0x0 0x17812000 0x1000>;
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ frame@17813000 {
+ reg = <0x0 0x17813000 0x1000>;
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ frame@17815000 {
+ reg = <0x0 0x17815000 0x1000>;
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ frame@17817000 {
+ reg = <0x0 0x17817000 0x1000>;
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ frame@17819000 {
+ reg = <0x0 0x17819000 0x1000>;
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ frame@1781b000 {
+ reg = <0x0 0x1781b000 0x1000>;
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ frame@1781d000 {
+ reg = <0x0 0x1781d000 0x1000>;
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ apps_rsc: rsc@18900000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x0 0x18900000 0x0 0x10000>,
+ <0x0 0x18910000 0x0 0x10000>,
+ <0x0 0x18920000 0x0 0x10000>;
+ reg-names = "drv-0",
+ "drv-1",
+ "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+ power-domains = <&system_pd>;
+ label = "apps_rsc";
+
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 3>,
+ <SLEEP_TCS 2>,
+ <WAKE_TCS 2>,
+ <CONTROL_TCS 0>;
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,kaanapali-rpmh-clk";
+ #clock-cells = <1>;
+ clocks = <&xo_board>;
+ clock-names = "xo";
+ };
+
+ rpmhpd: power-controller {
+ compatible = "qcom,kaanapali-rpmhpd";
+
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ #power-domain-cells = <1>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp-16 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_low_svs_d3: opp-50 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
+ };
+
+ rpmhpd_opp_low_svs_d2_1: opp-51 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2_1>;
+ };
+
+ rpmhpd_opp_low_svs_d2: opp-52 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+ };
+
+ rpmhpd_opp_low_svs_d1_1: opp-54 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1_1>;
+ };
+
+ rpmhpd_opp_low_svs_d1: opp-56 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ };
+
+ rpmhpd_opp_low_svs_d0: opp-60 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+ };
+
+ rpmhpd_opp_low_svs: opp-64 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_low_svs_l0: opp-76 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L0>;
+ };
+
+ rpmhpd_opp_low_svs_l1: opp-80 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+ };
+
+ rpmhpd_opp_low_svs_l2: opp-96 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>;
+ };
+
+ rpmhpd_opp_svs: opp-128 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l0: opp-144 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+ };
+
+ rpmhpd_opp_svs_l1: opp-192 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_svs_l2: opp-224 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ };
+
+ rpmhpd_opp_nom: opp-256 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp-320 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp-336 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp-384 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l0: opp-400 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L0>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp-416 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+
+ rpmhpd_opp_turbo_l2: opp-432 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
+ };
+
+ rpmhpd_opp_turbo_l3: opp-448 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
+ };
+
+ rpmhpd_opp_turbo_l4: opp-452 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
+ };
+
+ rpmhpd_opp_turbo_l5: opp-456 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>;
+ };
+
+ rpmhpd_opp_super_turbo_no_cpr: opp-480 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>;
+ };
+ };
+ };
+ };
+
+ nsp_noc: interconnect@260c0000 {
+ compatible = "qcom,kaanapali-nsp-noc";
+ reg = <0x0 0x260c0000 0x0 0x21280>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ /* Cluster 0 */
+ pmu@310b3400 {
+ compatible = "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon";
+ reg = <0x0 0x310b3400 0x0 0x600>;
+
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+ cpu_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <2188000>;
+ };
+
+ opp-1 {
+ opp-peak-kBps = <5412000>;
+ };
+
+ opp-2 {
+ opp-peak-kBps = <6220000>;
+ };
+
+ opp-3 {
+ opp-peak-kBps = <6832000>;
+ };
+
+ opp-4 {
+ opp-peak-kBps = <8368000>;
+ };
+
+ opp-5 {
+ opp-peak-kBps = <10944000>;
+ };
+
+ opp-6 {
+ opp-peak-kBps = <12748000>;
+ };
+
+ opp-7 {
+ opp-peak-kBps = <14744000>;
+ };
+
+ opp-8 {
+ opp-peak-kBps = <16896000>;
+ };
+
+ opp-9 {
+ opp-peak-kBps = <19120000>;
+ };
+
+ opp-10 {
+ opp-peak-kBps = <21332000>;
+ };
+ };
+ };
+
+ /* Cluster 1 */
+ pmu@310b7400 {
+ compatible = "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon";
+ reg = <0x0 0x310b7400 0x0 0x600>;
+
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+ };
+
+ gem_noc: interconnect@31100000 {
+ compatible = "qcom,kaanapali-gem-noc";
+ reg = <0x0 0x31100000 0x0 0x153080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ system-cache-controller@31800000 {
+ compatible = "qcom,kaanapali-llcc";
+ reg = <0x0 0x31800000 0x0 0x200000>,
+ <0x0 0x32800000 0x0 0x200000>,
+ <0x0 0x31c00000 0x0 0x200000>,
+ <0x0 0x32c00000 0x0 0x200000>,
+ <0x0 0x34800000 0x0 0x200000>,
+ <0x0 0x34c00000 0x0 0x200000>;
+ reg-names = "llcc0_base",
+ "llcc1_base",
+ "llcc2_base",
+ "llcc3_base",
+ "llcc_broadcast_base",
+ "llcc_broadcast_and_base";
+
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sram: sram@81f08000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x81f08000 0x0 0x200>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x81f08000 0x200>;
+
+ pdp_rx: scp-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x80>;
+ };
+
+ pdp_tx: scp-sram-section@100 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x100 0x80>;
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* Re: [PATCH 02/20] arm64: dts: qcom: Introduce Kaanapali SoC
2025-09-25 0:17 ` [PATCH 02/20] arm64: dts: qcom: Introduce Kaanapali SoC Jingyi Wang
@ 2025-09-25 3:22 ` Dmitry Baryshkov
2025-10-14 16:43 ` Taniya Das
2025-10-14 11:46 ` Akhil P Oommen
2025-11-20 6:53 ` Komal Bajaj
2 siblings, 1 reply; 135+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 3:22 UTC (permalink / raw)
To: Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Tengfei Fan
On Wed, Sep 24, 2025 at 05:17:19PM -0700, Jingyi Wang wrote:
> Kaanapali is Snapdragon SoC from Qualcomm.
>
> Features added in this patch:
> - CPUs with PSCI idle states and cpufreq
> - Interrupt-controller with PDC wakeup support
> - Timers, TCSR Clock Controllers
> - Reserved Shared memory
> - GCC and RPMHCC
> - TLMM
> - Interconnect with CPU BWMONs
> - QuP with uart
> - SMMU
> - RPMHPD
> - UFS with Inline Crypto Engine
> - LLCC
> - Watchdog
>
> Written with help from Raviteja Laggyshetty(added interconnect nodes),
> Taniya Das(added Clock Controllers and cpufreq), Jishnu Prakash
> (added rpmhpd), Nitin Rawat(added ufs) and Gaurav Kashyap(added ICE).
>
> Co-developed-by: Tengfei Fan <tengfei.fan@oss.qualcomm.com>
> Signed-off-by: Tengfei Fan <tengfei.fan@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1320 +++++++++++++++++++++++++++++++
> 1 file changed, 1320 insertions(+)
>
> +
> + soc: soc@0 {
> + compatible = "simple-bus";
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-ranges = <0 0 0 0 0x10 0>;
> + ranges = <0 0 0 0 0x10 0>;
> +
> + gcc: clock-controller@100000 {
> + compatible = "qcom,kaanapali-gcc";
> + reg = <0x0 0x00100000 0x0 0x1f4200>;
> +
> + clocks = <&bi_tcxo_div2>,
> + <0>,
> + <&sleep_clk>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>;
You have UFS clocks. Why are they <0> here?
> +
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 02/20] arm64: dts: qcom: Introduce Kaanapali SoC
2025-09-25 3:22 ` Dmitry Baryshkov
@ 2025-10-14 16:43 ` Taniya Das
0 siblings, 0 replies; 135+ messages in thread
From: Taniya Das @ 2025-10-14 16:43 UTC (permalink / raw)
To: Dmitry Baryshkov, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Tengfei Fan
On 9/25/2025 8:52 AM, Dmitry Baryshkov wrote:
> On Wed, Sep 24, 2025 at 05:17:19PM -0700, Jingyi Wang wrote:
>> Kaanapali is Snapdragon SoC from Qualcomm.
>>
>> Features added in this patch:
>> - CPUs with PSCI idle states and cpufreq
>> - Interrupt-controller with PDC wakeup support
>> - Timers, TCSR Clock Controllers
>> - Reserved Shared memory
>> - GCC and RPMHCC
>> - TLMM
>> - Interconnect with CPU BWMONs
>> - QuP with uart
>> - SMMU
>> - RPMHPD
>> - UFS with Inline Crypto Engine
>> - LLCC
>> - Watchdog
>>
>> Written with help from Raviteja Laggyshetty(added interconnect nodes),
>> Taniya Das(added Clock Controllers and cpufreq), Jishnu Prakash
>> (added rpmhpd), Nitin Rawat(added ufs) and Gaurav Kashyap(added ICE).
>>
>> Co-developed-by: Tengfei Fan <tengfei.fan@oss.qualcomm.com>
>> Signed-off-by: Tengfei Fan <tengfei.fan@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1320 +++++++++++++++++++++++++++++++
>> 1 file changed, 1320 insertions(+)
>>
>> +
>> + soc: soc@0 {
>> + compatible = "simple-bus";
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + dma-ranges = <0 0 0 0 0x10 0>;
>> + ranges = <0 0 0 0 0x10 0>;
>> +
>> + gcc: clock-controller@100000 {
>> + compatible = "qcom,kaanapali-gcc";
>> + reg = <0x0 0x00100000 0x0 0x1f4200>;
>> +
>> + clocks = <&bi_tcxo_div2>,
>> + <0>,
>> + <&sleep_clk>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>;
>
> You have UFS clocks. Why are they <0> here?
Yeah Dmitry, I will update the ufs_mem_phy clocks in the next patch.
>
>> +
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> +
>
--
Thanks,
Taniya Das
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 02/20] arm64: dts: qcom: Introduce Kaanapali SoC
2025-09-25 0:17 ` [PATCH 02/20] arm64: dts: qcom: Introduce Kaanapali SoC Jingyi Wang
2025-09-25 3:22 ` Dmitry Baryshkov
@ 2025-10-14 11:46 ` Akhil P Oommen
2025-11-04 9:04 ` Jingyi Wang
2025-11-20 6:53 ` Komal Bajaj
2 siblings, 1 reply; 135+ messages in thread
From: Akhil P Oommen @ 2025-10-14 11:46 UTC (permalink / raw)
To: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Tengfei Fan
On 9/25/2025 5:47 AM, Jingyi Wang wrote:
> Kaanapali is Snapdragon SoC from Qualcomm.
>
> Features added in this patch:
> - CPUs with PSCI idle states and cpufreq
> - Interrupt-controller with PDC wakeup support
> - Timers, TCSR Clock Controllers
> - Reserved Shared memory
> - GCC and RPMHCC
> - TLMM
> - Interconnect with CPU BWMONs
> - QuP with uart
> - SMMU
> - RPMHPD
> - UFS with Inline Crypto Engine
> - LLCC
> - Watchdog
>
> Written with help from Raviteja Laggyshetty(added interconnect nodes),
> Taniya Das(added Clock Controllers and cpufreq), Jishnu Prakash
> (added rpmhpd), Nitin Rawat(added ufs) and Gaurav Kashyap(added ICE).
>
> Co-developed-by: Tengfei Fan <tengfei.fan@oss.qualcomm.com>
> Signed-off-by: Tengfei Fan <tengfei.fan@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1320 +++++++++++++++++++++++++++++++
> 1 file changed, 1320 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> new file mode 100644
> index 000000000000..b385b4642883
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> @@ -0,0 +1,1320 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <dt-bindings/clock/qcom,kaanapali-gcc.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
> +#include <dt-bindings/firmware/qcom,scm.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interconnect/qcom,icc.h>
> +#include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/mailbox/qcom-ipcc.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "qcom,oryon";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + next-level-cache = <&l2_0>;
> + power-domains = <&cpu_pd0>;
> + power-domain-names = "psci";
> + clocks = <&pdp_scmi_perf 0>;
> +
> + l2_0: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + };
> + };
> +
> + cpu1: cpu@100 {
> + device_type = "cpu";
> + compatible = "qcom,oryon";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + next-level-cache = <&l2_0>;
> + power-domains = <&cpu_pd1>;
> + power-domain-names = "psci";
> + clocks = <&pdp_scmi_perf 0>;
> + };
> +
> + cpu2: cpu@200 {
> + device_type = "cpu";
> + compatible = "qcom,oryon";
> + reg = <0x0 0x200>;
> + enable-method = "psci";
> + next-level-cache = <&l2_0>;
> + power-domains = <&cpu_pd2>;
> + power-domain-names = "psci";
> + clocks = <&pdp_scmi_perf 0>;
> + };
> +
> + cpu3: cpu@300 {
> + device_type = "cpu";
> + compatible = "qcom,oryon";
> + reg = <0x0 0x300>;
> + enable-method = "psci";
> + next-level-cache = <&l2_0>;
> + power-domains = <&cpu_pd3>;
> + power-domain-names = "psci";
> + clocks = <&pdp_scmi_perf 0>;
> + };
> +
> + cpu4: cpu@400 {
> + device_type = "cpu";
> + compatible = "qcom,oryon";
> + reg = <0x0 0x400>;
> + enable-method = "psci";
> + next-level-cache = <&l2_0>;
> + power-domains = <&cpu_pd4>;
> + power-domain-names = "psci";
> + clocks = <&pdp_scmi_perf 0>;
> + };
> +
> + cpu5: cpu@500 {
> + device_type = "cpu";
> + compatible = "qcom,oryon";
> + reg = <0x0 0x500>;
> + enable-method = "psci";
> + next-level-cache = <&l2_0>;
> + power-domains = <&cpu_pd5>;
> + power-domain-names = "psci";
> + clocks = <&pdp_scmi_perf 0>;
> + };
> +
> + cpu6: cpu@10000 {
> + device_type = "cpu";
> + compatible = "qcom,oryon";
> + reg = <0x0 0x10000>;
> + enable-method = "psci";
> + next-level-cache = <&l2_1>;
> + power-domains = <&cpu_pd6>;
> + power-domain-names = "psci";
> + clocks = <&pdp_scmi_perf 1>;
> +
> + l2_1: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + };
> + };
> +
> + cpu7: cpu@10100 {
> + device_type = "cpu";
> + compatible = "qcom,oryon";
> + reg = <0x0 0x10100>;
> + enable-method = "psci";
> + next-level-cache = <&l2_1>;
> + power-domains = <&cpu_pd7>;
> + power-domain-names = "psci";
> + clocks = <&pdp_scmi_perf 1>;
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> +
> + core1 {
> + cpu = <&cpu1>;
> + };
> +
> + core2 {
> + cpu = <&cpu2>;
> + };
> +
> + core3 {
> + cpu = <&cpu3>;
> + };
> +
> + core4 {
> + cpu = <&cpu4>;
> + };
> +
> + core5 {
> + cpu = <&cpu5>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu6>;
> + };
> +
> + core1 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + idle-states {
> + entry-method = "psci";
> +
> + cluster0_c4: cpu-sleep-0 {
> + compatible = "arm,idle-state";
> + idle-state-name = "retention";
> + arm,psci-suspend-param = <0x00000004>;
> + entry-latency-us = <93>;
> + exit-latency-us = <129>;
> + min-residency-us = <560>;
> + };
> +
> + cluster1_c4: cpu-sleep-1 {
> + compatible = "arm,idle-state";
> + idle-state-name = "retention";
> + arm,psci-suspend-param = <0x00000004>;
> + entry-latency-us = <172>;
> + exit-latency-us = <130>;
> + min-residency-us = <686>;
> + };
> + };
> +
> + domain-idle-states {
> + cluster_cl5: cluster-sleep-0 {
> + compatible = "domain-idle-state";
> + arm,psci-suspend-param = <0x01000054>;
> + entry-latency-us = <2150>;
> + exit-latency-us = <1983>;
> + min-residency-us = <9144>;
> + };
> +
> + domain_ss3: domain-sleep-0 {
> + compatible = "domain-idle-state";
> + arm,psci-suspend-param = <0x0200c354>;
> + entry-latency-us = <2800>;
> + exit-latency-us = <4400>;
> + min-residency-us = <10150>;
> + };
> + };
> + };
> +
> + firmware {
> + scm: scm {
> + compatible = "qcom,scm-kaanapali", "qcom,scm";
> + qcom,dload-mode = <&tcsr 0x19000>;
> + };
> +
> + scmi: scmi {
> + compatible = "arm,scmi";
> + mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>;
> + mbox-names = "tx", "rx";
> + shmem = <&pdp_tx>, <&pdp_rx>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pdp_scmi_perf: protocol@13 {
> + reg = <0x13>;
> + #clock-cells = <1>;
> + };
> + };
> + };
> +
> + clk_virt: interconnect-0 {
> + compatible = "qcom,kaanapali-clk-virt";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + mc_virt: interconnect-1 {
> + compatible = "qcom,kaanapali-mc-virt";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + memory@a0000000 {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the size */
> + reg = <0x0 0xa0000000 0x0 0x0>;
> + };
> +
> + pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> +
> + cpu_pd0: power-domain-cpu0 {
> + #power-domain-cells = <0>;
> + power-domains = <&cluster_pd>;
> + domain-idle-states = <&cluster0_c4>;
> + };
> +
> + cpu_pd1: power-domain-cpu1 {
> + #power-domain-cells = <0>;
> + power-domains = <&cluster_pd>;
> + domain-idle-states = <&cluster0_c4>;
> + };
> +
> + cpu_pd2: power-domain-cpu2 {
> + #power-domain-cells = <0>;
> + power-domains = <&cluster_pd>;
> + domain-idle-states = <&cluster0_c4>;
> + };
> +
> + cpu_pd3: power-domain-cpu3 {
> + #power-domain-cells = <0>;
> + power-domains = <&cluster_pd>;
> + domain-idle-states = <&cluster0_c4>;
> + };
> +
> + cpu_pd4: power-domain-cpu4 {
> + #power-domain-cells = <0>;
> + power-domains = <&cluster_pd>;
> + domain-idle-states = <&cluster0_c4>;
> + };
> +
> + cpu_pd5: power-domain-cpu5 {
> + #power-domain-cells = <0>;
> + power-domains = <&cluster_pd>;
> + domain-idle-states = <&cluster0_c4>;
> + };
> +
> + cpu_pd6: power-domain-cpu6 {
> + #power-domain-cells = <0>;
> + power-domains = <&cluster_pd>;
> + domain-idle-states = <&cluster1_c4>;
> + };
> +
> + cpu_pd7: power-domain-cpu7 {
> + #power-domain-cells = <0>;
> + power-domains = <&cluster_pd>;
> + domain-idle-states = <&cluster1_c4>;
> + };
> +
> + cluster_pd: power-domain-cluster {
> + #power-domain-cells = <0>;
> + domain-idle-states = <&cluster_cl5>;
> + power-domains = <&system_pd>;
> + };
> +
> + system_pd: power-domain-system {
> + #power-domain-cells = <0>;
> + domain-idle-states = <&domain_ss3>;
> + };
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
This is missing a bunch of reserved regions which causes device crash
when you stress memory allocation.
-Akhil.
> + pdp_mem: pdp_region@81300000 {
> + reg = <0x0 0x81300000 0x0 0x100000>;
> + no-map;
> + };
> +
> + aop_cmd_db_mem: aop-cmd-db@81c60000 {
> + compatible = "qcom,cmd-db";
> + reg = <0x0 0x81c60000 0x0 0x20000>;
> + no-map;
> + };
> +
> + smem_mem: smem@81d00000 {
> + compatible = "qcom,smem";
> + reg = <0x0 0x81d00000 0x0 0x200000>;
> + hwlocks = <&tcsr_mutex 3>;
> + no-map;
> + };
> +
> + pdp_ns_shared_mem: pdp_ns_shared_region@81f00000 {
> + reg = <0x0 0x81f00000 0x0 0x100000>;
> + no-map;
> + };
> +
> + dsm_partition_1_mem: dsm-partition-1@84a00000 {
> + reg = <0x0 0x84a00000 0x0 0x5500000>;
> + no-map;
> + };
> +
> + dsm_partition_2_mem: dsm-partition-2@89f00000 {
> + reg = <0x0 0x89f00000 0x0 0xa80000>;
> + no-map;
> + };
> +
> + mpss_mem: mpss@8aa00000 {
> + reg = <0x0 0x8aa00000 0x0 0xeb00000>;
> + no-map;
> + };
> +
> + q6_mpss_dtb_mem: q6-mpss-dtb@99500000 {
> + reg = <0x0 0x99500000 0x0 0x80000>;
> + no-map;
> + };
> +
> + ipa_fw_mem: ipa-fw@99580000 {
> + reg = <0x0 0x99580000 0x0 0x10000>;
> + no-map;
> + };
> +
> + ipa_gsi_mem: ipa-gsi@99590000 {
> + reg = <0x0 0x99590000 0x0 0xa000>;
> + no-map;
> + };
> +
> + gpu_microcode_mem: gpu-microcode@9959a000 {
> + reg = <0x0 0x9959a000 0x0 0x2000>;
> + no-map;
> + };
> +
> + camera_mem: camera@99600000 {
> + reg = <0x0 0x99600000 0x0 0x800000>;
> + no-map;
> + };
> +
> + camera_2_mem: camera-2@99e00000 {
> + reg = <0x0 0x99e00000 0x0 0x800000>;
> + no-map;
> + };
> +
> + video_mem: video@9a600000 {
> + reg = <0x0 0x9a600000 0x0 0x800000>;
> + no-map;
> + };
> +
> + cvp_mem: cvp@9ae00000 {
> + reg = <0x0 0x9ae00000 0x0 0x700000>;
> + no-map;
> + };
> +
> + cdsp_mem: cdsp@9b500000 {
> + reg = <0x0 0x9b500000 0x0 0x1900000>;
> + no-map;
> + };
> +
> + q6_cdsp_dtb_mem: q6-cdsp-dtb@9ce00000 {
> + reg = <0x0 0x9ce00000 0x0 0x80000>;
> + no-map;
> + };
> +
> + soccp_mem: soccp@a03d0000 {
> + reg = <0x0 0xa03d0000 0x0 0x500000>;
> + no-map;
> + };
> +
> + soccp_dtb_mem: soccp-dtb@a08d0000 {
> + reg = <0x0 0xa08d0000 0x0 0x40000>;
> + no-map;
> + };
> +
> + q6_adsp_dtb_mem: q6-adsp-dtb@a1380000 {
> + reg = <0x0 0xa1380000 0x0 0x80000>;
> + no-map;
> + };
> +
> + adspslpi_mem: adspslpi@a1400000 {
> + reg = <0x0 0xa1400000 0x0 0x4c00000>;
> + no-map;
> + };
> +
> + rmtfs_mem: rmtfs@d7c00000 {
> + compatible = "qcom,rmtfs-mem";
> + reg = <0 0xd7c00000 0 0x400000>;
> + no-map;
> +
> + qcom,client-id = <1>;
> + qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
> + };
> + };
> +
> + soc: soc@0 {
> + compatible = "simple-bus";
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-ranges = <0 0 0 0 0x10 0>;
> + ranges = <0 0 0 0 0x10 0>;
> +
> + gcc: clock-controller@100000 {
> + compatible = "qcom,kaanapali-gcc";
> + reg = <0x0 0x00100000 0x0 0x1f4200>;
> +
> + clocks = <&bi_tcxo_div2>,
> + <0>,
> + <&sleep_clk>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>;
> +
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> + qupv3_1: geniqup@ac0000 {
> + compatible = "qcom,geni-se-qup";
> + reg = <0x0 0x00ac0000 0x0 0x2000>;
> +
> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AXI_CLK>,
> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> + clock-names = "m-ahb",
> + "s-ahb";
> +
> + iommus = <&apps_smmu 0xa3 0x0>;
> +
> + dma-coherent;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + uart7: serial@a9c000 {
> + compatible = "qcom,geni-debug-uart";
> + reg = <0x0 0x00a9c000 0x0 0x4000>;
> +
> + interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
> + clock-names = "se";
> +
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
> + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
> + interconnect-names = "qup-core",
> + "qup-config";
> +
> + pinctrl-0 = <&qup_uart7_default>;
> + pinctrl-names = "default";
> +
> + status = "disabled";
> + };
> + };
> +
> + ipcc: mailbox@1106000 {
> + compatible = "qcom,kaanapali-ipcc", "qcom,ipcc";
> + reg = <0x0 0x01106000 0x0 0x1000>;
> +
> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> +
> + #mbox-cells = <2>;
> + };
> +
> + cnoc_main: interconnect@1500000 {
> + compatible = "qcom,kaanapali-cnoc-main";
> + reg = <0x0 0x01500000 0x0 0x1a080>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + #interconnect-cells = <2>;
> + };
> +
> + config_noc: interconnect@1600000 {
> + compatible = "qcom,kaanapali-cnoc-cfg";
> + reg = <0x0 0x01600000 0x0 0x6200>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + #interconnect-cells = <2>;
> + };
> +
> + system_noc: interconnect@1680000 {
> + compatible = "qcom,kaanapali-system-noc";
> + reg = <0x0 0x01680000 0x0 0x1f080>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + #interconnect-cells = <2>;
> + };
> +
> + pcie_noc: interconnect@16c0000 {
> + compatible = "qcom,kaanapali-pcie-anoc";
> + reg = <0x0 0x016c0000 0x0 0x11400>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + #interconnect-cells = <2>;
> + clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
> + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
> + };
> +
> + aggre_noc: interconnect@16e0000 {
> + compatible = "qcom,kaanapali-aggre-noc";
> + reg = <0x0 0x016e0000 0x0 0x42400>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + #interconnect-cells = <2>;
> + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
> + <&rpmhcc RPMH_IPA_CLK>;
> + };
> +
> + mmss_noc: interconnect@1780000 {
> + compatible = "qcom,kaanapali-mmss-noc";
> + reg = <0x0 0x01780000 0x0 0x5b800>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + #interconnect-cells = <2>;
> + };
> +
> + ufs_mem_phy: phy@1d80000 {
> + compatible = "qcom,kaanapali-qmp-ufs-phy", "qcom,sm8750-qmp-ufs-phy";
> + reg = <0x0 0x01d80000 0x0 0x2000>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> + <&tcsrcc TCSR_UFS_CLKREF_EN>;
> +
> + clock-names = "ref",
> + "ref_aux",
> + "qref";
> +
> + resets = <&ufs_mem_hc 0>;
> + reset-names = "ufsphy";
> +
> + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + ufs_mem_hc: ufs@1d84000 {
> + compatible = "qcom,kaanapali-ufshc",
> + "qcom,ufshc",
> + "jedec,ufs-2.0";
> + reg = <0x0 0x01d84000 0x0 0x3000>;
> +
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_UFS_PHY_AHB_CLK>,
> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> + <&rpmhcc RPMH_LN_BB_CLK3>,
> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> + clock-names = "core_clk",
> + "bus_aggr_clk",
> + "iface_clk",
> + "core_clk_unipro",
> + "ref_clk",
> + "tx_lane0_sync_clk",
> + "rx_lane0_sync_clk",
> + "rx_lane1_sync_clk";
> +
> + operating-points-v2 = <&ufs_opp_table>;
> +
> + resets = <&gcc GCC_UFS_PHY_BCR>;
> + reset-names = "rst";
> +
> + interconnects = <&aggre_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
> + interconnect-names = "ufs-ddr",
> + "cpu-ufs";
> +
> + power-domains = <&gcc GCC_UFS_PHY_GDSC>;
> + required-opps = <&rpmhpd_opp_nom>;
> +
> + iommus = <&apps_smmu 0x60 0x0>;
> + dma-coherent;
> +
> + lanes-per-direction = <2>;
> + qcom,ice = <&ice>;
> +
> + phys = <&ufs_mem_phy>;
> + phy-names = "ufsphy";
> +
> + #reset-cells = <1>;
> +
> + status = "disabled";
> +
> + ufs_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-75000000 {
> + opp-hz = /bits/ 64 <75000000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <75000000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>;
> + required-opps = <&rpmhpd_opp_low_svs_d1>;
> + };
> +
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <100000000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-403000000 {
> + opp-hz = /bits/ 64 <403000000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <403000000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> +
> + ice: crypto@1d88000 {
> + compatible = "qcom,kaanapali-inline-crypto-engine",
> + "qcom,inline-crypto-engine";
> + reg = <0x0 0x01d88000 0x0 0x18000>;
> +
> + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
> + };
> +
> + tcsr_mutex: hwlock@1f40000 {
> + compatible = "qcom,tcsr-mutex";
> + reg = <0x0 0x01f40000 0x0 0x20000>;
> + #hwlock-cells = <1>;
> + };
> +
> + tcsr: syscon@1fc0000 {
> + compatible = "qcom,tcsr-kaanapali", "syscon";
> + reg = <0x0 0x1fc0000 0x0 0x30000>;
> + };
> +
> + tcsrcc: clock-controller@1fd5044 {
> + compatible = "qcom,kaanapali-tcsr", "syscon";
> + reg = <0x0 0x01fd5044 0x0 0x1c>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> +
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + lpass_lpiaon_noc: interconnect@7400000 {
> + compatible = "qcom,kaanapali-lpass-lpiaon-noc";
> + reg = <0x0 0x07400000 0x0 0x19080>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + #interconnect-cells = <2>;
> + };
> +
> + lpass_lpicx_noc: interconnect@7420000 {
> + compatible = "qcom,kaanapali-lpass-lpicx-noc";
> + reg = <0x0 0x07420000 0x0 0x44080>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + #interconnect-cells = <2>;
> + };
> +
> + lpass_ag_noc: interconnect@7f40000 {
> + compatible = "qcom,kaanapali-lpass-ag-noc";
> + reg = <0x0 0x07f40000 0x0 0xe080>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + #interconnect-cells = <2>;
> + };
> +
> + pdc: interrupt-controller@b220000 {
> + compatible = "qcom,kaanapali-pdc", "qcom,pdc";
> + reg = <0x0 0x0b220000 0x0 0x10000>,
> + <0x0 0x179600f0 0x0 0xf4>;
> +
> + qcom,pdc-ranges = <0 745 38>,
> + <40 785 11>,
> + <51 527 4>,
> + <58 534 2>,
> + <61 537 20>,
> + <84 559 14>,
> + <98 609 32>,
> + <130 717 12>,
> + <142 251 5>,
> + <147 796 16>,
> + <163 783 2>,
> + <165 531 2>,
> + <167 536 1>,
> + <168 557 2>,
> + <170 415 1>,
> + <171 438 1>,
> + <172 579 1>,
> + <173 703 1>,
> + <174 708 1>,
> + <175 714 1>,
> + <176 68 1>,
> + <177 86 1>,
> + <178 96 1>,
> + <179 249 1>;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&intc>;
> + interrupt-controller;
> + };
> +
> + aoss_qmp: power-management@c300000 {
> + compatible = "qcom,kaanapali-aoss-qmp", "qcom,aoss-qmp";
> + reg = <0x0 0x0c300000 0x0 0x400>;
> +
> + interrupts-extended = <&ipcc IPCC_MPROC_AOP
> + IPCC_MPROC_SIGNAL_GLINK_QMP
> + IRQ_TYPE_EDGE_RISING>;
> +
> + mboxes = <&ipcc IPCC_MPROC_AOP
> + IPCC_MPROC_SIGNAL_GLINK_QMP>;
> +
> + #clock-cells = <0>;
> + };
> +
> + tlmm: pinctrl@f100000 {
> + compatible = "qcom,kaanapali-tlmm";
> + reg = <0x0 0x0f100000 0x0 0x300000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 218>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + wakeup-parent = <&pdc>;
> +
> + qup_uart7_default: qup-uart7-state {
> + /* TX, RX */
> + pins = "gpio62", "gpio63";
> + function = "qup1_se7";
> + drive-strength = <2>;
> + bias-disable;
> + };
> + };
> +
> + sram@14680000 {
> + compatible = "qcom,kaanapali-imem", "syscon", "simple-mfd";
> + reg = <0x0 0x14680000 0x0 0x1000>;
> + ranges = <0 0 0x14680000 0x1000>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + pil-reloc@94c {
> + compatible = "qcom,pil-reloc-info";
> + reg = <0x94c 0xc8>;
> + };
> + };
> +
> + apps_smmu: iommu@15000000 {
> + compatible = "qcom,kaanapali-smmu-500", "qcom,smmu-500", "arm,mmu-500";
> + reg = <0x0 0x15000000 0x0 0x100000>;
> +
> + interrupts =<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>;
> +
> + #iommu-cells = <2>;
> + #global-interrupts = <1>;
> +
> + dma-coherent;
> + };
> +
> + intc: interrupt-controller@17000000 {
> + compatible = "arm,gic-v3";
> + reg = <0x0 0x17000000 0x0 0x10000>,
> + <0x0 0x17080000 0x0 0x200000>;
> +
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> + #interrupt-cells = <3>;
> + interrupt-controller;
> +
> + #redistributor-regions = <1>;
> + redistributor-stride = <0x0 0x40000>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + gic_its: msi-controller@17040000 {
> + compatible = "arm,gic-v3-its";
> + reg = <0x0 0x17040000 0x0 0x20000>;
> +
> + msi-controller;
> + #msi-cells = <1>;
> + };
> + };
> +
> + watchdog@17600000 {
> + compatible = "qcom,apss-wdt-kaanapali", "qcom,kpss-wdt";
> + reg = <0x0 0x17600000 0x0 0x1000>;
> + clocks = <&sleep_clk>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
> + };
> +
> + pdp0_mbox: mailbox@17610000 {
> + compatible = "qcom,kaanapali-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
> + reg = <0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>;
> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <1>;
> + };
> +
> + timer@17810000 {
> + compatible = "arm,armv7-timer-mem";
> + reg = <0x0 0x17810000 0x0 0x1000>;
> +
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0 0x20000000>;
> +
> + frame@17811000 {
> + reg = <0x0 0x17811000 0x1000>,
> + <0x0 0x17812000 0x1000>;
> + frame-number = <0>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + frame@17813000 {
> + reg = <0x0 0x17813000 0x1000>;
> + frame-number = <1>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + frame@17815000 {
> + reg = <0x0 0x17815000 0x1000>;
> + frame-number = <2>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + frame@17817000 {
> + reg = <0x0 0x17817000 0x1000>;
> + frame-number = <3>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + frame@17819000 {
> + reg = <0x0 0x17819000 0x1000>;
> + frame-number = <4>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + frame@1781b000 {
> + reg = <0x0 0x1781b000 0x1000>;
> + frame-number = <5>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + frame@1781d000 {
> + reg = <0x0 0x1781d000 0x1000>;
> + frame-number = <6>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> + };
> +
> + apps_rsc: rsc@18900000 {
> + compatible = "qcom,rpmh-rsc";
> + reg = <0x0 0x18900000 0x0 0x10000>,
> + <0x0 0x18910000 0x0 0x10000>,
> + <0x0 0x18920000 0x0 0x10000>;
> + reg-names = "drv-0",
> + "drv-1",
> + "drv-2";
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> +
> + power-domains = <&system_pd>;
> + label = "apps_rsc";
> +
> + qcom,tcs-offset = <0xd00>;
> + qcom,drv-id = <2>;
> + qcom,tcs-config = <ACTIVE_TCS 3>,
> + <SLEEP_TCS 2>,
> + <WAKE_TCS 2>,
> + <CONTROL_TCS 0>;
> +
> + apps_bcm_voter: bcm-voter {
> + compatible = "qcom,bcm-voter";
> + };
> +
> + rpmhcc: clock-controller {
> + compatible = "qcom,kaanapali-rpmh-clk";
> + #clock-cells = <1>;
> + clocks = <&xo_board>;
> + clock-names = "xo";
> + };
> +
> + rpmhpd: power-controller {
> + compatible = "qcom,kaanapali-rpmhpd";
> +
> + operating-points-v2 = <&rpmhpd_opp_table>;
> +
> + #power-domain-cells = <1>;
> +
> + rpmhpd_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + rpmhpd_opp_ret: opp-16 {
> + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
> + };
> +
> + rpmhpd_opp_low_svs_d3: opp-50 {
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
> + };
> +
> + rpmhpd_opp_low_svs_d2_1: opp-51 {
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2_1>;
> + };
> +
> + rpmhpd_opp_low_svs_d2: opp-52 {
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
> + };
> +
> + rpmhpd_opp_low_svs_d1_1: opp-54 {
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1_1>;
> + };
> +
> + rpmhpd_opp_low_svs_d1: opp-56 {
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
> + };
> +
> + rpmhpd_opp_low_svs_d0: opp-60 {
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
> + };
> +
> + rpmhpd_opp_low_svs: opp-64 {
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + };
> +
> + rpmhpd_opp_low_svs_l0: opp-76 {
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L0>;
> + };
> +
> + rpmhpd_opp_low_svs_l1: opp-80 {
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
> + };
> +
> + rpmhpd_opp_low_svs_l2: opp-96 {
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>;
> + };
> +
> + rpmhpd_opp_svs: opp-128 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + };
> +
> + rpmhpd_opp_svs_l0: opp-144 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
> + };
> +
> + rpmhpd_opp_svs_l1: opp-192 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + };
> +
> + rpmhpd_opp_svs_l2: opp-224 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
> + };
> +
> + rpmhpd_opp_nom: opp-256 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> + };
> +
> + rpmhpd_opp_nom_l1: opp-320 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> + };
> +
> + rpmhpd_opp_nom_l2: opp-336 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
> + };
> +
> + rpmhpd_opp_turbo: opp-384 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> + };
> +
> + rpmhpd_opp_turbo_l0: opp-400 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L0>;
> + };
> +
> + rpmhpd_opp_turbo_l1: opp-416 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> + };
> +
> + rpmhpd_opp_turbo_l2: opp-432 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
> + };
> +
> + rpmhpd_opp_turbo_l3: opp-448 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
> + };
> +
> + rpmhpd_opp_turbo_l4: opp-452 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
> + };
> +
> + rpmhpd_opp_turbo_l5: opp-456 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>;
> + };
> +
> + rpmhpd_opp_super_turbo_no_cpr: opp-480 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>;
> + };
> + };
> + };
> + };
> +
> + nsp_noc: interconnect@260c0000 {
> + compatible = "qcom,kaanapali-nsp-noc";
> + reg = <0x0 0x260c0000 0x0 0x21280>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + #interconnect-cells = <2>;
> + };
> +
> + /* Cluster 0 */
> + pmu@310b3400 {
> + compatible = "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon";
> + reg = <0x0 0x310b3400 0x0 0x600>;
> +
> + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
> +
> + operating-points-v2 = <&cpu_bwmon_opp_table>;
> +
> + cpu_bwmon_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-0 {
> + opp-peak-kBps = <2188000>;
> + };
> +
> + opp-1 {
> + opp-peak-kBps = <5412000>;
> + };
> +
> + opp-2 {
> + opp-peak-kBps = <6220000>;
> + };
> +
> + opp-3 {
> + opp-peak-kBps = <6832000>;
> + };
> +
> + opp-4 {
> + opp-peak-kBps = <8368000>;
> + };
> +
> + opp-5 {
> + opp-peak-kBps = <10944000>;
> + };
> +
> + opp-6 {
> + opp-peak-kBps = <12748000>;
> + };
> +
> + opp-7 {
> + opp-peak-kBps = <14744000>;
> + };
> +
> + opp-8 {
> + opp-peak-kBps = <16896000>;
> + };
> +
> + opp-9 {
> + opp-peak-kBps = <19120000>;
> + };
> +
> + opp-10 {
> + opp-peak-kBps = <21332000>;
> + };
> + };
> + };
> +
> + /* Cluster 1 */
> + pmu@310b7400 {
> + compatible = "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon";
> + reg = <0x0 0x310b7400 0x0 0x600>;
> +
> + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
> +
> + operating-points-v2 = <&cpu_bwmon_opp_table>;
> + };
> +
> + gem_noc: interconnect@31100000 {
> + compatible = "qcom,kaanapali-gem-noc";
> + reg = <0x0 0x31100000 0x0 0x153080>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + #interconnect-cells = <2>;
> + };
> +
> + system-cache-controller@31800000 {
> + compatible = "qcom,kaanapali-llcc";
> + reg = <0x0 0x31800000 0x0 0x200000>,
> + <0x0 0x32800000 0x0 0x200000>,
> + <0x0 0x31c00000 0x0 0x200000>,
> + <0x0 0x32c00000 0x0 0x200000>,
> + <0x0 0x34800000 0x0 0x200000>,
> + <0x0 0x34c00000 0x0 0x200000>;
> + reg-names = "llcc0_base",
> + "llcc1_base",
> + "llcc2_base",
> + "llcc3_base",
> + "llcc_broadcast_base",
> + "llcc_broadcast_and_base";
> +
> + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + sram: sram@81f08000 {
> + compatible = "mmio-sram";
> + reg = <0x0 0x81f08000 0x0 0x200>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x0 0x81f08000 0x200>;
> +
> + pdp_rx: scp-sram-section@0 {
> + compatible = "arm,scmi-shmem";
> + reg = <0x0 0x80>;
> + };
> +
> + pdp_tx: scp-sram-section@100 {
> + compatible = "arm,scmi-shmem";
> + reg = <0x100 0x80>;
> + };
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> +
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> + };
> +};
>
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 02/20] arm64: dts: qcom: Introduce Kaanapali SoC
2025-10-14 11:46 ` Akhil P Oommen
@ 2025-11-04 9:04 ` Jingyi Wang
2025-11-04 12:54 ` Konrad Dybcio
0 siblings, 1 reply; 135+ messages in thread
From: Jingyi Wang @ 2025-11-04 9:04 UTC (permalink / raw)
To: Akhil P Oommen, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Tengfei Fan
On 10/14/2025 7:46 PM, Akhil P Oommen wrote:
>
>
> On 9/25/2025 5:47 AM, Jingyi Wang wrote:
>> Kaanapali is Snapdragon SoC from Qualcomm.
>>
<...>
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>
> This is missing a bunch of reserved regions which causes device crash when you stress memory allocation.
>
> -Akhil.
>
Hi Akhil,
We will not add all the reserved-memory in dts, other regions are designed to
be added in bootloader.
Thanks,
Jingyi
>> + pdp_mem: pdp_region@81300000 {
>> + reg = <0x0 0x81300000 0x0 0x100000>;
>> + no-map;
>> + };
>> +
<...>
>
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 02/20] arm64: dts: qcom: Introduce Kaanapali SoC
2025-11-04 9:04 ` Jingyi Wang
@ 2025-11-04 12:54 ` Konrad Dybcio
2025-11-05 7:30 ` Jingyi Wang
0 siblings, 1 reply; 135+ messages in thread
From: Konrad Dybcio @ 2025-11-04 12:54 UTC (permalink / raw)
To: Jingyi Wang, Akhil P Oommen, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Tengfei Fan
On 11/4/25 10:04 AM, Jingyi Wang wrote:
>
>
> On 10/14/2025 7:46 PM, Akhil P Oommen wrote:
>>
>>
>> On 9/25/2025 5:47 AM, Jingyi Wang wrote:
>>> Kaanapali is Snapdragon SoC from Qualcomm.
>>>
> <...>
>>> +
>>> + reserved-memory {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + ranges;
>>> +
>>
>> This is missing a bunch of reserved regions which causes device crash when you stress memory allocation.
>>
>> -Akhil.
>>
>
> Hi Akhil,
>
> We will not add all the reserved-memory in dts, other regions are designed to
> be added in bootloader.
If what Akhil says is true and Linux is crashing, something must be
wrong..
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 02/20] arm64: dts: qcom: Introduce Kaanapali SoC
2025-11-04 12:54 ` Konrad Dybcio
@ 2025-11-05 7:30 ` Jingyi Wang
2025-11-05 10:13 ` Konrad Dybcio
0 siblings, 1 reply; 135+ messages in thread
From: Jingyi Wang @ 2025-11-05 7:30 UTC (permalink / raw)
To: Konrad Dybcio, Akhil P Oommen, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Tengfei Fan
On 11/4/2025 8:54 PM, Konrad Dybcio wrote:
> On 11/4/25 10:04 AM, Jingyi Wang wrote:
>>
>>
>> On 10/14/2025 7:46 PM, Akhil P Oommen wrote:
>>>
>>>
>>> On 9/25/2025 5:47 AM, Jingyi Wang wrote:
>>>> Kaanapali is Snapdragon SoC from Qualcomm.
>>>>
>> <...>
>>>> +
>>>> + reserved-memory {
>>>> + #address-cells = <2>;
>>>> + #size-cells = <2>;
>>>> + ranges;
>>>> +
>>>
>>> This is missing a bunch of reserved regions which causes device crash when you stress memory allocation.
>>>
>>> -Akhil.
>>>
>>
>> Hi Akhil,
>>
>> We will not add all the reserved-memory in dts, other regions are designed to
>> be added in bootloader.
>
> If what Akhil says is true and Linux is crashing, something must be
> wrong..
>
> Konrad
Hi Konrad,
There was discussion about the reserved memory in QCS8550 change.
And the conclusion is that reserved memory regions which aren't relevant to
the kernel(like the hypervisor region) don't need to be described in DT to avoid
memory map change and update frequently. These regions will be runtime added
through bootloader.
ref:https://lore.kernel.org/all/20240618072202.2516025-3-quic_tengfan@quicinc.com/
The bootloader we currently use for Kaanapali has not supported this, and we have
solutions like add temp change to add these in DTS until the final bootloader is
provided.
Thanks,
Jingyi
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 02/20] arm64: dts: qcom: Introduce Kaanapali SoC
2025-11-05 7:30 ` Jingyi Wang
@ 2025-11-05 10:13 ` Konrad Dybcio
0 siblings, 0 replies; 135+ messages in thread
From: Konrad Dybcio @ 2025-11-05 10:13 UTC (permalink / raw)
To: Jingyi Wang, Akhil P Oommen, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Tengfei Fan
On 11/5/25 8:30 AM, Jingyi Wang wrote:
>
>
> On 11/4/2025 8:54 PM, Konrad Dybcio wrote:
>> On 11/4/25 10:04 AM, Jingyi Wang wrote:
>>>
>>>
>>> On 10/14/2025 7:46 PM, Akhil P Oommen wrote:
>>>>
>>>>
>>>> On 9/25/2025 5:47 AM, Jingyi Wang wrote:
>>>>> Kaanapali is Snapdragon SoC from Qualcomm.
>>>>>
>>> <...>
>>>>> +
>>>>> + reserved-memory {
>>>>> + #address-cells = <2>;
>>>>> + #size-cells = <2>;
>>>>> + ranges;
>>>>> +
>>>>
>>>> This is missing a bunch of reserved regions which causes device crash when you stress memory allocation.
>>>>
>>>> -Akhil.
>>>>
>>>
>>> Hi Akhil,
>>>
>>> We will not add all the reserved-memory in dts, other regions are designed to
>>> be added in bootloader.
>>
>> If what Akhil says is true and Linux is crashing, something must be
>> wrong..
>>
>> Konrad
>
> Hi Konrad,
>
> There was discussion about the reserved memory in QCS8550 change.
> And the conclusion is that reserved memory regions which aren't relevant to
> the kernel(like the hypervisor region) don't need to be described in DT to avoid
> memory map change and update frequently. These regions will be runtime added
> through bootloader.
>
> ref:https://lore.kernel.org/all/20240618072202.2516025-3-quic_tengfan@quicinc.com/
>
> The bootloader we currently use for Kaanapali has not supported this, and we have
> solutions like add temp change to add these in DTS until the final bootloader is
> provided.
I think we're well past that date though? OnePlus website says I can order
their new flagship next week..
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 02/20] arm64: dts: qcom: Introduce Kaanapali SoC
2025-09-25 0:17 ` [PATCH 02/20] arm64: dts: qcom: Introduce Kaanapali SoC Jingyi Wang
2025-09-25 3:22 ` Dmitry Baryshkov
2025-10-14 11:46 ` Akhil P Oommen
@ 2025-11-20 6:53 ` Komal Bajaj
2025-11-20 7:22 ` Jingyi Wang
2 siblings, 1 reply; 135+ messages in thread
From: Komal Bajaj @ 2025-11-20 6:53 UTC (permalink / raw)
To: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Tengfei Fan
On 9/25/2025 5:47 AM, Jingyi Wang wrote:
> Kaanapali is Snapdragon SoC from Qualcomm.
>
> Features added in this patch:
> - CPUs with PSCI idle states and cpufreq
> - Interrupt-controller with PDC wakeup support
> - Timers, TCSR Clock Controllers
> - Reserved Shared memory
> - GCC and RPMHCC
> - TLMM
> - Interconnect with CPU BWMONs
> - QuP with uart
> - SMMU
> - RPMHPD
> - UFS with Inline Crypto Engine
> - LLCC
> - Watchdog
>
> Written with help from Raviteja Laggyshetty(added interconnect nodes),
> Taniya Das(added Clock Controllers and cpufreq), Jishnu Prakash
> (added rpmhpd), Nitin Rawat(added ufs) and Gaurav Kashyap(added ICE).
>
> Co-developed-by: Tengfei Fan <tengfei.fan@oss.qualcomm.com>
> Signed-off-by: Tengfei Fan <tengfei.fan@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1320 +++++++++++++++++++++++++++++++
> 1 file changed, 1320 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> new file mode 100644
> index 000000000000..b385b4642883
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> @@ -0,0 +1,1320 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <dt-bindings/clock/qcom,kaanapali-gcc.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
> +#include <dt-bindings/firmware/qcom,scm.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interconnect/qcom,icc.h>
> +#include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/mailbox/qcom-ipcc.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
Missed to include "kaanapali-ipcc.h"
---
Thanks
Komal
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 02/20] arm64: dts: qcom: Introduce Kaanapali SoC
2025-11-20 6:53 ` Komal Bajaj
@ 2025-11-20 7:22 ` Jingyi Wang
0 siblings, 0 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-11-20 7:22 UTC (permalink / raw)
To: Komal Bajaj, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Tengfei Fan
On 11/20/2025 2:53 PM, Komal Bajaj wrote:
>
> On 9/25/2025 5:47 AM, Jingyi Wang wrote:
>> Kaanapali is Snapdragon SoC from Qualcomm.
>>
>> Features added in this patch:
>> - CPUs with PSCI idle states and cpufreq
>> - Interrupt-controller with PDC wakeup support
>> - Timers, TCSR Clock Controllers
>> - Reserved Shared memory
>> - GCC and RPMHCC
>> - TLMM
>> - Interconnect with CPU BWMONs
>> - QuP with uart
>> - SMMU
>> - RPMHPD
>> - UFS with Inline Crypto Engine
>> - LLCC
>> - Watchdog
>>
>> Written with help from Raviteja Laggyshetty(added interconnect nodes),
>> Taniya Das(added Clock Controllers and cpufreq), Jishnu Prakash
>> (added rpmhpd), Nitin Rawat(added ufs) and Gaurav Kashyap(added ICE).
>>
>> Co-developed-by: Tengfei Fan <tengfei.fan@oss.qualcomm.com>
>> Signed-off-by: Tengfei Fan <tengfei.fan@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1320 +++++++++++++++++++++++++++++++
>> 1 file changed, 1320 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>> new file mode 100644
>> index 000000000000..b385b4642883
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>> @@ -0,0 +1,1320 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>> + */
>> +
>> +#include <dt-bindings/clock/qcom,kaanapali-gcc.h>
>> +#include <dt-bindings/clock/qcom,rpmh.h>
>> +#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
>> +#include <dt-bindings/firmware/qcom,scm.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/interconnect/qcom,icc.h>
>> +#include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/mailbox/qcom-ipcc.h>
>> +#include <dt-bindings/power/qcom-rpmpd.h>
>> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
>
> Missed to include "kaanapali-ipcc.h"
>
"kaanapali-ipcc.h" is added in the IPCC v3:
https://lore.kernel.org/all/20251031-knp-ipcc-v3-0-62ffb4168dff@oss.qualcomm.com/
so this file will be included in the next version for dts
Thanks,
Jingyi
> ---
> Thanks
> Komal
>
^ permalink raw reply [flat|nested] 135+ messages in thread
* [PATCH 03/20] arm64: dts: qcom: kaanapali: Add base MTP board
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
2025-09-25 0:17 ` [PATCH 01/20] dt-bindings: arm: qcom: Document Kaanapali SoC and its reference boards Jingyi Wang
2025-09-25 0:17 ` [PATCH 02/20] arm64: dts: qcom: Introduce Kaanapali SoC Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-09-25 3:18 ` Dmitry Baryshkov
2025-09-25 9:44 ` Konrad Dybcio
2025-09-25 0:17 ` [PATCH 04/20] arm64: dts: qcom: kaanapali: Add support for PCIe0 on Kaanapali Jingyi Wang
` (19 subsequent siblings)
22 siblings, 2 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang
Add initial support for Qualcomm Kaanapali MTP board which enables DSPs,
UFS and booting to shell with uart console.
Written with help from Jishnu Prakash (added rpmhpd nodes) and Nitin Rawat
(added ufs).
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 704 +++++++++++++++++++++++++++++
2 files changed, 705 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index d7f22476d510..7edfa5fa00fc 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb
+dtb-$(CONFIG_ARCH_QCOM) += kaanapali-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb
lemans-evk-camera-csi1-imx577-dtbs := lemans-evk.dtb lemans-evk-camera-csi1-imx577.dtbo
diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
new file mode 100644
index 000000000000..9cf3158e2712
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
@@ -0,0 +1,704 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "kaanapali.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Kaanapali MTP";
+ compatible = "qcom,kaanapali-mtp", "qcom,kaanapali";
+ chassis-type = "handset";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <76800000>;
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32764>;
+ #clock-cells = <0>;
+ };
+
+ bi_tcxo_div2: bi-tcxo-div2-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK_A>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pmh0101-rpmh-regulators";
+
+ qcom,pmic-id = "B_E0";
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <4000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <3552000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3048000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l4b_1p8: ldo4 {
+ regulator-name = "vreg_l4b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3148000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10b_1p8: ldo10 {
+ regulator-name = "vreg_l10b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l11b_1p0: ldo11 {
+ regulator-name = "vreg_l11b_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1292000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18b_1p2: ldo18 {
+ regulator-name = "vreg_l18b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+
+ qcom,pmic-id = "D_E0";
+
+ vreg_s10d_1p0: smps10 {
+ regulator-name = "vreg_s10d_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1d_1p2: ldo1 {
+ regulator-name = "vreg_l1d_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1256000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l2d_0p9: ldo2 {
+ regulator-name = "vreg_l2d_0p9";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <958000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l3d_0p8: ldo3 {
+ regulator-name = "vreg_l3d_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l4d_1p2: ldo4 {
+ regulator-name = "vreg_l4d_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+
+ qcom,pmic-id = "F_E0";
+
+ vreg_s6f_0p5: smps6 {
+ regulator-name = "vreg_s6f_0p5";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <570000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s7f_1p2: smps7 {
+ regulator-name = "vreg_s7f_1p2";
+ regulator-min-microvolt = <1224000>;
+ regulator-max-microvolt = <1372000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s8f_1p8: smps8 {
+ regulator-name = "vreg_s8f_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_1p2: ldo1 {
+ regulator-name = "vreg_l1f_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l2f_1p2: ldo2 {
+ regulator-name = "vreg_l2f_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l3f_0p8: ldo3 {
+ regulator-name = "vreg_l3f_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <936000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l4f_0p8: ldo4 {
+ regulator-name = "vreg_l4f_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+
+ qcom,pmic-id = "G_E0";
+
+ vreg_s7g_0p9: smps7 {
+ regulator-name = "vreg_s7g_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s9g_1p0: smps9 {
+ regulator-name = "vreg_s9g_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1g_1p2: ldo1 {
+ regulator-name = "vreg_l1g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l2g_1p8: ldo2 {
+ regulator-name = "vreg_l2g_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l4g_0p9: ldo4 {
+ regulator-name = "vreg_l4g_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+
+ qcom,pmic-id = "I_E0";
+
+ vreg_s7i_0p9: smps7 {
+ regulator-name = "vreg_s7i_0p9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <972000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2i_1p2: ldo2 {
+ regulator-name = "vreg_l2i_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l3i_0p8: ldo3 {
+ regulator-name = "vreg_l3i_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pmh0104-rpmh-regulators";
+
+ qcom,pmic-id = "J_E1";
+
+ vreg_s1j_0p8: smps1 {
+ regulator-name = "vreg_s1j_0p8";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2j_0p8: smps2 {
+ regulator-name = "vreg_s2j_0p8";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3j_1p2: smps3 {
+ regulator-name = "vreg_s3j_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4j_0p7: smps4 {
+ regulator-name = "vreg_s4j_0p7";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pmr735d-rpmh-regulators";
+
+ qcom,pmic-id = "K_E1";
+
+ vreg_l1k_0p8: ldo1 {
+ regulator-name = "vreg_l1k_0p8";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2k_0p7: ldo2 {
+ regulator-name = "vreg_l2k_0p7";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3k_1p2: ldo3 {
+ regulator-name = "vreg_l3k_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4k_1p0: ldo4 {
+ regulator-name = "vreg_l4k_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5k_0p7: ldo5 {
+ regulator-name = "vreg_l5k_0p7";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6k_1p7: ldo6 {
+ regulator-name = "vreg_l6k_1p7";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7k_0p7: ldo7 {
+ regulator-name = "vreg_l7k_0p7";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <848000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+
+ qcom,pmic-id = "M_E1";
+
+ vreg_l1m_1p0: ldo1 {
+ regulator-name = "vreg_l1m_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m_1p0: ldo2 {
+ regulator-name = "vreg_l2m_1p0";
+ regulator-min-microvolt = <1096000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m_2p8: ldo3 {
+ regulator-name = "vreg_l3m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m_2p2: ldo4 {
+ regulator-name = "vreg_l4m_2p2";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m_2p8: ldo6 {
+ regulator-name = "vreg_l6m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p8: ldo7 {
+ regulator-name = "vreg_l7m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-8 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+
+ qcom,pmic-id = "N_E1";
+
+ vreg_l1n_1p1: ldo1 {
+ regulator-name = "vreg_l1n_1p1";
+ regulator-min-microvolt = <1096000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n_1p2: ldo2 {
+ regulator-name = "vreg_l2n_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n_1p8: ldo3 {
+ regulator-name = "vreg_l3n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n_1p8: ldo4 {
+ regulator-name = "vreg_l4n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n_2p8: ldo5 {
+ regulator-name = "vreg_l5n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n_2p8: ldo6 {
+ regulator-name = "vreg_l6n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n_3p3: ldo7 {
+ regulator-name = "vreg_l7n_3p3";
+ regulator-min-microvolt = <3304000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&tlmm {
+ gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */
+ <74 1>, /* eSE */
+ <119 2>, /* SoCCP */
+ <144 4>; /* CXM UART */
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 217 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1200000>;
+ vccq-supply = <&vreg_l4d_1p2>;
+ vccq-max-microamp = <1200000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l4g_0p9>;
+ vdda-pll-supply = <&vreg_l1d_1p2>;
+
+ status = "okay";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* Re: [PATCH 03/20] arm64: dts: qcom: kaanapali: Add base MTP board
2025-09-25 0:17 ` [PATCH 03/20] arm64: dts: qcom: kaanapali: Add base MTP board Jingyi Wang
@ 2025-09-25 3:18 ` Dmitry Baryshkov
2025-09-25 7:17 ` Aiqun(Maria) Yu
2025-09-25 9:44 ` Konrad Dybcio
1 sibling, 1 reply; 135+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 3:18 UTC (permalink / raw)
To: Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On Wed, Sep 24, 2025 at 05:17:20PM -0700, Jingyi Wang wrote:
> Add initial support for Qualcomm Kaanapali MTP board which enables DSPs,
It doesn't
> UFS and booting to shell with uart console.
>
> Written with help from Jishnu Prakash (added rpmhpd nodes) and Nitin Rawat
> (added ufs).
>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 704 +++++++++++++++++++++++++++++
> 2 files changed, 705 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index d7f22476d510..7edfa5fa00fc 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += kaanapali-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb
>
> lemans-evk-camera-csi1-imx577-dtbs := lemans-evk.dtb lemans-evk-camera-csi1-imx577.dtbo
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> new file mode 100644
> index 000000000000..9cf3158e2712
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> @@ -0,0 +1,704 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +#include "kaanapali.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. Kaanapali MTP";
> + compatible = "qcom,kaanapali-mtp", "qcom,kaanapali";
> + chassis-type = "handset";
> +
> + aliases {
> + serial0 = &uart7;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + clocks {
> + xo_board: xo-board {
> + compatible = "fixed-clock";
> + clock-frequency = <76800000>;
> + #clock-cells = <0>;
> + };
> +
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32764>;
> + #clock-cells = <0>;
> + };
> +
> + bi_tcxo_div2: bi-tcxo-div2-clk {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-mult = <1>;
> + clock-div = <2>;
> + };
> +
> + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK_A>;
> + clock-mult = <1>;
> + clock-div = <2>;
> + };
> + };
> +};
> +
> +&apps_rsc {
> + regulators-0 {
> + compatible = "qcom,pmh0101-rpmh-regulators";
> +
> + qcom,pmic-id = "B_E0";
> +
> + vreg_bob1: bob1 {
> + regulator-name = "vreg_bob1";
> + regulator-min-microvolt = <3008000>;
> + regulator-max-microvolt = <4000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_bob2: bob2 {
> + regulator-name = "vreg_bob2";
> + regulator-min-microvolt = <2704000>;
> + regulator-max-microvolt = <3552000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l1b_1p8: ldo1 {
> + regulator-name = "vreg_l1b_1p8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l2b_3p0: ldo2 {
> + regulator-name = "vreg_l2b_3p0";
> + regulator-min-microvolt = <3008000>;
> + regulator-max-microvolt = <3048000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l4b_1p8: ldo4 {
> + regulator-name = "vreg_l4b_1p8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l5b_3p1: ldo5 {
> + regulator-name = "vreg_l5b_3p1";
> + regulator-min-microvolt = <3100000>;
> + regulator-max-microvolt = <3148000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l6b_1p8: ldo6 {
> + regulator-name = "vreg_l6b_1p8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3008000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l7b_1p8: ldo7 {
> + regulator-name = "vreg_l7b_1p8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3008000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l8b_1p8: ldo8 {
> + regulator-name = "vreg_l8b_1p8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3008000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l9b_2p9: ldo9 {
> + regulator-name = "vreg_l9b_2p9";
> + regulator-min-microvolt = <2960000>;
> + regulator-max-microvolt = <3008000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l10b_1p8: ldo10 {
> + regulator-name = "vreg_l10b_1p8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l11b_1p0: ldo11 {
> + regulator-name = "vreg_l11b_1p0";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1292000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l12b_1p8: ldo12 {
> + regulator-name = "vreg_l12b_1p8";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l13b_3p0: ldo13 {
> + regulator-name = "vreg_l13b_3p0";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l14b_3p2: ldo14 {
> + regulator-name = "vreg_l14b_3p2";
> + regulator-min-microvolt = <3200000>;
> + regulator-max-microvolt = <3200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l15b_1p8: ldo15 {
> + regulator-name = "vreg_l15b_1p8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l17b_2p5: ldo17 {
> + regulator-name = "vreg_l17b_2p5";
> + regulator-min-microvolt = <2504000>;
> + regulator-max-microvolt = <2504000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l18b_1p2: ldo18 {
> + regulator-name = "vreg_l18b_1p2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> + };
> +
> + regulators-1 {
> + compatible = "qcom,pmh0110-rpmh-regulators";
> +
> + qcom,pmic-id = "D_E0";
> +
> + vreg_s10d_1p0: smps10 {
> + regulator-name = "vreg_s10d_1p0";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l1d_1p2: ldo1 {
> + regulator-name = "vreg_l1d_1p2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1256000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l2d_0p9: ldo2 {
> + regulator-name = "vreg_l2d_0p9";
> + regulator-min-microvolt = <912000>;
> + regulator-max-microvolt = <958000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l3d_0p8: ldo3 {
> + regulator-name = "vreg_l3d_0p8";
> + regulator-min-microvolt = <880000>;
> + regulator-max-microvolt = <880000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l4d_1p2: ldo4 {
> + regulator-name = "vreg_l4d_1p2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> + };
> +
> + regulators-2 {
> + compatible = "qcom,pmh0110-rpmh-regulators";
> +
> + qcom,pmic-id = "F_E0";
> +
> + vreg_s6f_0p5: smps6 {
> + regulator-name = "vreg_s6f_0p5";
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <570000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_s7f_1p2: smps7 {
> + regulator-name = "vreg_s7f_1p2";
> + regulator-min-microvolt = <1224000>;
> + regulator-max-microvolt = <1372000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_s8f_1p8: smps8 {
> + regulator-name = "vreg_s8f_1p8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l1f_1p2: ldo1 {
> + regulator-name = "vreg_l1f_1p2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l2f_1p2: ldo2 {
> + regulator-name = "vreg_l2f_1p2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l3f_0p8: ldo3 {
> + regulator-name = "vreg_l3f_0p8";
> + regulator-min-microvolt = <880000>;
> + regulator-max-microvolt = <936000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l4f_0p8: ldo4 {
> + regulator-name = "vreg_l4f_0p8";
> + regulator-min-microvolt = <880000>;
> + regulator-max-microvolt = <912000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> + };
> +
> + regulators-3 {
> + compatible = "qcom,pmh0110-rpmh-regulators";
> +
> + qcom,pmic-id = "G_E0";
> +
> + vreg_s7g_0p9: smps7 {
> + regulator-name = "vreg_s7g_0p9";
> + regulator-min-microvolt = <880000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_s9g_1p0: smps9 {
> + regulator-name = "vreg_s9g_1p0";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l1g_1p2: ldo1 {
> + regulator-name = "vreg_l1g_1p2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l2g_1p8: ldo2 {
> + regulator-name = "vreg_l2g_1p8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l3g_1p2: ldo3 {
> + regulator-name = "vreg_l3g_1p2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l4g_0p9: ldo4 {
> + regulator-name = "vreg_l4g_0p9";
> + regulator-min-microvolt = <880000>;
> + regulator-max-microvolt = <920000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> + };
> +
> + regulators-4 {
> + compatible = "qcom,pmh0110-rpmh-regulators";
> +
> + qcom,pmic-id = "I_E0";
> +
> + vreg_s7i_0p9: smps7 {
> + regulator-name = "vreg_s7i_0p9";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <972000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l2i_1p2: ldo2 {
> + regulator-name = "vreg_l2i_1p2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l3i_0p8: ldo3 {
> + regulator-name = "vreg_l3i_0p8";
> + regulator-min-microvolt = <880000>;
> + regulator-max-microvolt = <920000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_AUTO>;
> + };
> + };
> +
> + regulators-5 {
> + compatible = "qcom,pmh0104-rpmh-regulators";
> +
> + qcom,pmic-id = "J_E1";
> +
> + vreg_s1j_0p8: smps1 {
> + regulator-name = "vreg_s1j_0p8";
> + regulator-min-microvolt = <400000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_s2j_0p8: smps2 {
> + regulator-name = "vreg_s2j_0p8";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_s3j_1p2: smps3 {
> + regulator-name = "vreg_s3j_1p2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_s4j_0p7: smps4 {
> + regulator-name = "vreg_s4j_0p7";
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> + };
> +
> + regulators-6 {
> + compatible = "qcom,pmr735d-rpmh-regulators";
> +
> + qcom,pmic-id = "K_E1";
> +
> + vreg_l1k_0p8: ldo1 {
> + regulator-name = "vreg_l1k_0p8";
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l2k_0p7: ldo2 {
> + regulator-name = "vreg_l2k_0p7";
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l3k_1p2: ldo3 {
> + regulator-name = "vreg_l3k_1p2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l4k_1p0: ldo4 {
> + regulator-name = "vreg_l4k_1p0";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l5k_0p7: ldo5 {
> + regulator-name = "vreg_l5k_0p7";
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l6k_1p7: ldo6 {
> + regulator-name = "vreg_l6k_1p7";
> + regulator-min-microvolt = <1700000>;
> + regulator-max-microvolt = <2000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l7k_0p7: ldo7 {
> + regulator-name = "vreg_l7k_0p7";
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <848000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_HPM>;
> + };
> + };
> +
> + regulators-7 {
> + compatible = "qcom,pm8010-rpmh-regulators";
> +
> + qcom,pmic-id = "M_E1";
> +
> + vreg_l1m_1p0: ldo1 {
> + regulator-name = "vreg_l1m_1p0";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l2m_1p0: ldo2 {
> + regulator-name = "vreg_l2m_1p0";
> + regulator-min-microvolt = <1096000>;
> + regulator-max-microvolt = <1104000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l3m_2p8: ldo3 {
> + regulator-name = "vreg_l3m_2p8";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2900000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l4m_2p2: ldo4 {
> + regulator-name = "vreg_l4m_2p2";
> + regulator-min-microvolt = <2200000>;
> + regulator-max-microvolt = <2200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l6m_2p8: ldo6 {
> + regulator-name = "vreg_l6m_2p8";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l7m_2p8: ldo7 {
> + regulator-name = "vreg_l7m_2p8";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> + };
> +
> + regulators-8 {
> + compatible = "qcom,pm8010-rpmh-regulators";
> +
> + qcom,pmic-id = "N_E1";
> +
> + vreg_l1n_1p1: ldo1 {
> + regulator-name = "vreg_l1n_1p1";
> + regulator-min-microvolt = <1096000>;
> + regulator-max-microvolt = <1104000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l2n_1p2: ldo2 {
> + regulator-name = "vreg_l2n_1p2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-allow-set-load;
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> + RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l3n_1p8: ldo3 {
> + regulator-name = "vreg_l3n_1p8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l4n_1p8: ldo4 {
> + regulator-name = "vreg_l4n_1p8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l5n_2p8: ldo5 {
> + regulator-name = "vreg_l5n_2p8";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l6n_2p8: ldo6 {
> + regulator-name = "vreg_l6n_2p8";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l7n_3p3: ldo7 {
> + regulator-name = "vreg_l7n_3p3";
> + regulator-min-microvolt = <3304000>;
> + regulator-max-microvolt = <3304000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> + };
> +};
> +
> +&tlmm {
> + gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */
> + <74 1>, /* eSE */
> + <119 2>, /* SoCCP */
> + <144 4>; /* CXM UART */
> +};
> +
> +&uart7 {
> + status = "okay";
> +};
> +
> +&ufs_mem_hc {
> + reset-gpios = <&tlmm 217 GPIO_ACTIVE_LOW>;
> +
> + vcc-supply = <&vreg_l17b_2p5>;
> + vcc-max-microamp = <1200000>;
> + vccq-supply = <&vreg_l4d_1p2>;
> + vccq-max-microamp = <1200000>;
> +
> + status = "okay";
> +};
> +
> +&ufs_mem_phy {
> + vdda-phy-supply = <&vreg_l4g_0p9>;
> + vdda-pll-supply = <&vreg_l1d_1p2>;
> +
> + status = "okay";
> +};
>
> --
> 2.25.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 03/20] arm64: dts: qcom: kaanapali: Add base MTP board
2025-09-25 3:18 ` Dmitry Baryshkov
@ 2025-09-25 7:17 ` Aiqun(Maria) Yu
0 siblings, 0 replies; 135+ messages in thread
From: Aiqun(Maria) Yu @ 2025-09-25 7:17 UTC (permalink / raw)
To: Dmitry Baryshkov, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
tingwei.zhang, trilok.soni, yijie.yang
On 9/25/2025 11:18 AM, Dmitry Baryshkov wrote:
> On Wed, Sep 24, 2025 at 05:17:20PM -0700, Jingyi Wang wrote:
>> Add initial support for Qualcomm Kaanapali MTP board which enables DSPs,
>
> It doesn't
Thanks for pointing that out.
We had originally squashed a more complete set of features into the base
SoC patch. However, after an offline review with Bjorn, we decided to
split it into smaller patches to make the review process easier from
Bjorn’s perspective. Unfortunately, we missed addressing this part of
the comments during that split.
--
Thx and BRs,
Aiqun(Maria) Yu
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 03/20] arm64: dts: qcom: kaanapali: Add base MTP board
2025-09-25 0:17 ` [PATCH 03/20] arm64: dts: qcom: kaanapali: Add base MTP board Jingyi Wang
2025-09-25 3:18 ` Dmitry Baryshkov
@ 2025-09-25 9:44 ` Konrad Dybcio
1 sibling, 0 replies; 135+ messages in thread
From: Konrad Dybcio @ 2025-09-25 9:44 UTC (permalink / raw)
To: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang
On 9/25/25 2:17 AM, Jingyi Wang wrote:
> Add initial support for Qualcomm Kaanapali MTP board which enables DSPs,
> UFS and booting to shell with uart console.
>
> Written with help from Jishnu Prakash (added rpmhpd nodes) and Nitin Rawat
> (added ufs).
>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
With the commit message fixed:
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread
* [PATCH 04/20] arm64: dts: qcom: kaanapali: Add support for PCIe0 on Kaanapali
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (2 preceding siblings ...)
2025-09-25 0:17 ` [PATCH 03/20] arm64: dts: qcom: kaanapali: Add base MTP board Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-09-25 10:56 ` Konrad Dybcio
2025-10-06 14:23 ` Krzysztof Kozlowski
2025-09-25 0:17 ` [PATCH 05/20] arm64: dts: qcom: kaanapali: Add SDC2 nodes for Kaanapali soc Jingyi Wang
` (18 subsequent siblings)
22 siblings, 2 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang, Qiang Yu
From: Qiang Yu <qiang.yu@oss.qualcomm.com>
Describe PCIe0 controller and PHY. Also add required system resources like
regulators, clocks, interrupts and registers configuration for PCIe0.
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 182 +++++++++++++++++++++++++++++++-
1 file changed, 181 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index b385b4642883..07dc112065d1 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -452,7 +452,7 @@ gcc: clock-controller@100000 {
clocks = <&bi_tcxo_div2>,
<0>,
<&sleep_clk>,
- <0>,
+ <&pcie0_phy>,
<0>,
<0>,
<0>,
@@ -561,6 +561,186 @@ mmss_noc: interconnect@1780000 {
#interconnect-cells = <2>;
};
+ pcie0: pcie@1c00000 {
+ device_type = "pci";
+ compatible = "qcom,kaanapali-pcie", "qcom,pcie-sm8550";
+ reg = <0 0x01c00000 0 0x3000>,
+ <0 0x40000000 0 0xf1d>,
+ <0 0x40000f20 0 0xa8>,
+ <0 0x40001000 0 0x1000>,
+ <0 0x40100000 0 0x100000>,
+ <0 0x01c03000 0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>,
+ <0x02000000 0 0x40300000 0 0x40300000 0 0x23d00000>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+ <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "noc_aggr",
+ "cnoc_sf_axi";
+
+ resets = <&gcc GCC_PCIE_0_BCR>,
+ <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
+
+ interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ power-domains = <&gcc GCC_PCIE_0_GDSC>;
+
+ eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
+
+ operating-points-v2 = <&pcie0_opp_table>;
+
+ iommu-map = <0 &apps_smmu 0x1400 0x1>,
+ <0x100 &apps_smmu 0x1401 0x1>;
+
+ interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ #interrupt-cells = <1>;
+
+ msi-map = <0x0 &gic_its 0x1400 0x1>,
+ <0x100 &gic_its 0x1401 0x1>;
+ msi-map-mask = <0xff00>;
+ max-link-speed = <3>;
+ linux,pci-domain = <0>;
+ num-lanes = <2>;
+ bus-range = <0 0xff>;
+
+ dma-coherent;
+
+ status = "disabled";
+
+ pcie0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* GEN 1 x1 */
+ opp-2500000 {
+ opp-hz = /bits/ 64 <2500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <250000 1>;
+ };
+
+ /* GEN 1 x2 and GEN 2 x1 */
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <500000 1>;
+ };
+
+ /* GEN 2 x2 */
+ opp-10000000 {
+ opp-hz = /bits/ 64 <10000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1000000 1>;
+ };
+
+ /* GEN 3 x1 */
+ opp-8000000 {
+ opp-hz = /bits/ 64 <8000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <984500 1>;
+ };
+
+ /* GEN 3 x2 */
+ opp-16000000 {
+ opp-hz = /bits/ 64 <16000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <1969000 1>;
+ };
+ };
+
+ pcieport0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ phys = <&pcie0_phy>;
+ };
+ };
+
+ pcie0_phy: phy@1c06000 {
+ compatible = "qcom,kaanapali-qmp-gen3x2-pcie-phy";
+ reg = <0 0x01c06000 0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&tcsrcc TCSR_PCIE_0_CLKREF_EN>,
+ <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe";
+
+ assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>,
+ <&gcc GCC_PCIE_0_NOCSR_COM_PHY_BCR>;
+ reset-names = "phy",
+ "phy_nocsr";
+
+ power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie0_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
ufs_mem_phy: phy@1d80000 {
compatible = "qcom,kaanapali-qmp-ufs-phy", "qcom,sm8750-qmp-ufs-phy";
reg = <0x0 0x01d80000 0x0 0x2000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* Re: [PATCH 04/20] arm64: dts: qcom: kaanapali: Add support for PCIe0 on Kaanapali
2025-09-25 0:17 ` [PATCH 04/20] arm64: dts: qcom: kaanapali: Add support for PCIe0 on Kaanapali Jingyi Wang
@ 2025-09-25 10:56 ` Konrad Dybcio
2025-10-06 14:23 ` Krzysztof Kozlowski
1 sibling, 0 replies; 135+ messages in thread
From: Konrad Dybcio @ 2025-09-25 10:56 UTC (permalink / raw)
To: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Chaitanya Chundru
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Qiang Yu
On 9/25/25 2:17 AM, Jingyi Wang wrote:
> From: Qiang Yu <qiang.yu@oss.qualcomm.com>
>
> Describe PCIe0 controller and PHY. Also add required system resources like
> regulators, clocks, interrupts and registers configuration for PCIe0.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
[...]
> +
> + pcieport0: pcie@0 {
"pcie0_port0:"
> + device_type = "pci";
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + bus-range = <0x01 0xff>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> + phys = <&pcie0_phy>;
how about:
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie0_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
with that:
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 04/20] arm64: dts: qcom: kaanapali: Add support for PCIe0 on Kaanapali
2025-09-25 0:17 ` [PATCH 04/20] arm64: dts: qcom: kaanapali: Add support for PCIe0 on Kaanapali Jingyi Wang
2025-09-25 10:56 ` Konrad Dybcio
@ 2025-10-06 14:23 ` Krzysztof Kozlowski
2025-10-07 1:24 ` Dmitry Baryshkov
1 sibling, 1 reply; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-06 14:23 UTC (permalink / raw)
To: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Qiang Yu
On 25/09/2025 09:17, Jingyi Wang wrote:
> From: Qiang Yu <qiang.yu@oss.qualcomm.com>
>
> Describe PCIe0 controller and PHY. Also add required system resources like
> regulators, clocks, interrupts and registers configuration for PCIe0.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 182 +++++++++++++++++++++++++++++++-
> 1 file changed, 181 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> index b385b4642883..07dc112065d1 100644
> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> @@ -452,7 +452,7 @@ gcc: clock-controller@100000 {
> clocks = <&bi_tcxo_div2>,
> <0>,
> <&sleep_clk>,
> - <0>,
Why are you removing lines which you just added? What sort of buggy
patch was before?
> + <&pcie0_phy>,
> <0>,
> <0>,
> <0>,
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 04/20] arm64: dts: qcom: kaanapali: Add support for PCIe0 on Kaanapali
2025-10-06 14:23 ` Krzysztof Kozlowski
@ 2025-10-07 1:24 ` Dmitry Baryshkov
2025-10-07 1:46 ` Krzysztof Kozlowski
0 siblings, 1 reply; 135+ messages in thread
From: Dmitry Baryshkov @ 2025-10-07 1:24 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Qiang Yu
On Mon, Oct 06, 2025 at 11:23:23PM +0900, Krzysztof Kozlowski wrote:
> On 25/09/2025 09:17, Jingyi Wang wrote:
> > From: Qiang Yu <qiang.yu@oss.qualcomm.com>
> >
> > Describe PCIe0 controller and PHY. Also add required system resources like
> > regulators, clocks, interrupts and registers configuration for PCIe0.
> >
> > Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> > Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> > ---
> > arch/arm64/boot/dts/qcom/kaanapali.dtsi | 182 +++++++++++++++++++++++++++++++-
> > 1 file changed, 181 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> > index b385b4642883..07dc112065d1 100644
> > --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> > @@ -452,7 +452,7 @@ gcc: clock-controller@100000 {
> > clocks = <&bi_tcxo_div2>,
> > <0>,
> > <&sleep_clk>,
> > - <0>,
>
>
> Why are you removing lines which you just added? What sort of buggy
> patch was before?
Weirdly enough, it's correct: this patch adds clock provider, which gets
used by the GCC. You might argue about the split, but there is no bug
here.
>
> > + <&pcie0_phy>,
> > <0>,
> > <0>,
> > <0>,
>
>
> Best regards,
> Krzysztof
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 04/20] arm64: dts: qcom: kaanapali: Add support for PCIe0 on Kaanapali
2025-10-07 1:24 ` Dmitry Baryshkov
@ 2025-10-07 1:46 ` Krzysztof Kozlowski
2025-10-08 19:04 ` Dmitry Baryshkov
0 siblings, 1 reply; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-07 1:46 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Qiang Yu
On 07/10/2025 10:24, Dmitry Baryshkov wrote:
> On Mon, Oct 06, 2025 at 11:23:23PM +0900, Krzysztof Kozlowski wrote:
>> On 25/09/2025 09:17, Jingyi Wang wrote:
>>> From: Qiang Yu <qiang.yu@oss.qualcomm.com>
>>>
>>> Describe PCIe0 controller and PHY. Also add required system resources like
>>> regulators, clocks, interrupts and registers configuration for PCIe0.
>>>
>>> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 182 +++++++++++++++++++++++++++++++-
>>> 1 file changed, 181 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>>> index b385b4642883..07dc112065d1 100644
>>> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>>> @@ -452,7 +452,7 @@ gcc: clock-controller@100000 {
>>> clocks = <&bi_tcxo_div2>,
>>> <0>,
>>> <&sleep_clk>,
>>> - <0>,
>>
>>
>> Why are you removing lines which you just added? What sort of buggy
>> patch was before?
>
> Weirdly enough, it's correct: this patch adds clock provider, which gets
> used by the GCC. You might argue about the split, but there is no bug
> here.
Yes, I argue about the split. This is new SoC, so any patch removing
something from previous patches means split was done wrongly.
It's just confusing and previous patch (the one with lines removed here)
just shows incomplete picture.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 04/20] arm64: dts: qcom: kaanapali: Add support for PCIe0 on Kaanapali
2025-10-07 1:46 ` Krzysztof Kozlowski
@ 2025-10-08 19:04 ` Dmitry Baryshkov
0 siblings, 0 replies; 135+ messages in thread
From: Dmitry Baryshkov @ 2025-10-08 19:04 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Qiang Yu
On Tue, Oct 07, 2025 at 10:46:29AM +0900, Krzysztof Kozlowski wrote:
> On 07/10/2025 10:24, Dmitry Baryshkov wrote:
> > On Mon, Oct 06, 2025 at 11:23:23PM +0900, Krzysztof Kozlowski wrote:
> >> On 25/09/2025 09:17, Jingyi Wang wrote:
> >>> From: Qiang Yu <qiang.yu@oss.qualcomm.com>
> >>>
> >>> Describe PCIe0 controller and PHY. Also add required system resources like
> >>> regulators, clocks, interrupts and registers configuration for PCIe0.
> >>>
> >>> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> >>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> >>> ---
> >>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 182 +++++++++++++++++++++++++++++++-
> >>> 1 file changed, 181 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> >>> index b385b4642883..07dc112065d1 100644
> >>> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> >>> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> >>> @@ -452,7 +452,7 @@ gcc: clock-controller@100000 {
> >>> clocks = <&bi_tcxo_div2>,
> >>> <0>,
> >>> <&sleep_clk>,
> >>> - <0>,
> >>
> >>
> >> Why are you removing lines which you just added? What sort of buggy
> >> patch was before?
> >
> > Weirdly enough, it's correct: this patch adds clock provider, which gets
> > used by the GCC. You might argue about the split, but there is no bug
> > here.
>
>
> Yes, I argue about the split. This is new SoC, so any patch removing
> something from previous patches means split was done wrongly.
I agree that the split is weird. But it's not buggy. Anyway, let's wait
for the next iteration, which will hopefully sort out everything.
> It's just confusing and previous patch (the one with lines removed here)
> just shows incomplete picture.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 135+ messages in thread
* [PATCH 05/20] arm64: dts: qcom: kaanapali: Add SDC2 nodes for Kaanapali soc
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (3 preceding siblings ...)
2025-09-25 0:17 ` [PATCH 04/20] arm64: dts: qcom: kaanapali: Add support for PCIe0 on Kaanapali Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-09-25 0:17 ` [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC Jingyi Wang
` (17 subsequent siblings)
22 siblings, 0 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang, Manish Pandey
From: Manish Pandey <manish.pandey@oss.qualcomm.com>
Add SD Card host controller for kaanapali soc.
Signed-off-by: Manish Pandey <manish.pandey@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 104 ++++++++++++++++++++++++++++++++
1 file changed, 104 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 07dc112065d1..ae1721cfbffc 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -908,6 +908,56 @@ lpass_ag_noc: interconnect@7f40000 {
#interconnect-cells = <2>;
};
+ sdhc_2: mmc@8804000 {
+ compatible = "qcom,kaanapali-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0 0x08804000 0 0x1000>;
+
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "core", "xo";
+
+ interconnects = <&aggre_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "sdhc-ddr", "cpu-sdhc";
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+
+ qcom,dll-config = <0x0007442c>;
+ qcom,ddr-config = <0x80040868>;
+
+ iommus = <&apps_smmu 0x540 0x0>;
+ dma-coherent;
+
+ resets = <&gcc GCC_SDCC2_BCR>;
+ status = "disabled";
+
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-peak-kBps = <160000 100000>;
+ opp-avg-kBps = <50000 0>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ opp-peak-kBps = <200000 120000>;
+ opp-avg-kBps = <104000 0>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,kaanapali-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x10000>,
@@ -974,6 +1024,60 @@ qup_uart7_default: qup-uart7-state {
drive-strength = <2>;
bias-disable;
};
+
+ sdc2_default: sdc2-default-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ card-detect-pins {
+ pins = "gpio55";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_sleep: sdc2-sleep-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ card-detect-pins {
+ pins = "gpio55";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
};
sram@14680000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (4 preceding siblings ...)
2025-09-25 0:17 ` [PATCH 05/20] arm64: dts: qcom: kaanapali: Add SDC2 nodes for Kaanapali soc Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-09-25 1:50 ` Krzysztof Kozłowski
2025-09-25 3:20 ` Dmitry Baryshkov
2025-09-25 0:17 ` [PATCH 07/20] arm64: dts: qcom: kaanapali: Add remoteprocs " Jingyi Wang
` (16 subsequent siblings)
22 siblings, 2 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang, Ronak Raheja
From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
Add the base USB devicetree definitions for Kaanapali platform. The overall
chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
(rev. v8) and M31 eUSB2 PHY.
Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
1 file changed, 155 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index ae1721cfbffc..08ab267bf9a7 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -958,6 +959,160 @@ opp-202000000 {
};
};
+ usb_1_hsphy: phy@88e3000 {
+ compatible = "qcom,kaanapali-m31-eusb2-phy",
+ "qcom,sm8750-m31-eusb2-phy";
+ reg = <0x0 0x88e3000 0x0 0x29c>;
+
+ clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_dp_qmpphy: phy@88e8000 {
+ compatible = "qcom,kaanapali-qmp-usb3-dp-phy",
+ "qcom,sm8750-qmp-usb3-dp-phy";
+ reg = <0x0 0x088e8000 0x0 0x4000>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&tcsrcc TCSR_USB3_CLKREF_EN>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe";
+
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+ reset-names = "phy",
+ "common";
+
+ power-domains = <&gcc GCC_USB3_PHY_GDSC>;
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ orientation-switch;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_dp_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_dp_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_dp_qmpphy_dp_in: endpoint {
+ };
+ };
+ };
+ };
+
+ usb_1: usb@a600000 {
+ compatible = "qcom,kaanapali-dwc3", "qcom,snps-dwc3";
+ reg = <0x0 0x0a600000 0x0 0xfc100>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ interconnects = <&aggre_noc MASTER_USB3 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_USB3 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "usb-ddr", "apps-usb";
+ iommus = <&apps_smmu 0x40 0x0>;
+
+ phys = <&usb_1_hsphy>, <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy", "usb3-phy";
+
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,usb2-gadget-lpm-disable;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,is-utmi-l1-suspend;
+ snps,usb3_lpm_capable;
+ snps,usb2-lpm-disable;
+ snps,has-lpm-erratum;
+ tx-fifo-resize;
+ dma-coherent;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
+ };
+ };
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,kaanapali-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x10000>,
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
2025-09-25 0:17 ` [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC Jingyi Wang
@ 2025-09-25 1:50 ` Krzysztof Kozłowski
2025-09-25 7:39 ` Aiqun(Maria) Yu
2025-09-25 13:57 ` Bjorn Andersson
2025-09-25 3:20 ` Dmitry Baryshkov
1 sibling, 2 replies; 135+ messages in thread
From: Krzysztof Kozłowski @ 2025-09-25 1:50 UTC (permalink / raw)
To: Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Ronak Raheja
On Thu, 25 Sept 2025 at 09:17, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
>
> From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>
> Add the base USB devicetree definitions for Kaanapali platform. The overall
> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
> (rev. v8) and M31 eUSB2 PHY.
>
> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
> 1 file changed, 155 insertions(+)
>
Second try, without HTML:
I really don't understand why you created such huge patchset. Year
ago, two years ago, we were discussing it already and explained that's
just inflating the patchset without reason.
New Soc is one logical change. Maybe two. Not 18!
Not one patch per node or feature.
This hides big picture, makes difficult to review everything,
difficult to test. Your patch count for LWN stats doesn't matter to
us.
NAK and I'm really disappointed I have to repeat the same review .
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
2025-09-25 1:50 ` Krzysztof Kozłowski
@ 2025-09-25 7:39 ` Aiqun(Maria) Yu
2025-09-25 8:24 ` Krzysztof Kozłowski
` (2 more replies)
2025-09-25 13:57 ` Bjorn Andersson
1 sibling, 3 replies; 135+ messages in thread
From: Aiqun(Maria) Yu @ 2025-09-25 7:39 UTC (permalink / raw)
To: Krzysztof Kozłowski, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
tingwei.zhang, trilok.soni, yijie.yang, Ronak Raheja
On 9/25/2025 9:50 AM, Krzysztof Kozłowski wrote:
> On Thu, 25 Sept 2025 at 09:17, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
>>
>> From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>>
>> Add the base USB devicetree definitions for Kaanapali platform. The overall
>> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
>> (rev. v8) and M31 eUSB2 PHY.
>>
>> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
>> 1 file changed, 155 insertions(+)
>>
>
>
> Second try, without HTML:
>
> I really don't understand why you created such huge patchset. Year
> ago, two years ago, we were discussing it already and explained that's
> just inflating the patchset without reason.
>
> New Soc is one logical change. Maybe two. Not 18!
It was previously squashed into the base soc dtsi patch and mark like:
Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
(added USB), Manish Pandey(added SDHCI), Gaurav Kashyap(added crypto),
Manaf Meethalavalappu Pallikunhi(added tsens), Qiang Yu(added PCIE) and
Jinlong Mao(added coresight).
While it is over 4000+ lines when we squash it together.
Also as offline reviewed with Bjorn, he suggested us to split out the
USB and other parts.
>
> Not one patch per node or feature.
>
> This hides big picture, makes difficult to review everything,
> difficult to test. Your patch count for LWN stats doesn't matter to
> us.
With the current splitting, the different author as each co-developer
can get the meaningful LWN stats.>
> NAK and I'm really disappointed I have to repeat the same review .
Currently, there are 10 SoC DTSI patches sent, structured as follows:
SoC initial
Base MTP board
SoC PCIe0
SoC SDC2
SoC USB
SoC remoteproc
SoC SPMI bus, TSENS, RNG, QCrypto, and Coresight
SoC additional features
SoC audio
SoC CAMSS
SoC video
Which parts would you prefer to squash into pls?
--
Thx and BRs,
Aiqun(Maria) Yu
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
2025-09-25 7:39 ` Aiqun(Maria) Yu
@ 2025-09-25 8:24 ` Krzysztof Kozłowski
2025-09-25 8:32 ` Krzysztof Kozlowski
2025-09-25 18:26 ` Trilok Soni
2 siblings, 0 replies; 135+ messages in thread
From: Krzysztof Kozłowski @ 2025-09-25 8:24 UTC (permalink / raw)
To: Aiqun(Maria) Yu
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, tingwei.zhang, trilok.soni, yijie.yang,
Ronak Raheja
On Thu, 25 Sept 2025 at 16:39, Aiqun(Maria) Yu
<aiqun.yu@oss.qualcomm.com> wrote:
>
> On 9/25/2025 9:50 AM, Krzysztof Kozłowski wrote:
> > On Thu, 25 Sept 2025 at 09:17, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
> >>
> >> From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> >>
> >> Add the base USB devicetree definitions for Kaanapali platform. The overall
> >> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
> >> (rev. v8) and M31 eUSB2 PHY.
> >>
> >> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> >> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> >> ---
> >> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
> >> 1 file changed, 155 insertions(+)
> >>
> >
> >
> > Second try, without HTML:
> >
> > I really don't understand why you created such huge patchset. Year
> > ago, two years ago, we were discussing it already and explained that's
> > just inflating the patchset without reason.
> >
> > New Soc is one logical change. Maybe two. Not 18!
>
> It was previously squashed into the base soc dtsi patch and mark like:
> Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
> (added USB), Manish Pandey(added SDHCI), Gaurav Kashyap(added crypto),
> Manaf Meethalavalappu Pallikunhi(added tsens), Qiang Yu(added PCIE) and
> Jinlong Mao(added coresight).
>
> While it is over 4000+ lines when we squash it together.
> Also as offline reviewed with Bjorn, he suggested us to split out the
> USB and other parts.
>
> >
> > Not one patch per node or feature.
> >
> > This hides big picture, makes difficult to review everything,
> > difficult to test. Your patch count for LWN stats doesn't matter to
> > us.
>
> With the current splitting, the different author as each co-developer
> can get the meaningful LWN stats.>
> > NAK and I'm really disappointed I have to repeat the same review .
> Currently, there are 10 SoC DTSI patches sent, structured as follows:
>
> SoC initial
> Base MTP board
> SoC PCIe0
> SoC SDC2
> SoC USB
> SoC remoteproc
> SoC SPMI bus, TSENS, RNG, QCrypto, and Coresight
> SoC additional features
> SoC audio
> SoC CAMSS
> SoC video
>
> Which parts would you prefer to squash into pls?
>
> --
> Thx and BRs,
> Aiqun(Maria) Yu
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
2025-09-25 7:39 ` Aiqun(Maria) Yu
2025-09-25 8:24 ` Krzysztof Kozłowski
@ 2025-09-25 8:32 ` Krzysztof Kozlowski
2025-09-25 9:01 ` Krzysztof Kozlowski
2025-09-25 18:26 ` Trilok Soni
2 siblings, 1 reply; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-25 8:32 UTC (permalink / raw)
To: Aiqun(Maria) Yu
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, tingwei.zhang, trilok.soni, yijie.yang,
Ronak Raheja
On Thu, 25 Sept 2025 at 16:39, Aiqun(Maria) Yu
<aiqun.yu@oss.qualcomm.com> wrote:
>
> On 9/25/2025 9:50 AM, Krzysztof Kozłowski wrote:
> > On Thu, 25 Sept 2025 at 09:17, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
> >>
> >> From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> >>
> >> Add the base USB devicetree definitions for Kaanapali platform. The overall
> >> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
> >> (rev. v8) and M31 eUSB2 PHY.
> >>
> >> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> >> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> >> ---
> >> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
> >> 1 file changed, 155 insertions(+)
> >>
> >
> >
> > Second try, without HTML:
> >
> > I really don't understand why you created such huge patchset. Year
> > ago, two years ago, we were discussing it already and explained that's
> > just inflating the patchset without reason.
> >
> > New Soc is one logical change. Maybe two. Not 18!
>
> It was previously squashed into the base soc dtsi patch and mark like:
> Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
> (added USB), Manish Pandey(added SDHCI), Gaurav Kashyap(added crypto),
> Manaf Meethalavalappu Pallikunhi(added tsens), Qiang Yu(added PCIE) and
> Jinlong Mao(added coresight).
>
> While it is over 4000+ lines when we squash it together.
That's why you send one node per patch? Multiple huge patch bombs land
the same time from Qualcomm, with patches adding one node. It's like
the "no more patch bombs" discussion and rule never existed (yeah, I
know it was removed but the spirit of keeping maintainers mailboxes
sane remains).
> Also as offline reviewed with Bjorn, he suggested us to split out the
> USB and other parts.
>
> >
> > Not one patch per node or feature.
> >
> > This hides big picture, makes difficult to review everything,
> > difficult to test. Your patch count for LWN stats doesn't matter to
> > us.
>
> With the current splitting, the different author as each co-developer
> can get the meaningful LWN stats.>
We don't care about your LWN stats.
Sending stuff like this for your stats, means that community and
reviewers pay with their time.
This is really just selfish. No care how maintainers need to scroll
through their mailboxes.
> > NAK and I'm really disappointed I have to repeat the same review .
> Currently, there are 10 SoC DTSI patches sent, structured as follows:
Why did you ignore all the feedback from 2024 and 2023? Every year it
has to be repeated?
>
> SoC initial
> Base MTP board
> SoC PCIe0
> SoC SDC2
> SoC USB
> SoC remoteproc
> SoC SPMI bus, TSENS, RNG, QCrypto, and Coresight
> SoC additional features
> SoC audio
> SoC CAMSS
> SoC video
>
> Which parts would you prefer to squash into pls?
I made very clear statements year and two years ago. We also discussed
it on IRC multiple times. Can you join discussions instead of ignoring
them?
>
> --
> Thx and BRs,
> Aiqun(Maria) Yu
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
2025-09-25 8:32 ` Krzysztof Kozlowski
@ 2025-09-25 9:01 ` Krzysztof Kozlowski
2025-09-25 16:49 ` Dmitry Baryshkov
0 siblings, 1 reply; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-25 9:01 UTC (permalink / raw)
To: Aiqun(Maria) Yu
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, tingwei.zhang, trilok.soni, yijie.yang,
Ronak Raheja
> > >> From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> > >>
> > >> Add the base USB devicetree definitions for Kaanapali platform. The overall
> > >> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
> > >> (rev. v8) and M31 eUSB2 PHY.
> > >>
> > >> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> > >> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> > >> ---
> > >> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
> > >> 1 file changed, 155 insertions(+)
> > >>
> > >
> > >
> > > Second try, without HTML:
> > >
> > > I really don't understand why you created such huge patchset. Year
> > > ago, two years ago, we were discussing it already and explained that's
> > > just inflating the patchset without reason.
> > >
> > > New Soc is one logical change. Maybe two. Not 18!
> >
> > It was previously squashed into the base soc dtsi patch and mark like:
> > Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
> > (added USB), Manish Pandey(added SDHCI), Gaurav Kashyap(added crypto),
> > Manaf Meethalavalappu Pallikunhi(added tsens), Qiang Yu(added PCIE) and
> > Jinlong Mao(added coresight).
> >
> > While it is over 4000+ lines when we squash it together.
>
> That's why you send one node per patch? Multiple huge patch bombs land
> the same time from Qualcomm, with patches adding one node. It's like
> the "no more patch bombs" discussion and rule never existed (yeah, I
> know it was removed but the spirit of keeping maintainers mailboxes
> sane remains).
>
>
> > Also as offline reviewed with Bjorn, he suggested us to split out the
> > USB and other parts.
> >
> > >
> > > Not one patch per node or feature.
> > >
> > > This hides big picture, makes difficult to review everything,
> > > difficult to test. Your patch count for LWN stats doesn't matter to
> > > us.
> >
> > With the current splitting, the different author as each co-developer
> > can get the meaningful LWN stats.>
>
> We don't care about your LWN stats.
>
> Sending stuff like this for your stats, means that community and
> reviewers pay with their time.
>
> This is really just selfish. No care how maintainers need to scroll
> through their mailboxes.
>
> > > NAK and I'm really disappointed I have to repeat the same review .
> > Currently, there are 10 SoC DTSI patches sent, structured as follows:
>
> Why did you ignore all the feedback from 2024 and 2023? Every year it
> has to be repeated?
>
> >
> > SoC initial
> > Base MTP board
> > SoC PCIe0
> > SoC SDC2
> > SoC USB
> > SoC remoteproc
> > SoC SPMI bus, TSENS, RNG, QCrypto, and Coresight
> > SoC additional features
> > SoC audio
> > SoC CAMSS
> > SoC video
> >
> > Which parts would you prefer to squash into pls?
>
> I made very clear statements year and two years ago. We also discussed
> it on IRC multiple times. Can you join discussions instead of ignoring
> them?
(Apologies for lack of trimming, typos, HTML - using phone)
...and you sent both inflated, LWN-stats-gaming huge patchbombs
(Kaanapali and Glymur) three days before the merge window starts.
Community works for free, doesn't it?
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
2025-09-25 9:01 ` Krzysztof Kozlowski
@ 2025-09-25 16:49 ` Dmitry Baryshkov
0 siblings, 0 replies; 135+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 16:49 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Aiqun(Maria) Yu, Jingyi Wang, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel, tingwei.zhang, trilok.soni, yijie.yang,
Ronak Raheja
On Thu, Sep 25, 2025 at 06:01:15PM +0900, Krzysztof Kozlowski wrote:
> > > >> From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> > > >>
> > > >> Add the base USB devicetree definitions for Kaanapali platform. The overall
> > > >> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
> > > >> (rev. v8) and M31 eUSB2 PHY.
> > > >>
> > > >> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> > > >> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> > > >> ---
> > > >> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
> > > >> 1 file changed, 155 insertions(+)
> > > >>
> > > >
> > > >
> > > > Second try, without HTML:
> > > >
> > > > I really don't understand why you created such huge patchset. Year
> > > > ago, two years ago, we were discussing it already and explained that's
> > > > just inflating the patchset without reason.
> > > >
> > > > New Soc is one logical change. Maybe two. Not 18!
> > >
> > > It was previously squashed into the base soc dtsi patch and mark like:
> > > Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
> > > (added USB), Manish Pandey(added SDHCI), Gaurav Kashyap(added crypto),
> > > Manaf Meethalavalappu Pallikunhi(added tsens), Qiang Yu(added PCIE) and
> > > Jinlong Mao(added coresight).
> > >
> > > While it is over 4000+ lines when we squash it together.
As a reviewer I'd totally prefer a single 4k line DT, because then I can
navigate through it while reviewing.
> >
> > That's why you send one node per patch? Multiple huge patch bombs land
> > the same time from Qualcomm, with patches adding one node. It's like
> > the "no more patch bombs" discussion and rule never existed (yeah, I
> > know it was removed but the spirit of keeping maintainers mailboxes
> > sane remains).
> >
> >
> > > Also as offline reviewed with Bjorn, he suggested us to split out the
> > > USB and other parts.
> > >
> > > >
> > > > Not one patch per node or feature.
> > > >
> > > > This hides big picture, makes difficult to review everything,
> > > > difficult to test. Your patch count for LWN stats doesn't matter to
> > > > us.
> > >
> > > With the current splitting, the different author as each co-developer
> > > can get the meaningful LWN stats.>
> >
> > We don't care about your LWN stats.
> >
> > Sending stuff like this for your stats, means that community and
> > reviewers pay with their time.
> >
> > This is really just selfish. No care how maintainers need to scroll
> > through their mailboxes.
> >
> > > > NAK and I'm really disappointed I have to repeat the same review .
> > > Currently, there are 10 SoC DTSI patches sent, structured as follows:
> >
> > Why did you ignore all the feedback from 2024 and 2023? Every year it
> > has to be repeated?
> >
> > >
> > > SoC initial
> > > Base MTP board
> > > SoC PCIe0
> > > SoC SDC2
> > > SoC USB
> > > SoC remoteproc
> > > SoC SPMI bus, TSENS, RNG, QCrypto, and Coresight
> > > SoC additional features
> > > SoC audio
> > > SoC CAMSS
> > > SoC video
> > >
> > > Which parts would you prefer to squash into pls?
> >
> > I made very clear statements year and two years ago. We also discussed
> > it on IRC multiple times. Can you join discussions instead of ignoring
> > them?
>
> (Apologies for lack of trimming, typos, HTML - using phone)
>
> ...and you sent both inflated, LWN-stats-gaming huge patchbombs
> (Kaanapali and Glymur) three days before the merge window starts.
> Community works for free, doesn't it?
Most of the maintainers have closed their trees, so it doesn't matter.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
2025-09-25 7:39 ` Aiqun(Maria) Yu
2025-09-25 8:24 ` Krzysztof Kozłowski
2025-09-25 8:32 ` Krzysztof Kozlowski
@ 2025-09-25 18:26 ` Trilok Soni
2025-09-26 13:04 ` Konrad Dybcio
2 siblings, 1 reply; 135+ messages in thread
From: Trilok Soni @ 2025-09-25 18:26 UTC (permalink / raw)
To: Aiqun(Maria) Yu, Krzysztof Kozłowski, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
tingwei.zhang, yijie.yang, Ronak Raheja
On 9/25/2025 12:39 AM, Aiqun(Maria) Yu wrote:
> On 9/25/2025 9:50 AM, Krzysztof Kozłowski wrote:
>> On Thu, 25 Sept 2025 at 09:17, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
>>>
>>> From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>>>
>>> Add the base USB devicetree definitions for Kaanapali platform. The overall
>>> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
>>> (rev. v8) and M31 eUSB2 PHY.
>>>
>>> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
>>> 1 file changed, 155 insertions(+)
>>>
>>
>>
>> Second try, without HTML:
>>
>> I really don't understand why you created such huge patchset. Year
>> ago, two years ago, we were discussing it already and explained that's
>> just inflating the patchset without reason.
>>
>> New Soc is one logical change. Maybe two. Not 18!
>
> It was previously squashed into the base soc dtsi patch and mark like:
> Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
> (added USB), Manish Pandey(added SDHCI), Gaurav Kashyap(added crypto),
> Manaf Meethalavalappu Pallikunhi(added tsens), Qiang Yu(added PCIE) and
> Jinlong Mao(added coresight).
>
> While it is over 4000+ lines when we squash it together.
> Also as offline reviewed with Bjorn, he suggested us to split out the
> USB and other parts.
>
>>
>> Not one patch per node or feature.
>>
>> This hides big picture, makes difficult to review everything,
>> difficult to test. Your patch count for LWN stats doesn't matter to
>> us.
Maria - the point here is to not design the series / code for stats, but
per maintainer expectations. Though it is difficult to know one preferred guideline.
>
> With the current splitting, the different author as each co-developer
> can get the meaningful LWN stats.>
>> NAK and I'm really disappointed I have to repeat the same review .
> Currently, there are 10 SoC DTSI patches sent, structured as follows:
>
> SoC initial
> Base MTP board
> SoC PCIe0
> SoC SDC2
> SoC USB
> SoC remoteproc
> SoC SPMI bus, TSENS, RNG, QCrypto, and Coresight
> SoC additional features
> SoC audio
> SoC CAMSS
> SoC video
>
> Which parts would you prefer to squash into pls?
>
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
2025-09-25 18:26 ` Trilok Soni
@ 2025-09-26 13:04 ` Konrad Dybcio
0 siblings, 0 replies; 135+ messages in thread
From: Konrad Dybcio @ 2025-09-26 13:04 UTC (permalink / raw)
To: Trilok Soni, Aiqun(Maria) Yu, Krzysztof Kozłowski,
Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
tingwei.zhang, yijie.yang, Ronak Raheja
On 9/25/25 8:26 PM, Trilok Soni wrote:
> On 9/25/2025 12:39 AM, Aiqun(Maria) Yu wrote:
>> On 9/25/2025 9:50 AM, Krzysztof Kozłowski wrote:
>>> On Thu, 25 Sept 2025 at 09:17, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
>>>>
>>>> From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>>>>
>>>> Add the base USB devicetree definitions for Kaanapali platform. The overall
>>>> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
>>>> (rev. v8) and M31 eUSB2 PHY.
>>>>
>>>> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
>>>> 1 file changed, 155 insertions(+)
>>>>
>>>
>>>
>>> Second try, without HTML:
>>>
>>> I really don't understand why you created such huge patchset. Year
>>> ago, two years ago, we were discussing it already and explained that's
>>> just inflating the patchset without reason.
>>>
>>> New Soc is one logical change. Maybe two. Not 18!
>>
>> It was previously squashed into the base soc dtsi patch and mark like:
>> Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
>> (added USB), Manish Pandey(added SDHCI), Gaurav Kashyap(added crypto),
>> Manaf Meethalavalappu Pallikunhi(added tsens), Qiang Yu(added PCIE) and
>> Jinlong Mao(added coresight).
>>
>> While it is over 4000+ lines when we squash it together.
>> Also as offline reviewed with Bjorn, he suggested us to split out the
>> USB and other parts.
>>
>>>
>>> Not one patch per node or feature.
>>>
>>> This hides big picture, makes difficult to review everything,
>>> difficult to test. Your patch count for LWN stats doesn't matter to
>>> us.
>
> Maria - the point here is to not design the series / code for stats, but
> per maintainer expectations. Though it is difficult to know one preferred guideline.
I believe Krzysztof's explicit mention of LWN might have misguided
Maria into saying getting good stats there is the goal which of course
wouldn't be a good thing for us to solely strive for..
To the best of my knowledge the actual secondary reason (beyond of course
trying to make the series more manageable which I think turned out mostly
successful and I largely agree with Bjorn's other response to this msg)
is to let authors of larger chunks be credited for their work individually
through commit authorship - which I don't think is "gaming" the stats if
the chunks are reasonably sized and the work is nontrivial (just like any
other post-introduction patches would be treated).
If I wrote let's say 35% of the DT and it would be squashed into a single
"add Kaanapali" patch under someone else's name, I would have had rather
mixed feelings as well..
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
2025-09-25 1:50 ` Krzysztof Kozłowski
2025-09-25 7:39 ` Aiqun(Maria) Yu
@ 2025-09-25 13:57 ` Bjorn Andersson
2025-09-25 14:12 ` Krzysztof Kozlowski
2025-09-25 21:31 ` Rob Herring
1 sibling, 2 replies; 135+ messages in thread
From: Bjorn Andersson @ 2025-09-25 13:57 UTC (permalink / raw)
To: Krzysztof Kozłowski
Cc: Jingyi Wang, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Ronak Raheja
On Thu, Sep 25, 2025 at 10:50:10AM +0900, Krzysztof Kozłowski wrote:
> On Thu, 25 Sept 2025 at 09:17, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
> >
> > From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> >
> > Add the base USB devicetree definitions for Kaanapali platform. The overall
> > chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
> > (rev. v8) and M31 eUSB2 PHY.
> >
> > Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> > Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> > ---
> > arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
> > 1 file changed, 155 insertions(+)
> >
>
>
> Second try, without HTML:
>
> I really don't understand why you created such huge patchset.
Because I looked at the logical changes that went into the big squash
that was initially planned, and requested that some of those was kept
intact - because they where independent logical changes.
> Year
> ago, two years ago, we were discussing it already and explained that's
> just inflating the patchset without reason.
>
We used to add things node by node and that was indeed not
comprehensible. Overall this adds features in large logical chunks, but
there are a few of the patches that could have been squashed.
> New Soc is one logical change. Maybe two. Not 18!
I can see your argument for one patch to introduce the soc. But two
doesn't make sense, because that incremental patch is going to be the
kitchen sink.
>
> Not one patch per node or feature.
>
Definitely agree that we don't want one patch for every tiny block!
> This hides big picture, makes difficult to review everything,
> difficult to test.
The big picture is already obscured due to the size of the content
added.
Comparing to previous targets, I see the baseline content in 2-3
patches, and the remainder of the series being things that usually has
been scattered in many more small changes in the following weeks or
months.
There's plenty of features in this series that are yet to be concluded
for SM8750.
> Your patch count for LWN stats doesn't matter to
> us.
I agree with this. That's why the QRD is 1 patch, and MTP is 4 (this I
think should be squashed to 2) - compared to 13 patches for across the
pair for SM8750 with less scope.
>
> NAK and I'm really disappointed I have to repeat the same review .
I'm not sure what you're disappointed in, this initial series is larger
than any we've seen before. I really like the work Jingyi has done here,
aggregating the otherwise scattered patches into one series.
Regards,
Bjorn
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
2025-09-25 13:57 ` Bjorn Andersson
@ 2025-09-25 14:12 ` Krzysztof Kozlowski
2025-09-25 21:31 ` Rob Herring
1 sibling, 0 replies; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-25 14:12 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Jingyi Wang, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Ronak Raheja
On Thu, 25 Sept 2025 at 22:57, Bjorn Andersson <andersson@kernel.org> wrote:
>
> On Thu, Sep 25, 2025 at 10:50:10AM +0900, Krzysztof Kozłowski wrote:
> > On Thu, 25 Sept 2025 at 09:17, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
> > >
> > > From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> > >
> > > Add the base USB devicetree definitions for Kaanapali platform. The overall
> > > chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
> > > (rev. v8) and M31 eUSB2 PHY.
> > >
> > > Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> > > Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> > > ---
> > > arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
> > > 1 file changed, 155 insertions(+)
> > >
> >
> >
> > Second try, without HTML:
> >
> > I really don't understand why you created such huge patchset.
>
> Because I looked at the logical changes that went into the big squash
> that was initially planned, and requested that some of those was kept
> intact - because they where independent logical changes.
Ack
>
> > Year
> > ago, two years ago, we were discussing it already and explained that's
> > just inflating the patchset without reason.
> >
>
> We used to add things node by node and that was indeed not
> comprehensible. Overall this adds features in large logical chunks, but
> there are a few of the patches that could have been squashed.
This patch adds three device nodes.
Other patches add one node. Some other remove the lines which were
added before!
The last argument is the most important. I don't say anything new...
If you add code, which you immediately remove, you do it wrong.
>
> > New Soc is one logical change. Maybe two. Not 18!
>
> I can see your argument for one patch to introduce the soc. But two
> doesn't make sense, because that incremental patch is going to be the
> kitchen sink.
Ack. Plus argument of actual patch line count
So maybe two SoC patches? Maybe three?
>
> >
> > Not one patch per node or feature.
> >
>
> Definitely agree that we don't want one patch for every tiny block!
>
> > This hides big picture, makes difficult to review everything,
> > difficult to test.
>
> The big picture is already obscured due to the size of the content
> added.
Not happy about this either, but understand the principle and business
choices, thus I don't comment on that.
>
> Comparing to previous targets, I see the baseline content in 2-3
> patches, and the remainder of the series being things that usually has
> been scattered in many more small changes in the following weeks or
> months.
>
> There's plenty of features in this series that are yet to be concluded
> for SM8750.
>
> > Your patch count for LWN stats doesn't matter to
> > us.
>
> I agree with this. That's why the QRD is 1 patch, and MTP is 4 (this I
> think should be squashed to 2) - compared to 13 patches for across the
> pair for SM8750 with less scope.
Ack, plus reorganize patches which are removing code added in previous patch.
>
> >
> > NAK and I'm really disappointed I have to repeat the same review .
>
> I'm not sure what you're disappointed in, this initial series is larger
> than any we've seen before. I really like the work Jingyi has done here,
> aggregating the otherwise scattered patches into one series.
Disappointing is only that I had this exactly talk with Qualcomm two
years ago and year ago and 2 months ago (QCS), and maybe more...
I'm sure that we had a internal meeting about Glymur and I said the
same. I emphasized this issue. Look at Glymur DTS - did my internal
emphasizing succeed?
No. I can speak on mailing lists every year, I can have internal
meeting(s) and it doesn't work.
Plus the timing of merge window with these two huge patch bombs is
just cherry on top.
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
2025-09-25 13:57 ` Bjorn Andersson
2025-09-25 14:12 ` Krzysztof Kozlowski
@ 2025-09-25 21:31 ` Rob Herring
2025-09-26 13:21 ` Konrad Dybcio
1 sibling, 1 reply; 135+ messages in thread
From: Rob Herring @ 2025-09-25 21:31 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Krzysztof Kozłowski, Jingyi Wang, Konrad Dybcio,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Ronak Raheja
On Thu, Sep 25, 2025 at 08:57:56AM -0500, Bjorn Andersson wrote:
> On Thu, Sep 25, 2025 at 10:50:10AM +0900, Krzysztof Kozłowski wrote:
> > On Thu, 25 Sept 2025 at 09:17, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
> > >
> > > From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> > >
> > > Add the base USB devicetree definitions for Kaanapali platform. The overall
> > > chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
> > > (rev. v8) and M31 eUSB2 PHY.
> > >
> > > Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> > > Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> > > ---
> > > arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
> > > 1 file changed, 155 insertions(+)
> > >
> >
> >
> > Second try, without HTML:
> >
> > I really don't understand why you created such huge patchset.
>
> Because I looked at the logical changes that went into the big squash
> that was initially planned, and requested that some of those was kept
> intact - because they where independent logical changes.
>
> > Year
> > ago, two years ago, we were discussing it already and explained that's
> > just inflating the patchset without reason.
> >
>
> We used to add things node by node and that was indeed not
> comprehensible. Overall this adds features in large logical chunks, but
> there are a few of the patches that could have been squashed.
>
> > New Soc is one logical change. Maybe two. Not 18!
>
> I can see your argument for one patch to introduce the soc. But two
> doesn't make sense, because that incremental patch is going to be the
> kitchen sink.
>
> >
> > Not one patch per node or feature.
> >
>
> Definitely agree that we don't want one patch for every tiny block!
>
> > This hides big picture, makes difficult to review everything,
> > difficult to test.
>
> The big picture is already obscured due to the size of the content
> added.
>
> Comparing to previous targets, I see the baseline content in 2-3
> patches, and the remainder of the series being things that usually has
> been scattered in many more small changes in the following weeks or
> months.
>
> There's plenty of features in this series that are yet to be concluded
> for SM8750.
>
> > Your patch count for LWN stats doesn't matter to
> > us.
>
> I agree with this. That's why the QRD is 1 patch, and MTP is 4 (this I
> think should be squashed to 2) - compared to 13 patches for across the
> pair for SM8750 with less scope.
>
> >
> > NAK and I'm really disappointed I have to repeat the same review .
>
> I'm not sure what you're disappointed in, this initial series is larger
> than any we've seen before. I really like the work Jingyi has done here,
> aggregating the otherwise scattered patches into one series.
The QCom folks can review all this first because I don't care to review
the 50+ binding (just bindings!) patches sent all at once right before
the merge window.
One comment on commit messages though. Please explain how the h/w block
is or isn't compatible with some existing platforms. Many just state the
obvious "add a compatible" or such. I've yet to find what kaanapali is
in relation to any other QCom chip. It may be the next SoC for the smart
toaster market for all I know.
Rob
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
2025-09-25 21:31 ` Rob Herring
@ 2025-09-26 13:21 ` Konrad Dybcio
2025-09-26 14:47 ` Rob Herring
0 siblings, 1 reply; 135+ messages in thread
From: Konrad Dybcio @ 2025-09-26 13:21 UTC (permalink / raw)
To: Rob Herring, Bjorn Andersson
Cc: Krzysztof Kozłowski, Jingyi Wang, Konrad Dybcio,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Ronak Raheja
On 9/25/25 11:31 PM, Rob Herring wrote:
> On Thu, Sep 25, 2025 at 08:57:56AM -0500, Bjorn Andersson wrote:
>> On Thu, Sep 25, 2025 at 10:50:10AM +0900, Krzysztof Kozłowski wrote:
>>> On Thu, 25 Sept 2025 at 09:17, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
>>>>
>>>> From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>>>>
>>>> Add the base USB devicetree definitions for Kaanapali platform. The overall
>>>> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
>>>> (rev. v8) and M31 eUSB2 PHY.
>>>>
>>>> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
>>>> 1 file changed, 155 insertions(+)
>>>>
>>>
>>>
>>> Second try, without HTML:
>>>
>>> I really don't understand why you created such huge patchset.
>>
>> Because I looked at the logical changes that went into the big squash
>> that was initially planned, and requested that some of those was kept
>> intact - because they where independent logical changes.
>>
>>> Year
>>> ago, two years ago, we were discussing it already and explained that's
>>> just inflating the patchset without reason.
>>>
>>
>> We used to add things node by node and that was indeed not
>> comprehensible. Overall this adds features in large logical chunks, but
>> there are a few of the patches that could have been squashed.
>>
>>> New Soc is one logical change. Maybe two. Not 18!
>>
>> I can see your argument for one patch to introduce the soc. But two
>> doesn't make sense, because that incremental patch is going to be the
>> kitchen sink.
>>
>>>
>>> Not one patch per node or feature.
>>>
>>
>> Definitely agree that we don't want one patch for every tiny block!
>>
>>> This hides big picture, makes difficult to review everything,
>>> difficult to test.
>>
>> The big picture is already obscured due to the size of the content
>> added.
>>
>> Comparing to previous targets, I see the baseline content in 2-3
>> patches, and the remainder of the series being things that usually has
>> been scattered in many more small changes in the following weeks or
>> months.
>>
>> There's plenty of features in this series that are yet to be concluded
>> for SM8750.
>>
>>> Your patch count for LWN stats doesn't matter to
>>> us.
>>
>> I agree with this. That's why the QRD is 1 patch, and MTP is 4 (this I
>> think should be squashed to 2) - compared to 13 patches for across the
>> pair for SM8750 with less scope.
>>
>>>
>>> NAK and I'm really disappointed I have to repeat the same review .
>>
>> I'm not sure what you're disappointed in, this initial series is larger
>> than any we've seen before. I really like the work Jingyi has done here,
>> aggregating the otherwise scattered patches into one series.
>
> The QCom folks can review all this first because I don't care to review
> the 50+ binding (just bindings!) patches sent all at once right before
> the merge window.
Unfortunately this is sort of beyond our control. We don't expect you to
review or apply these patches immediately.
The platform announcement just happened to occur at this and not any other
time, and we can't just ask the entire company to shift it to better
accommodate the kernel release cycle..
We do have an interest in sharing the work at the earliest time possible,
and with all the legal knots included, this is what it came down to.
I (and many others) made an internal push to upstream any pre-requisite
patches that we didn't need to disclose any platform details for in
advance, so this patchbomb is actually somewhat reduced.. but of course
DT and bindings are the main course size-wise and we simply couldn't do
it earlier.
Give or take 80% of the bindings will be "boring", i.e. "add compatbile"
or "add compatible and adjust clocks" because our hw is rather
standardized and the interesting changes often happen at a level beyond
bindings
> One comment on commit messages though. Please explain how the h/w block
> is or isn't compatible with some existing platforms. Many just state the
> obvious "add a compatible" or such. I've yet to find what kaanapali is
> in relation to any other QCom chip. It may be the next SoC for the smart
> toaster market for all I know.
Perhaps this would be useful to have in bindings commit messages, but
the cover letter of >this< series states that Kaanapali is the newly
announced Snapdragon 8 Elite Gen 5.
The product page states at the very bottom of the spec sheet that
SM8850 is another name for it (although the shift to codenames
happened precisely to disconnect from specific SKU numbers,
because e.g. both SA8775P and QCS9100 are 'lemans' silicon)
https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
2025-09-26 13:21 ` Konrad Dybcio
@ 2025-09-26 14:47 ` Rob Herring
2025-09-29 6:06 ` Aiqun(Maria) Yu
0 siblings, 1 reply; 135+ messages in thread
From: Rob Herring @ 2025-09-26 14:47 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Krzysztof Kozłowski, Jingyi Wang,
Konrad Dybcio, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni,
yijie.yang, Ronak Raheja
On Fri, Sep 26, 2025 at 8:21 AM Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 9/25/25 11:31 PM, Rob Herring wrote:
> > On Thu, Sep 25, 2025 at 08:57:56AM -0500, Bjorn Andersson wrote:
> >> On Thu, Sep 25, 2025 at 10:50:10AM +0900, Krzysztof Kozłowski wrote:
> >>> On Thu, 25 Sept 2025 at 09:17, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
> >>>>
> >>>> From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> >>>>
> >>>> Add the base USB devicetree definitions for Kaanapali platform. The overall
> >>>> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
> >>>> (rev. v8) and M31 eUSB2 PHY.
> >>>>
> >>>> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> >>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> >>>> ---
> >>>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
> >>>> 1 file changed, 155 insertions(+)
> >>>>
> >>>
> >>>
> >>> Second try, without HTML:
> >>>
> >>> I really don't understand why you created such huge patchset.
> >>
> >> Because I looked at the logical changes that went into the big squash
> >> that was initially planned, and requested that some of those was kept
> >> intact - because they where independent logical changes.
> >>
> >>> Year
> >>> ago, two years ago, we were discussing it already and explained that's
> >>> just inflating the patchset without reason.
> >>>
> >>
> >> We used to add things node by node and that was indeed not
> >> comprehensible. Overall this adds features in large logical chunks, but
> >> there are a few of the patches that could have been squashed.
> >>
> >>> New Soc is one logical change. Maybe two. Not 18!
> >>
> >> I can see your argument for one patch to introduce the soc. But two
> >> doesn't make sense, because that incremental patch is going to be the
> >> kitchen sink.
> >>
> >>>
> >>> Not one patch per node or feature.
> >>>
> >>
> >> Definitely agree that we don't want one patch for every tiny block!
> >>
> >>> This hides big picture, makes difficult to review everything,
> >>> difficult to test.
> >>
> >> The big picture is already obscured due to the size of the content
> >> added.
> >>
> >> Comparing to previous targets, I see the baseline content in 2-3
> >> patches, and the remainder of the series being things that usually has
> >> been scattered in many more small changes in the following weeks or
> >> months.
> >>
> >> There's plenty of features in this series that are yet to be concluded
> >> for SM8750.
> >>
> >>> Your patch count for LWN stats doesn't matter to
> >>> us.
> >>
> >> I agree with this. That's why the QRD is 1 patch, and MTP is 4 (this I
> >> think should be squashed to 2) - compared to 13 patches for across the
> >> pair for SM8750 with less scope.
> >>
> >>>
> >>> NAK and I'm really disappointed I have to repeat the same review .
> >>
> >> I'm not sure what you're disappointed in, this initial series is larger
> >> than any we've seen before. I really like the work Jingyi has done here,
> >> aggregating the otherwise scattered patches into one series.
> >
> > The QCom folks can review all this first because I don't care to review
> > the 50+ binding (just bindings!) patches sent all at once right before
> > the merge window.
>
> Unfortunately this is sort of beyond our control. We don't expect you to
> review or apply these patches immediately.
It is *only* in your (QCom) control. I would love to have control over
receiving patches to review, but sadly I do not.
Then you should mark them RFC at least if you know they are going into 6.18.
> The platform announcement just happened to occur at this and not any other
> time, and we can't just ask the entire company to shift it to better
> accommodate the kernel release cycle..
That's exactly what we expect. Companies following the rules or
preferences of the kernel community is exactly what is expected and
required. Companies that continuously fail to do that result in
requirements that all patches be first signed off by trusted kernel
developers in those companies.
What would you have done if the timing hit in the merge window where
you have trees which have policies of don't send new content during
merge windows? Just going to ignore that?
> We do have an interest in sharing the work at the earliest time possible,
> and with all the legal knots included, this is what it came down to.
>
> I (and many others) made an internal push to upstream any pre-requisite
> patches that we didn't need to disclose any platform details for in
> advance, so this patchbomb is actually somewhat reduced.. but of course
> DT and bindings are the main course size-wise and we simply couldn't do
> it earlier.
>
> Give or take 80% of the bindings will be "boring", i.e. "add compatbile"
> or "add compatible and adjust clocks" because our hw is rather
> standardized and the interesting changes often happen at a level beyond
> bindings
>
> > One comment on commit messages though. Please explain how the h/w block
> > is or isn't compatible with some existing platforms. Many just state the
> > obvious "add a compatible" or such. I've yet to find what kaanapali is
> > in relation to any other QCom chip. It may be the next SoC for the smart
> > toaster market for all I know.
>
> Perhaps this would be useful to have in bindings commit messages, but
> the cover letter of >this< series states that Kaanapali is the newly
> announced Snapdragon 8 Elite Gen 5.
Patches should stand on their own. I'm talking about patches in other series.
> The product page states at the very bottom of the spec sheet that
> SM8850 is another name for it (although the shift to codenames
> happened precisely to disconnect from specific SKU numbers,
> because e.g. both SA8775P and QCS9100 are 'lemans' silicon)
Sorry, I'm not going to go read your product pages...
Rob
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
2025-09-26 14:47 ` Rob Herring
@ 2025-09-29 6:06 ` Aiqun(Maria) Yu
2025-09-29 7:19 ` Dmitry Baryshkov
0 siblings, 1 reply; 135+ messages in thread
From: Aiqun(Maria) Yu @ 2025-09-29 6:06 UTC (permalink / raw)
To: Rob Herring, Konrad Dybcio
Cc: Bjorn Andersson, Krzysztof Kozłowski, Jingyi Wang,
Konrad Dybcio, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel, tingwei.zhang, trilok.soni, yijie.yang,
Ronak Raheja
On 9/26/2025 10:47 PM, Rob Herring wrote:
> On Fri, Sep 26, 2025 at 8:21 AM Konrad Dybcio
> <konrad.dybcio@oss.qualcomm.com> wrote:
>>
>> On 9/25/25 11:31 PM, Rob Herring wrote:
>>> On Thu, Sep 25, 2025 at 08:57:56AM -0500, Bjorn Andersson wrote:
>>>> On Thu, Sep 25, 2025 at 10:50:10AM +0900, Krzysztof Kozłowski wrote:
>>>>> On Thu, 25 Sept 2025 at 09:17, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
>>>>>>
>>>>>> From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>>>>>>
>>>>>> Add the base USB devicetree definitions for Kaanapali platform. The overall
>>>>>> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
>>>>>> (rev. v8) and M31 eUSB2 PHY.
>>>>>>
>>>>>> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>>>>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>>>>>> ---
>>>>>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
>>>>>> 1 file changed, 155 insertions(+)
>>>>>>
>>>>>
>>>>>
>>>>> Second try, without HTML:
>>>>>
>>>>> I really don't understand why you created such huge patchset.
>>>>
>>>> Because I looked at the logical changes that went into the big squash
>>>> that was initially planned, and requested that some of those was kept
>>>> intact - because they where independent logical changes.
>>>>
>>>>> Year
>>>>> ago, two years ago, we were discussing it already and explained that's
>>>>> just inflating the patchset without reason.
>>>>>
>>>>
>>>> We used to add things node by node and that was indeed not
>>>> comprehensible. Overall this adds features in large logical chunks, but
>>>> there are a few of the patches that could have been squashed.
>>>>
>>>>> New Soc is one logical change. Maybe two. Not 18!
>>>>
>>>> I can see your argument for one patch to introduce the soc. But two
>>>> doesn't make sense, because that incremental patch is going to be the
>>>> kitchen sink.
>>>>
>>>>>
>>>>> Not one patch per node or feature.
>>>>>
>>>>
>>>> Definitely agree that we don't want one patch for every tiny block!
>>>>
>>>>> This hides big picture, makes difficult to review everything,
>>>>> difficult to test.
>>>>
>>>> The big picture is already obscured due to the size of the content
>>>> added.
>>>>
>>>> Comparing to previous targets, I see the baseline content in 2-3
>>>> patches, and the remainder of the series being things that usually has
>>>> been scattered in many more small changes in the following weeks or
>>>> months.
>>>>
>>>> There's plenty of features in this series that are yet to be concluded
>>>> for SM8750.
>>>>
>>>>> Your patch count for LWN stats doesn't matter to
>>>>> us.
>>>>
>>>> I agree with this. That's why the QRD is 1 patch, and MTP is 4 (this I
>>>> think should be squashed to 2) - compared to 13 patches for across the
>>>> pair for SM8750 with less scope.
>>>>
>>>>>
>>>>> NAK and I'm really disappointed I have to repeat the same review .
>>>>
>>>> I'm not sure what you're disappointed in, this initial series is larger
>>>> than any we've seen before. I really like the work Jingyi has done here,
>>>> aggregating the otherwise scattered patches into one series.
>>>
>>> The QCom folks can review all this first because I don't care to review
>>> the 50+ binding (just bindings!) patches sent all at once right before
>>> the merge window.
>>
>> Unfortunately this is sort of beyond our control. We don't expect you to
>> review or apply these patches immediately.
>
> It is *only* in your (QCom) control. I would love to have control over
> receiving patches to review, but sadly I do not.
>
> Then you should mark them RFC at least if you know they are going into 6.18.
We can take your advice for "RFC" for next situation for this.
It would be ideal if most of these patches could make it into the 6.18
release—that is, get accepted before the merge window opens—since the
6.18 kernel is a very important version for us.
While, we fully respect the reviewers' perspective if some patches are
not yet clean or ready. In such cases, we’re prepared to put in
additional effort on our side, including backporting as needed.
>
>> The platform announcement just happened to occur at this and not any other
>> time, and we can't just ask the entire company to shift it to better
>> accommodate the kernel release cycle..
>
> That's exactly what we expect. Companies following the rules or
> preferences of the kernel community is exactly what is expected and
> required. Companies that continuously fail to do that result in
> requirements that all patches be first signed off by trusted kernel
> developers in those companies.
From my understanding, the community is intended to be open to all
developers—whether they contribute individually or through a company.
Imposing a strict "Signed-off-by" requirement risks excluding developers
who actively participate in this community effort.
We still strongly encourage broader participation from both individual
contributors and company-affiliated developers to foster a more open and
inclusive environment.
That said, I do agree that companies should aim to conduct thorough
internal reviews to reduce the burden on upstream maintainers and
reviewers. For large patch sets, perhaps we can consider using
"Reviewed-by" from trusted kernel developers within the company.
In fact, we did perform internal reviews before posting the Kaanapali
patches. However, we also respect the community rule that "Reviewed-by"
should only be added based on public review within the community.
Lastly, the principle of "upstream first" and submitting patches as
early as possible remains a key guideline in the current kernel
development process.
>
> What would you have done if the timing hit in the merge window where
> you have trees which have policies of don't send new content during
> merge windows? Just going to ignore that?
>
If some of the patches aren’t clean enough for the current review cycle
and the merge window has just opened, would it be appropriate to resend
them after the merge window closes—perhaps after October 12th?>
>> We do have an interest in sharing the work at the earliest time possible,
>> and with all the legal knots included, this is what it came down to.
>>
>> I (and many others) made an internal push to upstream any pre-requisite
>> patches that we didn't need to disclose any platform details for in
>> advance, so this patchbomb is actually somewhat reduced.. but of course
>> DT and bindings are the main course size-wise and we simply couldn't do
>> it earlier.
>>
>> Give or take 80% of the bindings will be "boring", i.e. "add compatbile"
>> or "add compatible and adjust clocks" because our hw is rather
>> standardized and the interesting changes often happen at a level beyond
>> bindings
>>
>>> One comment on commit messages though. Please explain how the h/w block
>>> is or isn't compatible with some existing platforms. Many just state the
>>> obvious "add a compatible" or such. I've yet to find what kaanapali is
>>> in relation to any other QCom chip. It may be the next SoC for the smart
>>> toaster market for all I know.
>>
>> Perhaps this would be useful to have in bindings commit messages, but
>> the cover letter of >this< series states that Kaanapali is the newly
>> announced Snapdragon 8 Elite Gen 5.
>
> Patches should stand on their own. I'm talking about patches in other series.
We can add the soc introduction information to the each patches series's
change log and resend after merge window October 12th. Like:
Kaanapali is the newly announced Snapdragon 8 Elite Gen 5, and here is
the document link for reference [1]:
[1]https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
>
>> The product page states at the very bottom of the spec sheet that
>> SM8850 is another name for it (although the shift to codenames
>> happened precisely to disconnect from specific SKU numbers,
>> because e.g. both SA8775P and QCS9100 are 'lemans' silicon)
>
> Sorry, I'm not going to go read your product pages...
Feel free to let me know whether the above suggested updated statements
in the patch change log address your comments.>
> Rob
--
Thx and BRs,
Aiqun(Maria) Yu
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
2025-09-29 6:06 ` Aiqun(Maria) Yu
@ 2025-09-29 7:19 ` Dmitry Baryshkov
0 siblings, 0 replies; 135+ messages in thread
From: Dmitry Baryshkov @ 2025-09-29 7:19 UTC (permalink / raw)
To: Aiqun(Maria) Yu
Cc: Rob Herring, Konrad Dybcio, Bjorn Andersson,
Krzysztof Kozłowski, Jingyi Wang, Konrad Dybcio,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, tingwei.zhang, trilok.soni, yijie.yang,
Ronak Raheja
On Mon, Sep 29, 2025 at 02:06:28PM +0800, Aiqun(Maria) Yu wrote:
> On 9/26/2025 10:47 PM, Rob Herring wrote:
> > On Fri, Sep 26, 2025 at 8:21 AM Konrad Dybcio
> > <konrad.dybcio@oss.qualcomm.com> wrote:
> >>
> >> On 9/25/25 11:31 PM, Rob Herring wrote:
> >>> On Thu, Sep 25, 2025 at 08:57:56AM -0500, Bjorn Andersson wrote:
> >>>> On Thu, Sep 25, 2025 at 10:50:10AM +0900, Krzysztof Kozłowski wrote:
> >>>>> On Thu, 25 Sept 2025 at 09:17, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
> >>>>>>
> >>>>>> From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> >>>>>>
> >>>>>> Add the base USB devicetree definitions for Kaanapali platform. The overall
> >>>>>> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
> >>>>>> (rev. v8) and M31 eUSB2 PHY.
> >>>>>>
> >>>>>> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> >>>>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> >>>>>> ---
> >>>>>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
> >>>>>> 1 file changed, 155 insertions(+)
> >>>>>>
> >>>>>
> >>>>>
> >>>>> Second try, without HTML:
> >>>>>
> >>>>> I really don't understand why you created such huge patchset.
> >>>>
> >>>> Because I looked at the logical changes that went into the big squash
> >>>> that was initially planned, and requested that some of those was kept
> >>>> intact - because they where independent logical changes.
> >>>>
> >>>>> Year
> >>>>> ago, two years ago, we were discussing it already and explained that's
> >>>>> just inflating the patchset without reason.
> >>>>>
> >>>>
> >>>> We used to add things node by node and that was indeed not
> >>>> comprehensible. Overall this adds features in large logical chunks, but
> >>>> there are a few of the patches that could have been squashed.
> >>>>
> >>>>> New Soc is one logical change. Maybe two. Not 18!
> >>>>
> >>>> I can see your argument for one patch to introduce the soc. But two
> >>>> doesn't make sense, because that incremental patch is going to be the
> >>>> kitchen sink.
> >>>>
> >>>>>
> >>>>> Not one patch per node or feature.
> >>>>>
> >>>>
> >>>> Definitely agree that we don't want one patch for every tiny block!
> >>>>
> >>>>> This hides big picture, makes difficult to review everything,
> >>>>> difficult to test.
> >>>>
> >>>> The big picture is already obscured due to the size of the content
> >>>> added.
> >>>>
> >>>> Comparing to previous targets, I see the baseline content in 2-3
> >>>> patches, and the remainder of the series being things that usually has
> >>>> been scattered in many more small changes in the following weeks or
> >>>> months.
> >>>>
> >>>> There's plenty of features in this series that are yet to be concluded
> >>>> for SM8750.
> >>>>
> >>>>> Your patch count for LWN stats doesn't matter to
> >>>>> us.
> >>>>
> >>>> I agree with this. That's why the QRD is 1 patch, and MTP is 4 (this I
> >>>> think should be squashed to 2) - compared to 13 patches for across the
> >>>> pair for SM8750 with less scope.
> >>>>
> >>>>>
> >>>>> NAK and I'm really disappointed I have to repeat the same review .
> >>>>
> >>>> I'm not sure what you're disappointed in, this initial series is larger
> >>>> than any we've seen before. I really like the work Jingyi has done here,
> >>>> aggregating the otherwise scattered patches into one series.
> >>>
> >>> The QCom folks can review all this first because I don't care to review
> >>> the 50+ binding (just bindings!) patches sent all at once right before
> >>> the merge window.
> >>
> >> Unfortunately this is sort of beyond our control. We don't expect you to
> >> review or apply these patches immediately.
> >
> > It is *only* in your (QCom) control. I would love to have control over
> > receiving patches to review, but sadly I do not.
> >
> > Then you should mark them RFC at least if you know they are going into 6.18.
>
> We can take your advice for "RFC" for next situation for this.
>
> It would be ideal if most of these patches could make it into the 6.18
> release—that is, get accepted before the merge window opens—since the
> 6.18 kernel is a very important version for us.
Most of the branches related to 6.18 tree should be already closed (and
were almost closed for the last week or two, depending on the
subsystem). 6.17 was released several hours ago, which means we are now
in the merge window towards 6.18.
>
> While, we fully respect the reviewers' perspective if some patches are
> not yet clean or ready. In such cases, we’re prepared to put in
> additional effort on our side, including backporting as needed.
I'm not sure what do you mean here.
>
> >
> >> The platform announcement just happened to occur at this and not any other
> >> time, and we can't just ask the entire company to shift it to better
> >> accommodate the kernel release cycle..
> >
> > That's exactly what we expect. Companies following the rules or
> > preferences of the kernel community is exactly what is expected and
> > required. Companies that continuously fail to do that result in
> > requirements that all patches be first signed off by trusted kernel
> > developers in those companies.
> From my understanding, the community is intended to be open to all
> developers—whether they contribute individually or through a company.
> Imposing a strict "Signed-off-by" requirement risks excluding developers
> who actively participate in this community effort.
> We still strongly encourage broader participation from both individual
> contributors and company-affiliated developers to foster a more open and
> inclusive environment.
>
> That said, I do agree that companies should aim to conduct thorough
> internal reviews to reduce the burden on upstream maintainers and
> reviewers. For large patch sets, perhaps we can consider using
> "Reviewed-by" from trusted kernel developers within the company.
>
> In fact, we did perform internal reviews before posting the Kaanapali
> patches. However, we also respect the community rule that "Reviewed-by"
> should only be added based on public review within the community.
>
> Lastly, the principle of "upstream first" and submitting patches as
> early as possible remains a key guideline in the current kernel
> development process.
>
> >
> > What would you have done if the timing hit in the merge window where
> > you have trees which have policies of don't send new content during
> > merge windows? Just going to ignore that?
> >
>
> If some of the patches aren’t clean enough for the current review cycle
> and the merge window has just opened, would it be appropriate to resend
> them after the merge window closes—perhaps after October 12th?>
No need to, most of the patches will be reviewed. But the ship for 6.18
has already sailed. 6.19 is the earliest merge target.
> >> We do have an interest in sharing the work at the earliest time possible,
> >> and with all the legal knots included, this is what it came down to.
> >>
> >> I (and many others) made an internal push to upstream any pre-requisite
> >> patches that we didn't need to disclose any platform details for in
> >> advance, so this patchbomb is actually somewhat reduced.. but of course
> >> DT and bindings are the main course size-wise and we simply couldn't do
> >> it earlier.
> >>
> >> Give or take 80% of the bindings will be "boring", i.e. "add compatbile"
> >> or "add compatible and adjust clocks" because our hw is rather
> >> standardized and the interesting changes often happen at a level beyond
> >> bindings
> >>
> >>> One comment on commit messages though. Please explain how the h/w block
> >>> is or isn't compatible with some existing platforms. Many just state the
> >>> obvious "add a compatible" or such. I've yet to find what kaanapali is
> >>> in relation to any other QCom chip. It may be the next SoC for the smart
> >>> toaster market for all I know.
> >>
> >> Perhaps this would be useful to have in bindings commit messages, but
> >> the cover letter of >this< series states that Kaanapali is the newly
> >> announced Snapdragon 8 Elite Gen 5.
> >
> > Patches should stand on their own. I'm talking about patches in other series.
>
> We can add the soc introduction information to the each patches series's
> change log and resend after merge window October 12th. Like:
> Kaanapali is the newly announced Snapdragon 8 Elite Gen 5, and here is
> the document link for reference [1]:
> [1]https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
Note, you have been asked to explain the details regarding IP block
compatibility, rather than just marketing details regarding the
platform. A proper commit message might say something like 'Block foo on
Kaapanali is compatible with the same block on the MSM8960, use
qcom,msm8960-foo as a fallback compatible string'. Or 'Block foo on
Kaanapali has different register stride between ADC channels, as such it
requires a new compatible string'.
>
> >
> >> The product page states at the very bottom of the spec sheet that
> >> SM8850 is another name for it (although the shift to codenames
> >> happened precisely to disconnect from specific SKU numbers,
> >> because e.g. both SA8775P and QCS9100 are 'lemans' silicon)
> >
> > Sorry, I'm not going to go read your product pages...
>
>
> Feel free to let me know whether the above suggested updated statements
> in the patch change log address your comments.>
2c from my side: please work on declaring the _actual_ dependencies for
the series (as in 'patches in the series won't even build without
changes a, b, c). Use b4 --edit-deps to declare those dependencies.
Remove unnecessary dependencies between DT bindings (by using ephemeral
nodes instead of actual platform indices). Drop long lists of
pseudo-dependencies from cover letters. They do more harm than help.
Work with Bjorn and Konrad on how to better structure the DT patches.
Make sure that all your commit messages describe the _reason_ for the
change rather than the patch contents.
> > Rob
> --
> Thx and BRs,
> Aiqun(Maria) Yu
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
2025-09-25 0:17 ` [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC Jingyi Wang
2025-09-25 1:50 ` Krzysztof Kozłowski
@ 2025-09-25 3:20 ` Dmitry Baryshkov
2025-09-25 7:49 ` Aiqun(Maria) Yu
1 sibling, 1 reply; 135+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 3:20 UTC (permalink / raw)
To: Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Ronak Raheja
On Wed, Sep 24, 2025 at 05:17:23PM -0700, Jingyi Wang wrote:
> From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>
> Add the base USB devicetree definitions for Kaanapali platform. The overall
> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
> (rev. v8) and M31 eUSB2 PHY.
>
> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
> 1 file changed, 155 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> index ae1721cfbffc..08ab267bf9a7 100644
> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> @@ -12,6 +12,7 @@
> #include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/mailbox/qcom-ipcc.h>
> +#include <dt-bindings/phy/phy-qcom-qmp.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> @@ -958,6 +959,160 @@ opp-202000000 {
> };
> };
>
> + usb_1_hsphy: phy@88e3000 {
No update for GCC clocks?
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
2025-09-25 3:20 ` Dmitry Baryshkov
@ 2025-09-25 7:49 ` Aiqun(Maria) Yu
2025-09-25 9:46 ` Konrad Dybcio
0 siblings, 1 reply; 135+ messages in thread
From: Aiqun(Maria) Yu @ 2025-09-25 7:49 UTC (permalink / raw)
To: Dmitry Baryshkov, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
tingwei.zhang, trilok.soni, yijie.yang, Ronak Raheja
On 9/25/2025 11:20 AM, Dmitry Baryshkov wrote:
> On Wed, Sep 24, 2025 at 05:17:23PM -0700, Jingyi Wang wrote:
>> From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>>
>> Add the base USB devicetree definitions for Kaanapali platform. The overall
>> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
>> (rev. v8) and M31 eUSB2 PHY.
>>
>> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
>> 1 file changed, 155 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>> index ae1721cfbffc..08ab267bf9a7 100644
>> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>> @@ -12,6 +12,7 @@
>> #include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/mailbox/qcom-ipcc.h>
>> +#include <dt-bindings/phy/phy-qcom-qmp.h>
>> #include <dt-bindings/power/qcom-rpmpd.h>
>> #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>> @@ -958,6 +959,160 @@ opp-202000000 {
>> };
>> };
>>
>> + usb_1_hsphy: phy@88e3000 {
>
> No update for GCC clocks?
>
could you help to have more detailed comments here pls?
For this driver phy-qcom-m31-eusb2, only ref clk is needed per my
current information.
--
Thx and BRs,
Aiqun(Maria) Yu
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
2025-09-25 7:49 ` Aiqun(Maria) Yu
@ 2025-09-25 9:46 ` Konrad Dybcio
0 siblings, 0 replies; 135+ messages in thread
From: Konrad Dybcio @ 2025-09-25 9:46 UTC (permalink / raw)
To: Aiqun(Maria) Yu, Dmitry Baryshkov, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
tingwei.zhang, trilok.soni, yijie.yang, Ronak Raheja
On 9/25/25 9:49 AM, Aiqun(Maria) Yu wrote:
> On 9/25/2025 11:20 AM, Dmitry Baryshkov wrote:
>> On Wed, Sep 24, 2025 at 05:17:23PM -0700, Jingyi Wang wrote:
>>> From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>>>
>>> Add the base USB devicetree definitions for Kaanapali platform. The overall
>>> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
>>> (rev. v8) and M31 eUSB2 PHY.
>>>
>>> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
>>> 1 file changed, 155 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>>> index ae1721cfbffc..08ab267bf9a7 100644
>>> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>>> @@ -12,6 +12,7 @@
>>> #include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> #include <dt-bindings/mailbox/qcom-ipcc.h>
>>> +#include <dt-bindings/phy/phy-qcom-qmp.h>
>>> #include <dt-bindings/power/qcom-rpmpd.h>
>>> #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>>> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>>> @@ -958,6 +959,160 @@ opp-202000000 {
>>> };
>>> };
>>>
>>> + usb_1_hsphy: phy@88e3000 {
>>
>> No update for GCC clocks?
>>
>
> could you help to have more detailed comments here pls?
> For this driver phy-qcom-m31-eusb2, only ref clk is needed per my
> current information.
The QMPPHY acts as a clock provider, which we're expected to plug
it back into GCC (and DISP_CC), see e.g. sm8650.dtsi
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread
* [PATCH 07/20] arm64: dts: qcom: kaanapali: Add remoteprocs for Kaanapali SoC
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (5 preceding siblings ...)
2025-09-25 0:17 ` [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-09-30 17:24 ` Alexey Klimov
2025-09-25 0:17 ` [PATCH 08/20] arm64: dts: qcom: Add PMK8850 pmic dtsi Jingyi Wang
` (15 subsequent siblings)
22 siblings, 1 reply; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang
Add remoteproc PAS loader for ADSP, CDSP, MPSS and SoCCP with
its SMP2P and fastrpc nodes.
Written with help from Kumari Pallavi(added fastrpc).
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 484 ++++++++++++++++++++++++++++++++
1 file changed, 484 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 08ab267bf9a7..c3b38fd851c5 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -438,6 +438,121 @@ rmtfs_mem: rmtfs@d7c00000 {
};
};
+ smp2p-adsp {
+ compatible = "qcom,smp2p";
+
+ interrupts-extended = <&ipcc IPCC_MPROC_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_MPROC_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,smem = <443>, <429>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ smp2p_adsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_adsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+
+ interrupts-extended = <&ipcc IPCC_MPROC_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_MPROC_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,smem = <94>, <432>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ smp2p_cdsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_cdsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-modem {
+ compatible = "qcom,smp2p";
+
+ interrupts-extended = <&ipcc IPCC_MPROC_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_MPROC_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,smem = <435>, <428>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ smp2p_modem_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_modem_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ ipa_smp2p_out: ipa-ap-to-modem {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ ipa_smp2p_in: ipa-modem-to-ap {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-soccp {
+ compatible = "qcom,smp2p";
+
+ interrupts-extended = <&ipcc IPCC_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,smem = <617>, <616>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <19>;
+
+ soccp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ soccp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
soc: soc@0 {
compatible = "simple-bus";
@@ -504,6 +619,58 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
};
};
+ remoteproc_soccp: remoteproc-soccp@d00000 {
+ compatible = "qcom,kaanapali-soccp-pas";
+ reg = <0x0 0x00d00000 0x0 0x200000>;
+
+ interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 10 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "pong",
+ "wake-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "cx",
+ "mx";
+
+ memory-region = <&soccp_mem>,
+ <&soccp_dtb_mem>;
+
+ qcom,smem-states = <&soccp_smp2p_out 0>,
+ <&soccp_smp2p_out 10>,
+ <&soccp_smp2p_out 9>,
+ <&soccp_smp2p_out 8>;
+ qcom,smem-state-names = "stop",
+ "wakeup",
+ "sleep",
+ "ping";
+
+ status = "okay";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ qcom,remote-pid = <19>;
+ label = "soccp";
+ };
+ };
+
ipcc: mailbox@1106000 {
compatible = "qcom,kaanapali-ipcc", "qcom,ipcc";
reg = <0x0 0x01106000 0x0 0x1000>;
@@ -888,6 +1055,164 @@ tcsrcc: clock-controller@1fd5044 {
#reset-cells = <1>;
};
+ remoteproc_mpss: remoteproc@4080000 {
+ compatible = "qcom,kaanapali-mpss-pas", "qcom,sm8750-mpss-pas";
+ reg = <0x0 0x04080000 0x0 0x10000>;
+
+ interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MSS>;
+ power-domain-names = "cx",
+ "mss";
+
+ memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>,
+ <&dsm_partition_1_mem>, <&dsm_partition_2_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_modem_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_MPROC_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_MPROC_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ qcom,remote-pid = <1>;
+
+ label = "mpss";
+ };
+ };
+
+ remoteproc_adsp: remoteproc@6800000 {
+ compatible = "qcom,kaanapali-adsp-pas", "qcom,sm8550-adsp-pas";
+ reg = <0x0 0x06800000 0x0 0x10000>;
+
+ interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ power-domains = <&rpmhpd RPMHPD_LCX>,
+ <&rpmhpd RPMHPD_LMX>;
+ power-domain-names = "lcx",
+ "lmx";
+
+ memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_adsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ remoteproc_adsp_glink: glink-edge {
+ interrupts-extended = <&ipcc IPCC_MPROC_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_MPROC_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ qcom,remote-pid = <2>;
+
+ label = "lpass";
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "adsp";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+
+ iommus = <&apps_smmu 0x1003 0x80>,
+ <&apps_smmu 0x1043 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+
+ iommus = <&apps_smmu 0x1004 0x80>,
+ <&apps_smmu 0x1044 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+
+ iommus = <&apps_smmu 0x1005 0x80>,
+ <&apps_smmu 0x1045 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+
+ iommus = <&apps_smmu 0x1006 0x80>,
+ <&apps_smmu 0x1046 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+
+ iommus = <&apps_smmu 0x1007 0x40>,
+ <&apps_smmu 0x1067 0x0>,
+ <&apps_smmu 0x1087 0x0>;
+ dma-coherent;
+ };
+ };
+ };
+ };
+
lpass_lpiaon_noc: interconnect@7400000 {
compatible = "qcom,kaanapali-lpass-lpiaon-noc";
reg = <0x0 0x07400000 0x0 0x19080>;
@@ -1629,6 +1954,165 @@ nsp_noc: interconnect@260c0000 {
#interconnect-cells = <2>;
};
+ remoteproc_cdsp: remoteproc@26300000 {
+ compatible = "qcom,kaanapali-cdsp-pas", "qcom,sm8550-cdsp-pas";
+ reg = <0x0 0x26300000 0x0 0x10000>;
+
+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_NSP>;
+ power-domain-names = "cx",
+ "mxc",
+ "nsp";
+
+ memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
+ qcom,qmp = <&aoss_qmp>;
+ qcom,smem-states = <&smp2p_cdsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_MPROC_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_MPROC_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ qcom,remote-pid = <5>;
+ label = "cdsp";
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "cdsp";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+ iommus = <&apps_smmu 0x19c1 0x0>,
+ <&apps_smmu 0x1961 0x0>,
+ <&apps_smmu 0x0c21 0x0>,
+ <&apps_smmu 0x0c01 0x40>;
+ dma-coherent;
+ };
+
+ compute-cb@2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+ iommus = <&apps_smmu 0x1962 0x0>,
+ <&apps_smmu 0x0c02 0x20>,
+ <&apps_smmu 0x0c42 0x0>,
+ <&apps_smmu 0x19c2 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x1963 0x0>,
+ <&apps_smmu 0x0c23 0x0>,
+ <&apps_smmu 0x0c03 0x40>,
+ <&apps_smmu 0x19c3 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu 0x1964 0x0>,
+ <&apps_smmu 0x0c44 0x0>,
+ <&apps_smmu 0x0c04 0x20>,
+ <&apps_smmu 0x19c4 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu 0x1965 0x0>,
+ <&apps_smmu 0x0c45 0x0>,
+ <&apps_smmu 0x0c05 0x20>,
+ <&apps_smmu 0x19c5 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&apps_smmu 0x1966 0x0>,
+ <&apps_smmu 0x0c06 0x20>,
+ <&apps_smmu 0x0c46 0x0>,
+ <&apps_smmu 0x19c6 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+ iommus = <&apps_smmu 0x1967 0x0>,
+ <&apps_smmu 0x0c27 0x0>,
+ <&apps_smmu 0x0c07 0x40>,
+ <&apps_smmu 0x19c7 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@8 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <8>;
+ iommus = <&apps_smmu 0x1968 0x0>,
+ <&apps_smmu 0x0c08 0x20>,
+ <&apps_smmu 0x0c48 0x0>,
+ <&apps_smmu 0x19c8 0x0>;
+ dma-coherent;
+ };
+
+ /* note: secure cb9 in downstream */
+
+ compute-cb@12 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <12>;
+ iommus = <&apps_smmu 0x196c 0x0>,
+ <&apps_smmu 0x0c2c 0x00>,
+ <&apps_smmu 0x0c0c 0x40>,
+ <&apps_smmu 0x19cc 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@13 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <13>;
+ iommus = <&apps_smmu 0x196d 0x0>,
+ <&apps_smmu 0x0c0d 0x40>,
+ <&apps_smmu 0x0c2e 0x0>,
+ <&apps_smmu 0x0c2d 0x0>,
+ <&apps_smmu 0x19cd 0x0>;
+ dma-coherent;
+ };
+ };
+ };
+ };
+
/* Cluster 0 */
pmu@310b3400 {
compatible = "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon";
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* Re: [PATCH 07/20] arm64: dts: qcom: kaanapali: Add remoteprocs for Kaanapali SoC
2025-09-25 0:17 ` [PATCH 07/20] arm64: dts: qcom: kaanapali: Add remoteprocs " Jingyi Wang
@ 2025-09-30 17:24 ` Alexey Klimov
2025-11-04 8:59 ` Jingyi Wang
0 siblings, 1 reply; 135+ messages in thread
From: Alexey Klimov @ 2025-09-30 17:24 UTC (permalink / raw)
To: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang
On Thu Sep 25, 2025 at 1:17 AM BST, Jingyi Wang wrote:
> Add remoteproc PAS loader for ADSP, CDSP, MPSS and SoCCP with
> its SMP2P and fastrpc nodes.
>
> Written with help from Kumari Pallavi(added fastrpc).
Co-developed-by tag then maybe?
Also I don't see this name in email addresses.
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 484 ++++++++++++++++++++++++++++++++
> 1 file changed, 484 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> index 08ab267bf9a7..c3b38fd851c5 100644
> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> @@ -438,6 +438,121 @@ rmtfs_mem: rmtfs@d7c00000 {
> };
> };
[...]
> + remoteproc_adsp: remoteproc@6800000 {
> + compatible = "qcom,kaanapali-adsp-pas", "qcom,sm8550-adsp-pas";
> + reg = <0x0 0x06800000 0x0 0x10000>;
> +
> + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog",
> + "fatal",
> + "ready",
> + "handover",
> + "stop-ack",
> + "shutdown-ack";
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "xo";
> +
> + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> +
> + power-domains = <&rpmhpd RPMHPD_LCX>,
> + <&rpmhpd RPMHPD_LMX>;
> + power-domain-names = "lcx",
> + "lmx";
> +
> + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
> +
> + qcom,qmp = <&aoss_qmp>;
> +
> + qcom,smem-states = <&smp2p_adsp_out 0>;
> + qcom,smem-state-names = "stop";
> +
> + status = "disabled";
> +
> + remoteproc_adsp_glink: glink-edge {
> + interrupts-extended = <&ipcc IPCC_MPROC_LPASS
> + IPCC_MPROC_SIGNAL_GLINK_QMP
> + IRQ_TYPE_EDGE_RISING>;
> +
> + mboxes = <&ipcc IPCC_MPROC_LPASS
> + IPCC_MPROC_SIGNAL_GLINK_QMP>;
> +
> + qcom,remote-pid = <2>;
> +
> + label = "lpass";
> +
> + fastrpc {
> + compatible = "qcom,fastrpc";
> + qcom,glink-channels = "fastrpcglink-apps-dsp";
> + label = "adsp";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + compute-cb@3 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <3>;
> +
> + iommus = <&apps_smmu 0x1003 0x80>,
> + <&apps_smmu 0x1043 0x20>;
> + dma-coherent;
> + };
> +
> + compute-cb@4 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <4>;
> +
> + iommus = <&apps_smmu 0x1004 0x80>,
> + <&apps_smmu 0x1044 0x20>;
> + dma-coherent;
> + };
> +
> + compute-cb@5 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <5>;
> +
> + iommus = <&apps_smmu 0x1005 0x80>,
> + <&apps_smmu 0x1045 0x20>;
> + dma-coherent;
> + };
> +
> + compute-cb@6 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <6>;
> +
> + iommus = <&apps_smmu 0x1006 0x80>,
> + <&apps_smmu 0x1046 0x20>;
> + dma-coherent;
> + };
> +
> + compute-cb@7 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <7>;
> +
> + iommus = <&apps_smmu 0x1007 0x40>,
> + <&apps_smmu 0x1067 0x0>,
> + <&apps_smmu 0x1087 0x0>;
> + dma-coherent;
> + };
> + };
> + };
> + };
Fastrpc nodes here. Was this tested? If yes, then how?
Or was it just copied from somewhere from downstream?
The same questions basically go for cdsp fastrpc too.
[..]
> + label = "cdsp";
> +
> + fastrpc {
> + compatible = "qcom,fastrpc";
> + qcom,glink-channels = "fastrpcglink-apps-dsp";
> + label = "cdsp";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + compute-cb@1 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <1>;
> + iommus = <&apps_smmu 0x19c1 0x0>,
> + <&apps_smmu 0x1961 0x0>,
> + <&apps_smmu 0x0c21 0x0>,
> + <&apps_smmu 0x0c01 0x40>;
> + dma-coherent;
> + };
> +
> + compute-cb@2 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <2>;
> + iommus = <&apps_smmu 0x1962 0x0>,
> + <&apps_smmu 0x0c02 0x20>,
> + <&apps_smmu 0x0c42 0x0>,
> + <&apps_smmu 0x19c2 0x0>;
> + dma-coherent;
> + };
> +
> + compute-cb@3 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <3>;
> + iommus = <&apps_smmu 0x1963 0x0>,
> + <&apps_smmu 0x0c23 0x0>,
> + <&apps_smmu 0x0c03 0x40>,
> + <&apps_smmu 0x19c3 0x0>;
> + dma-coherent;
> + };
> +
> + compute-cb@4 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <4>;
> + iommus = <&apps_smmu 0x1964 0x0>,
> + <&apps_smmu 0x0c44 0x0>,
> + <&apps_smmu 0x0c04 0x20>,
> + <&apps_smmu 0x19c4 0x0>;
> + dma-coherent;
> + };
> +
> + compute-cb@5 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <5>;
> + iommus = <&apps_smmu 0x1965 0x0>,
> + <&apps_smmu 0x0c45 0x0>,
> + <&apps_smmu 0x0c05 0x20>,
> + <&apps_smmu 0x19c5 0x0>;
> + dma-coherent;
> + };
> +
> + compute-cb@6 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <6>;
> + iommus = <&apps_smmu 0x1966 0x0>,
> + <&apps_smmu 0x0c06 0x20>,
> + <&apps_smmu 0x0c46 0x0>,
> + <&apps_smmu 0x19c6 0x0>;
> + dma-coherent;
> + };
> +
> + compute-cb@7 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <7>;
> + iommus = <&apps_smmu 0x1967 0x0>,
> + <&apps_smmu 0x0c27 0x0>,
> + <&apps_smmu 0x0c07 0x40>,
> + <&apps_smmu 0x19c7 0x0>;
> + dma-coherent;
> + };
> +
> + compute-cb@8 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <8>;
> + iommus = <&apps_smmu 0x1968 0x0>,
> + <&apps_smmu 0x0c08 0x20>,
> + <&apps_smmu 0x0c48 0x0>,
> + <&apps_smmu 0x19c8 0x0>;
> + dma-coherent;
> + };
> +
> + /* note: secure cb9 in downstream */
> +
> + compute-cb@12 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <12>;
> + iommus = <&apps_smmu 0x196c 0x0>,
> + <&apps_smmu 0x0c2c 0x00>,
> + <&apps_smmu 0x0c0c 0x40>,
> + <&apps_smmu 0x19cc 0x0>;
> + dma-coherent;
> + };
> +
> + compute-cb@13 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <13>;
> + iommus = <&apps_smmu 0x196d 0x0>,
> + <&apps_smmu 0x0c0d 0x40>,
> + <&apps_smmu 0x0c2e 0x0>,
> + <&apps_smmu 0x0c2d 0x0>,
> + <&apps_smmu 0x19cd 0x0>;
> + dma-coherent;
> + };
> + };
> + };
> + };
> +
Best regards,
Alexey
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 07/20] arm64: dts: qcom: kaanapali: Add remoteprocs for Kaanapali SoC
2025-09-30 17:24 ` Alexey Klimov
@ 2025-11-04 8:59 ` Jingyi Wang
2025-11-04 10:01 ` Kumari Pallavi
0 siblings, 1 reply; 135+ messages in thread
From: Jingyi Wang @ 2025-11-04 8:59 UTC (permalink / raw)
To: Alexey Klimov, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, kumari.pallavi
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang
On 10/1/2025 1:24 AM, Alexey Klimov wrote:
> On Thu Sep 25, 2025 at 1:17 AM BST, Jingyi Wang wrote:
>> Add remoteproc PAS loader for ADSP, CDSP, MPSS and SoCCP with
>> its SMP2P and fastrpc nodes.
>>
>> Written with help from Kumari Pallavi(added fastrpc).
>
> Co-developed-by tag then maybe?
>
> Also I don't see this name in email addresses.
>
Hi Alexey,
We got review comments to merge dt changes in one patch, we are still discussing on
how to organize next version, I think we can add the Co-developed-by tag if remoteproc
is sent as a single patch in next version, "Written with" description will be used
to avoid SOB chain too long.
Thanks,
Jingyi
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 484 ++++++++++++++++++++++++++++++++
>> 1 file changed, 484 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>> index 08ab267bf9a7..c3b38fd851c5 100644
>> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>> @@ -438,6 +438,121 @@ rmtfs_mem: rmtfs@d7c00000 {
>> };
>> };
>
> [...]
>
>> + remoteproc_adsp: remoteproc@6800000 {
>> + compatible = "qcom,kaanapali-adsp-pas", "qcom,sm8550-adsp-pas";
>> + reg = <0x0 0x06800000 0x0 0x10000>;
>> +
>> + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
>> + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
>> + interrupt-names = "wdog",
>> + "fatal",
>> + "ready",
>> + "handover",
>> + "stop-ack",
>> + "shutdown-ack";
>> +
>> + clocks = <&rpmhcc RPMH_CXO_CLK>;
>> + clock-names = "xo";
>> +
>> + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
>> +
>> + power-domains = <&rpmhpd RPMHPD_LCX>,
>> + <&rpmhpd RPMHPD_LMX>;
>> + power-domain-names = "lcx",
>> + "lmx";
>> +
>> + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
>> +
>> + qcom,qmp = <&aoss_qmp>;
>> +
>> + qcom,smem-states = <&smp2p_adsp_out 0>;
>> + qcom,smem-state-names = "stop";
>> +
>> + status = "disabled";
>> +
>> + remoteproc_adsp_glink: glink-edge {
>> + interrupts-extended = <&ipcc IPCC_MPROC_LPASS
>> + IPCC_MPROC_SIGNAL_GLINK_QMP
>> + IRQ_TYPE_EDGE_RISING>;
>> +
>> + mboxes = <&ipcc IPCC_MPROC_LPASS
>> + IPCC_MPROC_SIGNAL_GLINK_QMP>;
>> +
>> + qcom,remote-pid = <2>;
>> +
>> + label = "lpass";
>> +
>> + fastrpc {
>> + compatible = "qcom,fastrpc";
>> + qcom,glink-channels = "fastrpcglink-apps-dsp";
>> + label = "adsp";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + compute-cb@3 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <3>;
>> +
>> + iommus = <&apps_smmu 0x1003 0x80>,
>> + <&apps_smmu 0x1043 0x20>;
>> + dma-coherent;
>> + };
>> +
>> + compute-cb@4 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <4>;
>> +
>> + iommus = <&apps_smmu 0x1004 0x80>,
>> + <&apps_smmu 0x1044 0x20>;
>> + dma-coherent;
>> + };
>> +
>> + compute-cb@5 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <5>;
>> +
>> + iommus = <&apps_smmu 0x1005 0x80>,
>> + <&apps_smmu 0x1045 0x20>;
>> + dma-coherent;
>> + };
>> +
>> + compute-cb@6 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <6>;
>> +
>> + iommus = <&apps_smmu 0x1006 0x80>,
>> + <&apps_smmu 0x1046 0x20>;
>> + dma-coherent;
>> + };
>> +
>> + compute-cb@7 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <7>;
>> +
>> + iommus = <&apps_smmu 0x1007 0x40>,
>> + <&apps_smmu 0x1067 0x0>,
>> + <&apps_smmu 0x1087 0x0>;
>> + dma-coherent;
>> + };
>> + };
>> + };
>> + };
>
> Fastrpc nodes here. Was this tested? If yes, then how?
> Or was it just copied from somewhere from downstream?
>
> The same questions basically go for cdsp fastrpc too.
>
+Kumari, could you please comment on this?
>
> [..]
>
>> + label = "cdsp";
>> +
>> + fastrpc {
>> + compatible = "qcom,fastrpc";
>> + qcom,glink-channels = "fastrpcglink-apps-dsp";
>> + label = "cdsp";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + compute-cb@1 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <1>;
>> + iommus = <&apps_smmu 0x19c1 0x0>,
>> + <&apps_smmu 0x1961 0x0>,
>> + <&apps_smmu 0x0c21 0x0>,
>> + <&apps_smmu 0x0c01 0x40>;
>> + dma-coherent;
>> + };
>> +
>> + compute-cb@2 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <2>;
>> + iommus = <&apps_smmu 0x1962 0x0>,
>> + <&apps_smmu 0x0c02 0x20>,
>> + <&apps_smmu 0x0c42 0x0>,
>> + <&apps_smmu 0x19c2 0x0>;
>> + dma-coherent;
>> + };
>> +
>> + compute-cb@3 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <3>;
>> + iommus = <&apps_smmu 0x1963 0x0>,
>> + <&apps_smmu 0x0c23 0x0>,
>> + <&apps_smmu 0x0c03 0x40>,
>> + <&apps_smmu 0x19c3 0x0>;
>> + dma-coherent;
>> + };
>> +
>> + compute-cb@4 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <4>;
>> + iommus = <&apps_smmu 0x1964 0x0>,
>> + <&apps_smmu 0x0c44 0x0>,
>> + <&apps_smmu 0x0c04 0x20>,
>> + <&apps_smmu 0x19c4 0x0>;
>> + dma-coherent;
>> + };
>> +
>> + compute-cb@5 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <5>;
>> + iommus = <&apps_smmu 0x1965 0x0>,
>> + <&apps_smmu 0x0c45 0x0>,
>> + <&apps_smmu 0x0c05 0x20>,
>> + <&apps_smmu 0x19c5 0x0>;
>> + dma-coherent;
>> + };
>> +
>> + compute-cb@6 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <6>;
>> + iommus = <&apps_smmu 0x1966 0x0>,
>> + <&apps_smmu 0x0c06 0x20>,
>> + <&apps_smmu 0x0c46 0x0>,
>> + <&apps_smmu 0x19c6 0x0>;
>> + dma-coherent;
>> + };
>> +
>> + compute-cb@7 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <7>;
>> + iommus = <&apps_smmu 0x1967 0x0>,
>> + <&apps_smmu 0x0c27 0x0>,
>> + <&apps_smmu 0x0c07 0x40>,
>> + <&apps_smmu 0x19c7 0x0>;
>> + dma-coherent;
>> + };
>> +
>> + compute-cb@8 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <8>;
>> + iommus = <&apps_smmu 0x1968 0x0>,
>> + <&apps_smmu 0x0c08 0x20>,
>> + <&apps_smmu 0x0c48 0x0>,
>> + <&apps_smmu 0x19c8 0x0>;
>> + dma-coherent;
>> + };
>> +
>> + /* note: secure cb9 in downstream */
>> +
>> + compute-cb@12 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <12>;
>> + iommus = <&apps_smmu 0x196c 0x0>,
>> + <&apps_smmu 0x0c2c 0x00>,
>> + <&apps_smmu 0x0c0c 0x40>,
>> + <&apps_smmu 0x19cc 0x0>;
>> + dma-coherent;
>> + };
>> +
>> + compute-cb@13 {
>> + compatible = "qcom,fastrpc-compute-cb";
>> + reg = <13>;
>> + iommus = <&apps_smmu 0x196d 0x0>,
>> + <&apps_smmu 0x0c0d 0x40>,
>> + <&apps_smmu 0x0c2e 0x0>,
>> + <&apps_smmu 0x0c2d 0x0>,
>> + <&apps_smmu 0x19cd 0x0>;
>> + dma-coherent;
>> + };
>> + };
>> + };
>> + };
>> +
>
> Best regards,
> Alexey
>
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 07/20] arm64: dts: qcom: kaanapali: Add remoteprocs for Kaanapali SoC
2025-11-04 8:59 ` Jingyi Wang
@ 2025-11-04 10:01 ` Kumari Pallavi
2025-11-04 13:25 ` Alexey Klimov
0 siblings, 1 reply; 135+ messages in thread
From: Kumari Pallavi @ 2025-11-04 10:01 UTC (permalink / raw)
To: Jingyi Wang, Alexey Klimov, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang
On 11/4/2025 2:29 PM, Jingyi Wang wrote:
>
>
> On 10/1/2025 1:24 AM, Alexey Klimov wrote:
>> On Thu Sep 25, 2025 at 1:17 AM BST, Jingyi Wang wrote:
>>> Add remoteproc PAS loader for ADSP, CDSP, MPSS and SoCCP with
>>> its SMP2P and fastrpc nodes.
>>>
>>> Written with help from Kumari Pallavi(added fastrpc).
>>
>> Co-developed-by tag then maybe?
>>
>> Also I don't see this name in email addresses.
>>
>
> Hi Alexey,
>
> We got review comments to merge dt changes in one patch, we are still discussing on
> how to organize next version, I think we can add the Co-developed-by tag if remoteproc
> is sent as a single patch in next version, "Written with" description will be used
> to avoid SOB chain too long.
>
> Thanks,
> Jingyi
>
>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 484 ++++++++++++++++++++++++++++++++
>>> 1 file changed, 484 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>>> index 08ab267bf9a7..c3b38fd851c5 100644
>>> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>>> @@ -438,6 +438,121 @@ rmtfs_mem: rmtfs@d7c00000 {
>>> };
>>> };
>>
>> [...]
>>
>>> + remoteproc_adsp: remoteproc@6800000 {
>>> + compatible = "qcom,kaanapali-adsp-pas", "qcom,sm8550-adsp-pas";
>>> + reg = <0x0 0x06800000 0x0 0x10000>;
>>> +
>>> + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
>>> + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
>>> + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
>>> + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
>>> + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
>>> + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
>>> + interrupt-names = "wdog",
>>> + "fatal",
>>> + "ready",
>>> + "handover",
>>> + "stop-ack",
>>> + "shutdown-ack";
>>> +
>>> + clocks = <&rpmhcc RPMH_CXO_CLK>;
>>> + clock-names = "xo";
>>> +
>>> + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
>>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
>>> +
>>> + power-domains = <&rpmhpd RPMHPD_LCX>,
>>> + <&rpmhpd RPMHPD_LMX>;
>>> + power-domain-names = "lcx",
>>> + "lmx";
>>> +
>>> + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
>>> +
>>> + qcom,qmp = <&aoss_qmp>;
>>> +
>>> + qcom,smem-states = <&smp2p_adsp_out 0>;
>>> + qcom,smem-state-names = "stop";
>>> +
>>> + status = "disabled";
>>> +
>>> + remoteproc_adsp_glink: glink-edge {
>>> + interrupts-extended = <&ipcc IPCC_MPROC_LPASS
>>> + IPCC_MPROC_SIGNAL_GLINK_QMP
>>> + IRQ_TYPE_EDGE_RISING>;
>>> +
>>> + mboxes = <&ipcc IPCC_MPROC_LPASS
>>> + IPCC_MPROC_SIGNAL_GLINK_QMP>;
>>> +
>>> + qcom,remote-pid = <2>;
>>> +
>>> + label = "lpass";
>>> +
>>> + fastrpc {
>>> + compatible = "qcom,fastrpc";
>>> + qcom,glink-channels = "fastrpcglink-apps-dsp";
>>> + label = "adsp";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + compute-cb@3 {
>>> + compatible = "qcom,fastrpc-compute-cb";
>>> + reg = <3>;
>>> +
>>> + iommus = <&apps_smmu 0x1003 0x80>,
>>> + <&apps_smmu 0x1043 0x20>;
>>> + dma-coherent;
>>> + };
>>> +
>>> + compute-cb@4 {
>>> + compatible = "qcom,fastrpc-compute-cb";
>>> + reg = <4>;
>>> +
>>> + iommus = <&apps_smmu 0x1004 0x80>,
>>> + <&apps_smmu 0x1044 0x20>;
>>> + dma-coherent;
>>> + };
>>> +
>>> + compute-cb@5 {
>>> + compatible = "qcom,fastrpc-compute-cb";
>>> + reg = <5>;
>>> +
>>> + iommus = <&apps_smmu 0x1005 0x80>,
>>> + <&apps_smmu 0x1045 0x20>;
>>> + dma-coherent;
>>> + };
>>> +
>>> + compute-cb@6 {
>>> + compatible = "qcom,fastrpc-compute-cb";
>>> + reg = <6>;
>>> +
>>> + iommus = <&apps_smmu 0x1006 0x80>,
>>> + <&apps_smmu 0x1046 0x20>;
>>> + dma-coherent;
>>> + };
>>> +
>>> + compute-cb@7 {
>>> + compatible = "qcom,fastrpc-compute-cb";
>>> + reg = <7>;
>>> +
>>> + iommus = <&apps_smmu 0x1007 0x40>,
>>> + <&apps_smmu 0x1067 0x0>,
>>> + <&apps_smmu 0x1087 0x0>;
>>> + dma-coherent;
>>> + };
>>> + };
>>> + };
>>> + };
>>
>> Fastrpc nodes here. Was this tested? If yes, then how?
>> Or was it just copied from somewhere from downstream?
>>
>> The same questions basically go for cdsp fastrpc too.
>>
>
> +Kumari, could you please comment on this?
>
I verified the CDSP and ADSP nodes by running the tests available at
https://github.com/qualcomm/fastrpc/tree/development/test. Upon
successful execution, the message "All tests completed successfully" is
displayed.
>>
>> [..]
>>
>>> + label = "cdsp";
>>> +
>>> + fastrpc {
>>> + compatible = "qcom,fastrpc";
>>> + qcom,glink-channels = "fastrpcglink-apps-dsp";
>>> + label = "cdsp";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + compute-cb@1 {
>>> + compatible = "qcom,fastrpc-compute-cb";
>>> + reg = <1>;
>>> + iommus = <&apps_smmu 0x19c1 0x0>,
>>> + <&apps_smmu 0x1961 0x0>,
>>> + <&apps_smmu 0x0c21 0x0>,
>>> + <&apps_smmu 0x0c01 0x40>;
>>> + dma-coherent;
>>> + };
>>> +
>>> + compute-cb@2 {
>>> + compatible = "qcom,fastrpc-compute-cb";
>>> + reg = <2>;
>>> + iommus = <&apps_smmu 0x1962 0x0>,
>>> + <&apps_smmu 0x0c02 0x20>,
>>> + <&apps_smmu 0x0c42 0x0>,
>>> + <&apps_smmu 0x19c2 0x0>;
>>> + dma-coherent;
>>> + };
>>> +
>>> + compute-cb@3 {
>>> + compatible = "qcom,fastrpc-compute-cb";
>>> + reg = <3>;
>>> + iommus = <&apps_smmu 0x1963 0x0>,
>>> + <&apps_smmu 0x0c23 0x0>,
>>> + <&apps_smmu 0x0c03 0x40>,
>>> + <&apps_smmu 0x19c3 0x0>;
>>> + dma-coherent;
>>> + };
>>> +
>>> + compute-cb@4 {
>>> + compatible = "qcom,fastrpc-compute-cb";
>>> + reg = <4>;
>>> + iommus = <&apps_smmu 0x1964 0x0>,
>>> + <&apps_smmu 0x0c44 0x0>,
>>> + <&apps_smmu 0x0c04 0x20>,
>>> + <&apps_smmu 0x19c4 0x0>;
>>> + dma-coherent;
>>> + };
>>> +
>>> + compute-cb@5 {
>>> + compatible = "qcom,fastrpc-compute-cb";
>>> + reg = <5>;
>>> + iommus = <&apps_smmu 0x1965 0x0>,
>>> + <&apps_smmu 0x0c45 0x0>,
>>> + <&apps_smmu 0x0c05 0x20>,
>>> + <&apps_smmu 0x19c5 0x0>;
>>> + dma-coherent;
>>> + };
>>> +
>>> + compute-cb@6 {
>>> + compatible = "qcom,fastrpc-compute-cb";
>>> + reg = <6>;
>>> + iommus = <&apps_smmu 0x1966 0x0>,
>>> + <&apps_smmu 0x0c06 0x20>,
>>> + <&apps_smmu 0x0c46 0x0>,
>>> + <&apps_smmu 0x19c6 0x0>;
>>> + dma-coherent;
>>> + };
>>> +
>>> + compute-cb@7 {
>>> + compatible = "qcom,fastrpc-compute-cb";
>>> + reg = <7>;
>>> + iommus = <&apps_smmu 0x1967 0x0>,
>>> + <&apps_smmu 0x0c27 0x0>,
>>> + <&apps_smmu 0x0c07 0x40>,
>>> + <&apps_smmu 0x19c7 0x0>;
>>> + dma-coherent;
>>> + };
>>> +
>>> + compute-cb@8 {
>>> + compatible = "qcom,fastrpc-compute-cb";
>>> + reg = <8>;
>>> + iommus = <&apps_smmu 0x1968 0x0>,
>>> + <&apps_smmu 0x0c08 0x20>,
>>> + <&apps_smmu 0x0c48 0x0>,
>>> + <&apps_smmu 0x19c8 0x0>;
>>> + dma-coherent;
>>> + };
>>> +
>>> + /* note: secure cb9 in downstream */
>>> +
>>> + compute-cb@12 {
>>> + compatible = "qcom,fastrpc-compute-cb";
>>> + reg = <12>;
>>> + iommus = <&apps_smmu 0x196c 0x0>,
>>> + <&apps_smmu 0x0c2c 0x00>,
>>> + <&apps_smmu 0x0c0c 0x40>,
>>> + <&apps_smmu 0x19cc 0x0>;
>>> + dma-coherent;
>>> + };
>>> +
>>> + compute-cb@13 {
>>> + compatible = "qcom,fastrpc-compute-cb";
>>> + reg = <13>;
>>> + iommus = <&apps_smmu 0x196d 0x0>,
>>> + <&apps_smmu 0x0c0d 0x40>,
>>> + <&apps_smmu 0x0c2e 0x0>,
>>> + <&apps_smmu 0x0c2d 0x0>,
>>> + <&apps_smmu 0x19cd 0x0>;
>>> + dma-coherent;
>>> + };
>>> + };
>>> + };
>>> + };
>>> +
>>
>> Best regards,
>> Alexey
>>
>
Thanks,
Pallavi
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 07/20] arm64: dts: qcom: kaanapali: Add remoteprocs for Kaanapali SoC
2025-11-04 10:01 ` Kumari Pallavi
@ 2025-11-04 13:25 ` Alexey Klimov
0 siblings, 0 replies; 135+ messages in thread
From: Alexey Klimov @ 2025-11-04 13:25 UTC (permalink / raw)
To: Kumari Pallavi, Jingyi Wang, Alexey Klimov, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang
On Tue Nov 4, 2025 at 10:01 AM GMT, Kumari Pallavi wrote:
>
>
> On 11/4/2025 2:29 PM, Jingyi Wang wrote:
>>
>>
>> On 10/1/2025 1:24 AM, Alexey Klimov wrote:
>>> On Thu Sep 25, 2025 at 1:17 AM BST, Jingyi Wang wrote:
>>>> Add remoteproc PAS loader for ADSP, CDSP, MPSS and SoCCP with
>>>> its SMP2P and fastrpc nodes.
[..]
>>> Fastrpc nodes here. Was this tested? If yes, then how?
>>> Or was it just copied from somewhere from downstream?
>>>
>>> The same questions basically go for cdsp fastrpc too.
>>>
>>
>> +Kumari, could you please comment on this?
>>
>
> I verified the CDSP and ADSP nodes by running the tests available at
> https://github.com/qualcomm/fastrpc/tree/development/test. Upon
> successful execution, the message "All tests completed successfully" is
> displayed.
Sounds good. Thanks.
Best regards,
Alexey
^ permalink raw reply [flat|nested] 135+ messages in thread
* [PATCH 08/20] arm64: dts: qcom: Add PMK8850 pmic dtsi
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (6 preceding siblings ...)
2025-09-25 0:17 ` [PATCH 07/20] arm64: dts: qcom: kaanapali: Add remoteprocs " Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-09-25 12:20 ` Konrad Dybcio
2025-09-25 0:17 ` [PATCH 09/20] arm64: dts: qcom: Add PMH0101 " Jingyi Wang
` (14 subsequent siblings)
22 siblings, 1 reply; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang, Jishnu Prakash,
Kamal Wadhwa
From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Add base DTS file for PMK8850 including PON, GPIO, RTC and SDAM nodes.
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/pmk8850.dtsi | 66 +++++++++++++++++++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/pmk8850.dtsi b/arch/arm64/boot/dts/qcom/pmk8850.dtsi
new file mode 100644
index 000000000000..c19a98ca984b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmk8850.dtsi
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus0 {
+ pmic@0 {
+ compatible = "qcom,pmk8850", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmk8850_pon: pon@1300 {
+ compatible = "qcom,pmk8350-pon";
+ reg = <0x1300>, <0x800>;
+ reg-names = "hlos", "pbs";
+
+ pon_pwrkey: pwrkey {
+ compatible = "qcom,pmk8350-pwrkey";
+ interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_POWER>;
+ };
+
+ pon_resin: resin {
+ compatible = "qcom,pmk8350-resin";
+ interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
+ status = "disabled";
+ };
+ };
+
+ pmk8850_gpios: gpio@b800 {
+ compatible = "qcom,pmk8850-gpio", "qcom,spmi-gpio";
+ reg = <0xb800>;
+ gpio-controller;
+ gpio-ranges = <&pmk8850_gpios 0 0 8>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pmk8850_rtc: rtc@6100 {
+ compatible = "qcom,pmk8350-rtc";
+ reg = <0x6100>, <0x6200>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pmk8850_sdam_2: nvram@7100 {
+ compatible = "qcom,spmi-sdam";
+ reg = <0x7100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x7100 0x100>;
+
+ reboot_reason: reboot-reason@48 {
+ reg = <0x48 0x1>;
+ bits = <1 7>;
+ };
+ };
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* Re: [PATCH 08/20] arm64: dts: qcom: Add PMK8850 pmic dtsi
2025-09-25 0:17 ` [PATCH 08/20] arm64: dts: qcom: Add PMK8850 pmic dtsi Jingyi Wang
@ 2025-09-25 12:20 ` Konrad Dybcio
0 siblings, 0 replies; 135+ messages in thread
From: Konrad Dybcio @ 2025-09-25 12:20 UTC (permalink / raw)
To: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jishnu Prakash, Kamal Wadhwa
On 9/25/25 2:17 AM, Jingyi Wang wrote:
> From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
>
> Add base DTS file for PMK8850 including PON, GPIO, RTC and SDAM nodes.
>
> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/pmk8850.dtsi | 66 +++++++++++++++++++++++++++++++++++
> 1 file changed, 66 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/pmk8850.dtsi b/arch/arm64/boot/dts/qcom/pmk8850.dtsi
> new file mode 100644
> index 000000000000..c19a98ca984b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/pmk8850.dtsi
> @@ -0,0 +1,66 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/input/linux-event-codes.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/spmi/spmi.h>
> +
> +&spmi_bus0 {
> + pmic@0 {
> + compatible = "qcom,pmk8850", "qcom,spmi-pmic";
> + reg = <0x0 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pmk8850_pon: pon@1300 {
> + compatible = "qcom,pmk8350-pon";
> + reg = <0x1300>, <0x800>;
> + reg-names = "hlos", "pbs";
1 reg and -name per line, please
[...]
> + pmk8850_rtc: rtc@6100 {
> + compatible = "qcom,pmk8350-rtc";
> + reg = <0x6100>, <0x6200>;
> + reg-names = "rtc", "alarm";
and here
with that:
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread
* [PATCH 09/20] arm64: dts: qcom: Add PMH0101 pmic dtsi
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (7 preceding siblings ...)
2025-09-25 0:17 ` [PATCH 08/20] arm64: dts: qcom: Add PMK8850 pmic dtsi Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-09-25 12:20 ` Konrad Dybcio
2025-09-25 0:17 ` [PATCH 10/20] arm64: dts: qcom: Add PMH0104 " Jingyi Wang
` (13 subsequent siblings)
22 siblings, 1 reply; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang, Jishnu Prakash,
Kamal Wadhwa
From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Add base DTS file for PMH0101 including temp-alarm, GPIO,
PWM and flash nodes.
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/pmh0101.dtsi | 45 +++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/pmh0101.dtsi b/arch/arm64/boot/dts/qcom/pmh0101.dtsi
new file mode 100644
index 000000000000..831c79305f7a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmh0101.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus0 {
+ pmic@1 {
+ compatible = "qcom,pmh0101", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmh0101_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmh0101_gpios: gpio@8800 {
+ compatible = "qcom,pmh0101-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmh0101_gpios 0 0 18>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pmh0101_flash: led-controller@ee00 {
+ compatible = "qcom,pmh0101-flash-led", "qcom,spmi-flash-led";
+ reg = <0xee00>;
+ status = "disabled";
+ };
+
+ pmh0101_pwm: pwm {
+ compatible = "qcom,pmh0101-pwm", "qcom,pm8350c-pwm";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* Re: [PATCH 09/20] arm64: dts: qcom: Add PMH0101 pmic dtsi
2025-09-25 0:17 ` [PATCH 09/20] arm64: dts: qcom: Add PMH0101 " Jingyi Wang
@ 2025-09-25 12:20 ` Konrad Dybcio
2025-10-09 13:47 ` Jishnu Prakash
0 siblings, 1 reply; 135+ messages in thread
From: Konrad Dybcio @ 2025-09-25 12:20 UTC (permalink / raw)
To: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jishnu Prakash, Kamal Wadhwa
On 9/25/25 2:17 AM, Jingyi Wang wrote:
> From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
>
> Add base DTS file for PMH0101 including temp-alarm, GPIO,
> PWM and flash nodes.
>
> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/pmh0101.dtsi | 45 +++++++++++++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/pmh0101.dtsi b/arch/arm64/boot/dts/qcom/pmh0101.dtsi
> new file mode 100644
> index 000000000000..831c79305f7a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/pmh0101.dtsi
> @@ -0,0 +1,45 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/spmi/spmi.h>
> +
> +&spmi_bus0 {
> + pmic@1 {
> + compatible = "qcom,pmh0101", "qcom,spmi-pmic";
> + reg = <0x1 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pmh0101_temp_alarm: temp-alarm@a00 {
> + compatible = "qcom,spmi-temp-alarm";
> + reg = <0xa00>;
> + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
> + #thermal-sensor-cells = <0>;
> + };
> +
> + pmh0101_gpios: gpio@8800 {
> + compatible = "qcom,pmh0101-gpio", "qcom,spmi-gpio";
> + reg = <0x8800>;
> + gpio-controller;
> + gpio-ranges = <&pmh0101_gpios 0 0 18>;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + pmh0101_flash: led-controller@ee00 {
> + compatible = "qcom,pmh0101-flash-led", "qcom,spmi-flash-led";
> + reg = <0xee00>;
> + status = "disabled";
> + };
> +
> + pmh0101_pwm: pwm {
> + compatible = "qcom,pmh0101-pwm", "qcom,pm8350c-pwm";
> + #pwm-cells = <2>;
> + status = "disabled";
> + };
Any reason for these to be disabled?
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 09/20] arm64: dts: qcom: Add PMH0101 pmic dtsi
2025-09-25 12:20 ` Konrad Dybcio
@ 2025-10-09 13:47 ` Jishnu Prakash
0 siblings, 0 replies; 135+ messages in thread
From: Jishnu Prakash @ 2025-10-09 13:47 UTC (permalink / raw)
To: Konrad Dybcio, Jingyi Wang, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Kamal Wadhwa
Hi Konrad,
On 9/25/2025 5:50 PM, Konrad Dybcio wrote:
> On 9/25/25 2:17 AM, Jingyi Wang wrote:
>> From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
>>
>> Add base DTS file for PMH0101 including temp-alarm, GPIO,
>> PWM and flash nodes.
>>
>> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
>> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/pmh0101.dtsi | 45 +++++++++++++++++++++++++++++++++++
>> 1 file changed, 45 insertions(+)
>>
...
>> +
>> + pmh0101_flash: led-controller@ee00 {
>> + compatible = "qcom,pmh0101-flash-led", "qcom,spmi-flash-led";
>> + reg = <0xee00>;
>> + status = "disabled";
>> + };
>> +
>> + pmh0101_pwm: pwm {
>> + compatible = "qcom,pmh0101-pwm", "qcom,pm8350c-pwm";
>> + #pwm-cells = <2>;
>> + status = "disabled";
>> + };
>
> Any reason for these to be disabled?
PMH0101 is used on both Kaanapali and Glymur, but the flash and PWM
peripherals are used on Kaanapali alone and not Glymur, so we
kept them disabled by default and enabled them in the Kaanapali
board files where they would be used.
Thanks,
Jishnu
>
> Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread
* [PATCH 10/20] arm64: dts: qcom: Add PMH0104 pmic dtsi
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (8 preceding siblings ...)
2025-09-25 0:17 ` [PATCH 09/20] arm64: dts: qcom: Add PMH0101 " Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-09-25 7:59 ` Krzysztof Kozlowski
2025-09-25 0:17 ` [PATCH 11/20] arm64: dts: qcom: Add PMH0110 " Jingyi Wang
` (12 subsequent siblings)
22 siblings, 1 reply; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang, Jishnu Prakash,
Kamal Wadhwa
From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Add base DTS file for PMH0104 inclduing temp-alarm and GPIO nodes.
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/pmh0104.dtsi | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/pmh0104.dtsi b/arch/arm64/boot/dts/qcom/pmh0104.dtsi
new file mode 100644
index 000000000000..f5393fdebe95
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmh0104.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus1 {
+ pmh0104_j_e1: pmic@PMH0104_J_E1_SID {
+ compatible = "qcom,pmh0104", "qcom,spmi-pmic";
+ reg = <PMH0104_J_E1_SID SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmh0104_j_e1_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <PMH0104_J_E1_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmh0104_j_e1_gpios: gpio@8800 {
+ compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmh0104_j_e1_gpios 0 0 8>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* Re: [PATCH 10/20] arm64: dts: qcom: Add PMH0104 pmic dtsi
2025-09-25 0:17 ` [PATCH 10/20] arm64: dts: qcom: Add PMH0104 " Jingyi Wang
@ 2025-09-25 7:59 ` Krzysztof Kozlowski
2025-09-25 12:21 ` Konrad Dybcio
0 siblings, 1 reply; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-25 7:59 UTC (permalink / raw)
To: Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jishnu Prakash,
Kamal Wadhwa
On Thu, 25 Sept 2025 at 09:17, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
>
> From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
>
> Add base DTS file for PMH0104 inclduing temp-alarm and GPIO nodes.
>
> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/pmh0104.dtsi | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/pmh0104.dtsi b/arch/arm64/boot/dts/qcom/pmh0104.dtsi
> new file mode 100644
> index 000000000000..f5393fdebe95
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/pmh0104.dtsi
> @@ -0,0 +1,33 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/spmi/spmi.h>
> +
> +&spmi_bus1 {
> + pmh0104_j_e1: pmic@PMH0104_J_E1_SID {
This might be fine for Kaanapali, but it's wrong for Glymur.
We discussed it already and I'm surprised you come with completely
different solution, not talking with the community, not aligning to
solve it properly.
Judging by other patches sent now, I recommend to drop it.
And instead just join the talks... Otherwise how am I suppose to look
at this? Everything I said should be repeated?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 10/20] arm64: dts: qcom: Add PMH0104 pmic dtsi
2025-09-25 7:59 ` Krzysztof Kozlowski
@ 2025-09-25 12:21 ` Konrad Dybcio
2025-09-29 6:51 ` Aiqun(Maria) Yu
0 siblings, 1 reply; 135+ messages in thread
From: Konrad Dybcio @ 2025-09-25 12:21 UTC (permalink / raw)
To: Krzysztof Kozlowski, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jishnu Prakash,
Kamal Wadhwa
On 9/25/25 9:59 AM, Krzysztof Kozlowski wrote:
> On Thu, 25 Sept 2025 at 09:17, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
>>
>> From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
>>
>> Add base DTS file for PMH0104 inclduing temp-alarm and GPIO nodes.
>>
>> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
>> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/pmh0104.dtsi | 33 +++++++++++++++++++++++++++++++++
>> 1 file changed, 33 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/pmh0104.dtsi b/arch/arm64/boot/dts/qcom/pmh0104.dtsi
>> new file mode 100644
>> index 000000000000..f5393fdebe95
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/pmh0104.dtsi
>> @@ -0,0 +1,33 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/spmi/spmi.h>
>> +
>> +&spmi_bus1 {
>> + pmh0104_j_e1: pmic@PMH0104_J_E1_SID {
>
>
> This might be fine for Kaanapali, but it's wrong for Glymur.
>
> We discussed it already and I'm surprised you come with completely
> different solution, not talking with the community, not aligning to
> solve it properly.
I think I omitted said discussion.. if it was in public, could you share
a reference here, and if not, would you happen to have it saved somewhere
that you could forward to me?
Konrad
>
> Judging by other patches sent now, I recommend to drop it.
>
> And instead just join the talks... Otherwise how am I suppose to look
> at this? Everything I said should be repeated?
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 10/20] arm64: dts: qcom: Add PMH0104 pmic dtsi
2025-09-25 12:21 ` Konrad Dybcio
@ 2025-09-29 6:51 ` Aiqun(Maria) Yu
0 siblings, 0 replies; 135+ messages in thread
From: Aiqun(Maria) Yu @ 2025-09-29 6:51 UTC (permalink / raw)
To: Konrad Dybcio, Krzysztof Kozlowski, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
tingwei.zhang, trilok.soni, yijie.yang, Jishnu Prakash,
Kamal Wadhwa
On 9/25/2025 8:21 PM, Konrad Dybcio wrote:
> On 9/25/25 9:59 AM, Krzysztof Kozlowski wrote:
>> On Thu, 25 Sept 2025 at 09:17, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
>>>
>>> From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
>>>
>>> Add base DTS file for PMH0104 inclduing temp-alarm and GPIO nodes.
>>>
>>> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
>>> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/pmh0104.dtsi | 33 +++++++++++++++++++++++++++++++++
>>> 1 file changed, 33 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/pmh0104.dtsi b/arch/arm64/boot/dts/qcom/pmh0104.dtsi
>>> new file mode 100644
>>> index 000000000000..f5393fdebe95
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/qcom/pmh0104.dtsi
>>> @@ -0,0 +1,33 @@
>>> +// SPDX-License-Identifier: BSD-3-Clause
>>> +/*
>>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>>> + */
>>> +
>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>> +#include <dt-bindings/spmi/spmi.h>
>>> +
>>> +&spmi_bus1 {
>>> + pmh0104_j_e1: pmic@PMH0104_J_E1_SID {
>>
>>
>> This might be fine for Kaanapali, but it's wrong for Glymur.
>>
>> We discussed it already and I'm surprised you come with completely
>> different solution, not talking with the community, not aligning to
>> solve it properly.
>
> I think I omitted said discussion.. if it was in public, could you share
> a reference here, and if not, would you happen to have it saved somewhere
> that you could forward to me?
>
> Konrad
>>
>> Judging by other patches sent now, I recommend to drop it.
>>
>> And instead just join the talks... Otherwise how am I suppose to look
Could you include the talks with us?
I've discussed with Jishnu, Kamal and Rajendra before the patches send here.
The conclusion is Kaanapali should be post as it is here.
Feel free to have me in this followed discussion.
>> at this? Everything I said should be repeated?
>>
>> Best regards,
>> Krzysztof
>>
--
Thx and BRs,
Aiqun(Maria) Yu
^ permalink raw reply [flat|nested] 135+ messages in thread
* [PATCH 11/20] arm64: dts: qcom: Add PMH0110 pmic dtsi
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (9 preceding siblings ...)
2025-09-25 0:17 ` [PATCH 10/20] arm64: dts: qcom: Add PMH0104 " Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-09-25 0:17 ` [PATCH 12/20] arm64: dts: qcom: kaanapali: Add misc features Jingyi Wang
` (11 subsequent siblings)
22 siblings, 0 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang, Jishnu Prakash,
Kamal Wadhwa
From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Add base DTS file for PMH0110 including temp-alarm and GPIO nodes.
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/pmh0110.dtsi | 109 ++++++++++++++++++++++++++++++++++
1 file changed, 109 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/pmh0110.dtsi b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
new file mode 100644
index 000000000000..b99c33cba886
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: BSD-3-Clause-Clear
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus0 {
+ pmh0110_d_e0: pmic@PMH0110_D_E0_SID {
+ compatible = "qcom,pmh0110", "qcom,spmi-pmic";
+ reg = <PMH0110_D_E0_SID SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pmh0110_d_e0_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <PMH0110_D_E0_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmh0110_d_e0_gpios: gpio@8800 {
+ compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmh0110_d_e0_gpios 0 0 14>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmh0110_f_e0: pmic@PMH0110_F_E0_SID {
+ compatible = "qcom,pmh0110", "qcom,spmi-pmic";
+ reg = <PMH0110_F_E0_SID SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pmh0110_f_e0_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <PMH0110_F_E0_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmh0110_f_e0_gpios: gpio@8800 {
+ compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmh0110_f_e0_gpios 0 0 14>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmh0110_g_e0: pmic@PMH0110_G_E0_SID {
+ compatible = "qcom,pmh0110", "qcom,spmi-pmic";
+ reg = <PMH0110_G_E0_SID SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pmh0110_g_e0_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <PMH0110_G_E0_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmh0110_g_e0_gpios: gpio@8800 {
+ compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmh0110_g_e0_gpios 0 0 14>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmh0110_i_e0: pmic@PMH0110_I_E0_SID {
+ compatible = "qcom,pmh0110", "qcom,spmi-pmic";
+ reg = <PMH0110_I_E0_SID SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pmh0110_i_e0_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <PMH0110_I_E0_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmh0110_i_e0_gpios: gpio@8800 {
+ compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmh0110_i_e0_gpios 0 0 14>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* [PATCH 12/20] arm64: dts: qcom: kaanapali: Add misc features
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (10 preceding siblings ...)
2025-09-25 0:17 ` [PATCH 11/20] arm64: dts: qcom: Add PMH0110 " Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-09-25 0:17 ` [PATCH 13/20] arm64: dts: qcom: kaanapali: Add QUPv3 configuration for serial engines Jingyi Wang
` (10 subsequent siblings)
22 siblings, 0 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang
Add more features for Kaanapali SoC including spmi-bus, tsens,
random number generator (RNG), Qcrypto and coresight.
Written with help from Jishnu Prakash(added spmi-bus), Gaurav Kashyap
(added crypto), Manaf Meethalavalappu Pallikunhi(added tsens) and
Jinlong Mao(added coresight).
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 927 ++++++++++++++++++++++++++++++++
1 file changed, 927 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index c3b38fd851c5..6ed7acdb871e 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -671,6 +671,11 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
};
};
+ rng: rng@10c3000 {
+ compatible = "qcom,kaanapali-trng", "qcom,trng";
+ reg = <0x0 0x010c3000 0x0 0x1000>;
+ };
+
ipcc: mailbox@1106000 {
compatible = "qcom,kaanapali-ipcc", "qcom,ipcc";
reg = <0x0 0x01106000 0x0 0x1000>;
@@ -1034,6 +1039,39 @@ ice: crypto@1d88000 {
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
};
+ cryptobam: dma-controller@1dc4000 {
+ compatible = "qcom,bam-crypto-v6";
+ reg = <0x0 0x01dc4000 0x0 0x22000>;
+
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+
+ #dma-cells = <1>;
+
+ iommus = <&apps_smmu 0xc0 0x0>,
+ <&apps_smmu 0xc1 0x0>;
+
+ qcom,ee = <0>;
+ qcom,num-ees = <4>;
+ num-channels = <16>;
+ qcom,controlled-remotely;
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,kaanapali-qce", "qcom,sm8150-qce", "qcom,qce";
+ reg = <0x0 0x01dfa000 0x0 0x6000>;
+
+ interconnects = <&aggre_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "memory";
+
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+
+ iommus = <&apps_smmu 0xc0 0x0>,
+ <&apps_smmu 0xc1 0x0>;
+
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x20000>;
@@ -1472,6 +1510,90 @@ pdc: interrupt-controller@b220000 {
interrupt-controller;
};
+ tsens0: thermal-sensor@c229000 {
+ compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c229000 0x0 0x1000>,
+ <0x0 0x0c222000 0x0 0x1000>;
+ interrupts = <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+ #qcom,sensors = <5>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: thermal-sensor@c22a000 {
+ compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c22a000 0x0 0x1000>,
+ <0x0 0x0c223000 0x0 0x1000>;
+ interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+ #qcom,sensors = <12>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens2: thermal-sensor@c22b000 {
+ compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c22b000 0x0 0x1000>,
+ <0x0 0x0c224000 0x0 0x1000>;
+ interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+ #qcom,sensors = <7>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens3: thermal-sensor@c22c000 {
+ compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c22c000 0x0 0x1000>,
+ <0x0 0x0c225000 0x0 0x1000>;
+ interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+ #qcom,sensors = <4>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens4: thermal-sensor@c22d000 {
+ compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c22d000 0x0 0x1000>,
+ <0x0 0x0c226000 0x0 0x1000>;
+ interrupts = <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+ #qcom,sensors = <8>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens5: thermal-sensor@c22e000 {
+ compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c22e000 0x0 0x1000>,
+ <0x0 0x0c227000 0x0 0x1000>;
+ interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+ #qcom,sensors = <12>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens6: thermal-sensor@c22f000 {
+ compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c22f000 0x0 0x1000>,
+ <0x0 0x0c228000 0x0 0x1000>;
+ interrupts = <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+ #qcom,sensors = <7>;
+ #thermal-sensor-cells = <1>;
+ };
+
aoss_qmp: power-management@c300000 {
compatible = "qcom,kaanapali-aoss-qmp", "qcom,aoss-qmp";
reg = <0x0 0x0c300000 0x0 0x400>;
@@ -1486,6 +1608,53 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
#clock-cells = <0>;
};
+ pmic_arbiter: arbiter@c400000 {
+ compatible = "qcom,kaanapali-spmi-pmic-arb", "qcom,glymur-spmi-pmic-arb";
+ reg = <0x0 0x0c400000 0x0 0x3000>,
+ <0x0 0x0c900000 0x0 0x400000>,
+ <0x0 0x0c4c0000 0x0 0x400000>,
+ <0x0 0x0c403000 0x0 0x8000>;
+ reg-names = "core",
+ "chnls",
+ "obsrvr",
+ "chnl_map";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ qcom,channel = <0>;
+ qcom,ee = <0>;
+
+ spmi_bus0: spmi@c426000 {
+ reg = <0x0 0x0c426000 0x0 0x4000>,
+ <0x0 0x0c8c0000 0x0 0x10000>,
+ <0x0 0x0c42a000 0x0 0x8000>;
+ reg-names = "cnfg",
+ "intr",
+ "chnl_owner";
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+
+ spmi_bus1: spmi@c437000 {
+ reg = <0x0 0x0c437000 0x0 0x4000>,
+ <0x0 0x0c8d0000 0x0 0x10000>,
+ <0x0 0x0c43b000 0x0 0x8000>;
+ reg-names = "cnfg",
+ "intr",
+ "chnl_owner";
+ interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+ };
+
tlmm: pinctrl@f100000 {
compatible = "qcom,kaanapali-tlmm";
reg = <0x0 0x0f100000 0x0 0x300000>;
@@ -1560,6 +1729,103 @@ card-detect-pins {
};
};
+ stm@10002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0x0 0x10002000 0x0 0x1000>,
+ <0x0 0x16280000 0x0 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ stm_out_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel_in0_in_stm>;
+ };
+ };
+ };
+ };
+
+ funnel@10041000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10041000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@7 {
+ reg = <7>;
+ funnel_in0_in_stm: endpoint {
+ remote-endpoint =
+ <&stm_out_funnel_in0>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_in0_out_funnel_aoss: endpoint {
+ remote-endpoint =
+ <&funnel_aoss_in_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@11304000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+ reg = <0x0 0x11304000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@6 {
+ reg = <6>;
+ funnel_aoss_in_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel_in0_out_funnel_aoss>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_aoss_out_tmc_etf: endpoint {
+ remote-endpoint =
+ <&tmc_etf_in_funnel_aoss>;
+ };
+ };
+ };
+ };
+
+ tmc@11305000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x11305000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ tmc_etf_in_funnel_aoss: endpoint {
+ remote-endpoint =
+ <&funnel_aoss_out_tmc_etf>;
+ };
+ };
+ };
+ };
+
sram@14680000 {
compatible = "qcom,kaanapali-imem", "syscon", "simple-mfd";
reg = <0x0 0x14680000 0x0 0x1000>;
@@ -2232,6 +2498,667 @@ pdp_tx: scp-sram-section@100 {
};
};
+ thermal-zones {
+ cpullc-0-0-thermal {
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ cpullc-0-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpullc-0-1-thermal {
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ cpullc-0-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-0-0-thermal {
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ qmx-0-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-0-1-thermal {
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ qmx-0-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-0-2-thermal {
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ qmx-0-2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-0-0-thermal {
+ thermal-sensors = <&tsens1 0>;
+
+ trips {
+ cpu-0-0-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-0-1-thermal {
+ thermal-sensors = <&tsens1 1>;
+
+ trips {
+ cpu-0-0-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-1-0-thermal {
+ thermal-sensors = <&tsens1 2>;
+
+ trips {
+ cpu-0-1-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-1-1-thermal {
+ thermal-sensors = <&tsens1 3>;
+
+ trips {
+ cpu-0-1-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-2-0-thermal {
+ thermal-sensors = <&tsens1 4>;
+
+ trips {
+ cpu-0-2-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-2-1-thermal {
+ thermal-sensors = <&tsens1 5>;
+
+ trips {
+ cpu-0-2-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-3-0-thermal {
+ thermal-sensors = <&tsens1 6>;
+
+ trips {
+ cpu-0-3-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-3-1-thermal {
+ thermal-sensors = <&tsens1 7>;
+
+ trips {
+ cpu-0-3-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-4-0-thermal {
+ thermal-sensors = <&tsens1 8>;
+
+ trips {
+ cpu-0-4-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-4-1-thermal {
+ thermal-sensors = <&tsens1 9>;
+
+ trips {
+ cpu-0-4-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-5-0-thermal {
+ thermal-sensors = <&tsens1 10>;
+
+ trips {
+ cpu-0-5-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-5-1-thermal {
+ thermal-sensors = <&tsens1 11>;
+
+ trips {
+ cpu-0-5-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpullc-1-0-thermal {
+ thermal-sensors = <&tsens2 0>;
+
+ trips {
+ cpullc-1-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpullc-1-1-thermal {
+ thermal-sensors = <&tsens2 1>;
+
+ trips {
+ cpullc-1-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-1-0-thermal {
+ thermal-sensors = <&tsens2 2>;
+
+ trips {
+ qmx-1-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-1-1-thermal {
+ thermal-sensors = <&tsens2 3>;
+
+ trips {
+ qmx-1-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-1-2-thermal {
+ thermal-sensors = <&tsens2 4>;
+
+ trips {
+ qmx-1-2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-1-3-thermal {
+ thermal-sensors = <&tsens2 5>;
+
+ trips {
+ qmx-1-3-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-1-4-thermal {
+ thermal-sensors = <&tsens2 6>;
+
+ trips {
+ qmx-1-4-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-0-0-thermal {
+ thermal-sensors = <&tsens3 0>;
+
+ trips {
+ cpu-1-0-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-0-1-thermal {
+ thermal-sensors = <&tsens3 1>;
+
+ trips {
+ cpu-1-0-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-1-0-thermal {
+ thermal-sensors = <&tsens3 2>;
+
+ trips {
+ cpu-1-1-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-1-1-thermal {
+ thermal-sensors = <&tsens3 3>;
+
+ trips {
+ cpu-1-1-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphvx-0-thermal {
+ thermal-sensors = <&tsens4 0>;
+
+ trips {
+ nsphvx-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphvx-1-thermal {
+ thermal-sensors = <&tsens4 1>;
+
+ trips {
+ nsphvx-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphvx-2-thermal {
+ thermal-sensors = <&tsens4 2>;
+
+ trips {
+ nsphvx-2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphvx-3-thermal {
+ thermal-sensors = <&tsens4 3>;
+
+ trips {
+ nsphvx-3-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx-0-thermal {
+ thermal-sensors = <&tsens4 4>;
+
+ trips {
+ nsphmx-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx-1-thermal {
+ thermal-sensors = <&tsens4 5>;
+
+ trips {
+ nsphmx-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx-2-thermal {
+ thermal-sensors = <&tsens4 6>;
+
+ trips {
+ nsphmx-2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx-3-thermal {
+ thermal-sensors = <&tsens4 7>;
+
+ trips {
+ nsphmx-3-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-0-thermal {
+ thermal-sensors = <&tsens5 0>;
+
+ trips {
+ gpuss-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-1-thermal {
+ thermal-sensors = <&tsens5 1>;
+
+ trips {
+ gpuss-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-2-thermal {
+ thermal-sensors = <&tsens5 2>;
+
+ trips {
+ gpuss-2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-3-thermal {
+ thermal-sensors = <&tsens5 3>;
+
+ trips {
+ gpuss-3-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-4-thermal {
+ thermal-sensors = <&tsens5 4>;
+
+ trips {
+ gpuss-4-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-5-thermal {
+ thermal-sensors = <&tsens5 5>;
+
+ trips {
+ gpuss-5-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-6-thermal {
+ thermal-sensors = <&tsens5 6>;
+
+ trips {
+ gpuss-6-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-7-thermal {
+ thermal-sensors = <&tsens5 7>;
+
+ trips {
+ gpuss-7-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-8-thermal {
+ thermal-sensors = <&tsens5 8>;
+
+ trips {
+ gpuss-8-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-9-thermal {
+ thermal-sensors = <&tsens5 9>;
+
+ trips {
+ gpuss-9-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-10-thermal {
+ thermal-sensors = <&tsens5 10>;
+
+ trips {
+ gpuss-10-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddr-thermal {
+ thermal-sensors = <&tsens5 11>;
+
+ trips {
+ ddr-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss-0-thermal {
+ thermal-sensors = <&tsens6 0>;
+
+ trips {
+ mdmss-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss-1-thermal {
+ thermal-sensors = <&tsens6 1>;
+ trips {
+ mdmss-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss-2-thermal {
+ thermal-sensors = <&tsens6 2>;
+
+ trips {
+ mdmss-2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss-3-thermal {
+ thermal-sensors = <&tsens6 3>;
+
+ trips {
+ mdmss-3-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera-0-thermal {
+ thermal-sensors = <&tsens6 4>;
+
+ trips {
+ camera-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera-1-thermal {
+ thermal-sensors = <&tsens6 5>;
+
+ trips {
+ camera-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ video-thermal {
+ thermal-sensors = <&tsens6 6>;
+
+ trips {
+ video-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* [PATCH 13/20] arm64: dts: qcom: kaanapali: Add QUPv3 configuration for serial engines
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (11 preceding siblings ...)
2025-09-25 0:17 ` [PATCH 12/20] arm64: dts: qcom: kaanapali: Add misc features Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-09-25 12:28 ` Konrad Dybcio
2025-09-25 0:17 ` [PATCH 14/20] arm64: dts: qcom: kaanapali-mtp: Enable more features Jingyi Wang
` (9 subsequent siblings)
22 siblings, 1 reply; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang, Jyothi Kumar Seerapu
From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
Add device tree support for QUPv3 serial engine protocols on Kaanapali.
Kaanapali has 24 QUP serial engines across 4 QUP wrappers, each with
support of GPI DMA engines, and it also includes 5 I2C hubs.
Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
Co-developed-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 2306 +++++++++++++++++++++++++++++--
1 file changed, 2199 insertions(+), 107 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 6ed7acdb871e..182044f61142 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,kaanapali-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
+#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
@@ -579,6 +580,508 @@ gcc: clock-controller@100000 {
#power-domain-cells = <1>;
};
+ gpi_dma2: dma-controller@800000 {
+ compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x00800000 0x0 0x60000>;
+
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>;
+
+ dma-channels = <12>;
+ dma-channel-mask = <0x1f>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0x436 0x0>;
+ dma-coherent;
+ };
+
+ qupv3_2: geniqup@8c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x008c0000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ iommus = <&apps_smmu 0x423 0x0>;
+
+ dma-coherent;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ i2c8: i2c@880000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00880000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c8_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi8: spi@880000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00880000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c9: i2c@884000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00884000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c9_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi9: spi@884000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00884000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c10: i2c@888000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00888000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c10_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi10: spi@888000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00888000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c11: i2c@88c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x0088c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c11_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi11: spi@88c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x0088c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c12: i2c@890000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00890000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c12_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
+ i2c_master_hub: geniqup@9c0000 {
+ compatible = "qcom,geni-se-i2c-master-hub";
+ reg = <0x0 0x009c0000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
+ clock-names = "s-ahb";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ i2c_hub_0: i2c@980000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x00980000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c0_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_1: i2c@984000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x00984000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c1_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_2: i2c@988000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x00988000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c2_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_3: i2c@98c000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x0098c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c3_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_4: i2c@990000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x00990000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c4_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
+ gpi_dma1: dma-controller@a00000 {
+ compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x00a00000 0x0 0x60000>;
+
+ interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>;
+
+ dma-channels = <12>;
+ dma-channel-mask = <0x1f>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0xb6 0x0>;
+ dma-coherent;
+ };
+
qupv3_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x2000>;
@@ -596,142 +1099,1230 @@ qupv3_1: geniqup@ac0000 {
#size-cells = <2>;
ranges;
- uart7: serial@a9c000 {
- compatible = "qcom,geni-debug-uart";
- reg = <0x0 0x00a9c000 0x0 0x4000>;
+ i2c0: i2c@a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a80000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 828 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c0_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi0: spi@a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a80000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 828 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c1: i2c@a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a84000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 829 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c1_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi1: spi@a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a84000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 829 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c2: i2c@a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a88000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c2_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi2: spi@a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a88000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c3: i2c@a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a8c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi3: spi@a8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a8c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c4: i2c@a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a90000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c4_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi4: spi@a90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a90000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c5: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a94000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c5_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi5: spi@a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a94000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c6: i2c@a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a98000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c6_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi6: spi@a98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a98000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart7: serial@a9c000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x00a9c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart7_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+ };
+
+ remoteproc_soccp: remoteproc-soccp@d00000 {
+ compatible = "qcom,kaanapali-soccp-pas";
+ reg = <0x0 0x00d00000 0x0 0x200000>;
+
+ interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 10 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "pong",
+ "wake-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "cx",
+ "mx";
+
+ memory-region = <&soccp_mem>,
+ <&soccp_dtb_mem>;
+
+ qcom,smem-states = <&soccp_smp2p_out 0>,
+ <&soccp_smp2p_out 10>,
+ <&soccp_smp2p_out 9>,
+ <&soccp_smp2p_out 8>;
+ qcom,smem-state-names = "stop",
+ "wakeup",
+ "sleep",
+ "ping";
+
+ status = "okay";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ qcom,remote-pid = <19>;
+ label = "soccp";
+ };
+ };
+
+ rng: rng@10c3000 {
+ compatible = "qcom,kaanapali-trng", "qcom,trng";
+ reg = <0x0 0x010c3000 0x0 0x1000>;
+ };
+
+ ipcc: mailbox@1106000 {
+ compatible = "qcom,kaanapali-ipcc", "qcom,ipcc";
+ reg = <0x0 0x01106000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ #mbox-cells = <2>;
+ };
+
+ cnoc_main: interconnect@1500000 {
+ compatible = "qcom,kaanapali-cnoc-main";
+ reg = <0x0 0x01500000 0x0 0x1a080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ config_noc: interconnect@1600000 {
+ compatible = "qcom,kaanapali-cnoc-cfg";
+ reg = <0x0 0x01600000 0x0 0x6200>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ system_noc: interconnect@1680000 {
+ compatible = "qcom,kaanapali-system-noc";
+ reg = <0x0 0x01680000 0x0 0x1f080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ pcie_noc: interconnect@16c0000 {
+ compatible = "qcom,kaanapali-pcie-anoc";
+ reg = <0x0 0x016c0000 0x0 0x11400>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
+ };
+
+ aggre_noc: interconnect@16e0000 {
+ compatible = "qcom,kaanapali-aggre-noc";
+ reg = <0x0 0x016e0000 0x0 0x42400>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&rpmhcc RPMH_IPA_CLK>;
+ };
+
+ mmss_noc: interconnect@1780000 {
+ compatible = "qcom,kaanapali-mmss-noc";
+ reg = <0x0 0x01780000 0x0 0x5b800>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ gpi_dma3: dma-controller@1900000 {
+ compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x01900000 0x0 0x60000>;
+
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
+
+ dma-channels = <12>;
+ dma-channel-mask = <0x1e>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0x4d6 0x0>;
+ dma-coherent;
+ };
+
+ qupv3_3: geniqup@19c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x019c0000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ iommus = <&apps_smmu 0x4c3 0x0>;
+
+ dma-coherent;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ i2c13: i2c@1980000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01980000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma3 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c13_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c14: i2c@1984000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01984000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma3 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma3 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c14_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi14: spi@1984000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x01984000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma3 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma3 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c15: i2c@1988000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01988000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma3 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma3 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c15_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi15: spi@1988000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x01988000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma3 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma3 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c16: i2c@198c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x0198c000 0x0 0x4000>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma3 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma3 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c16_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi16: spi@198c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x198c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma3 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma3 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c17: i2c@1990000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01990000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma3 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma3 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c17_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi17: spi@1990000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x01990000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma3 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma3 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart18: serial@1994000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x01994000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart18_default>, <&qup_uart18_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+ };
+
+ gpi_dma4: dma-controller@1a00000 {
+ compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x01a00000 0x0 0x60000>;
+
+ interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
+
+ dma-channels = <12>;
+ dma-channel-mask = <0x1e>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0x536 0x0>;
+ dma-coherent;
+ };
+
+ qupv3_4: geniqup@1ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x01ac0000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_4_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_4_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ iommus = <&apps_smmu 0x523 0x0>;
+
+ dma-coherent;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ i2c19: i2c@1a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01a80000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP4_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma4 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma4 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c19_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi19: spi@1a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x01a80000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP4_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma4 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma4 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c20: i2c@1a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01a84000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP4_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma4 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma4 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c20_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi20: spi@1a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x01a84000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP4_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma4 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma4 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c21: i2c@1a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01a88000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP4_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma4 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma4 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c21_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi21: spi@1a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x01a88000 0x0 0x4000>;
- interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clocks = <&gcc GCC_QUPV3_WRAP4_S2_CLK>;
clock-names = "se";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "qup-core",
"qup-config";
- pinctrl-0 = <&qup_uart7_default>;
+ dmas = <&gpi_dma4 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma4 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
status = "disabled";
};
- };
- remoteproc_soccp: remoteproc-soccp@d00000 {
- compatible = "qcom,kaanapali-soccp-pas";
- reg = <0x0 0x00d00000 0x0 0x200000>;
+ i2c22: i2c@1a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01a8c000 0x0 0x4000>;
- interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
- <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
- <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
- <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
- <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
- <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>,
- <&soccp_smp2p_in 10 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "wdog",
- "fatal",
- "ready",
- "handover",
- "stop-ack",
- "pong",
- "wake-ack";
+ interrupts = <GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "xo";
+ clocks = <&gcc GCC_QUPV3_WRAP4_S3_CLK>;
+ clock-names = "se";
- power-domains = <&rpmhpd RPMHPD_CX>,
- <&rpmhpd RPMHPD_MX>;
- power-domain-names = "cx",
- "mx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
- memory-region = <&soccp_mem>,
- <&soccp_dtb_mem>;
+ dmas = <&gpi_dma4 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma4 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
- qcom,smem-states = <&soccp_smp2p_out 0>,
- <&soccp_smp2p_out 10>,
- <&soccp_smp2p_out 9>,
- <&soccp_smp2p_out 8>;
- qcom,smem-state-names = "stop",
- "wakeup",
- "sleep",
- "ping";
+ pinctrl-0 = <&qup_i2c22_data_clk>;
+ pinctrl-names = "default";
- status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
- glink-edge {
- interrupts-extended = <&ipcc IPCC_MPROC_SOCCP
- IPCC_MPROC_SIGNAL_GLINK_QMP
- IRQ_TYPE_EDGE_RISING>;
- mboxes = <&ipcc IPCC_MPROC_SOCCP
- IPCC_MPROC_SIGNAL_GLINK_QMP>;
- qcom,remote-pid = <19>;
- label = "soccp";
+ status = "disabled";
};
- };
- rng: rng@10c3000 {
- compatible = "qcom,kaanapali-trng", "qcom,trng";
- reg = <0x0 0x010c3000 0x0 0x1000>;
- };
-
- ipcc: mailbox@1106000 {
- compatible = "qcom,kaanapali-ipcc", "qcom,ipcc";
- reg = <0x0 0x01106000 0x0 0x1000>;
+ i2c23: i2c@1a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01a90000 0x0 0x4000>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <3>;
-
- #mbox-cells = <2>;
- };
+ interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
- cnoc_main: interconnect@1500000 {
- compatible = "qcom,kaanapali-cnoc-main";
- reg = <0x0 0x01500000 0x0 0x1a080>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- };
+ clocks = <&gcc GCC_QUPV3_WRAP4_S4_CLK>;
+ clock-names = "se";
- config_noc: interconnect@1600000 {
- compatible = "qcom,kaanapali-cnoc-cfg";
- reg = <0x0 0x01600000 0x0 0x6200>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- };
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
- system_noc: interconnect@1680000 {
- compatible = "qcom,kaanapali-system-noc";
- reg = <0x0 0x01680000 0x0 0x1f080>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- };
+ dmas = <&gpi_dma4 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma4 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
- pcie_noc: interconnect@16c0000 {
- compatible = "qcom,kaanapali-pcie-anoc";
- reg = <0x0 0x016c0000 0x0 0x11400>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
- <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
- };
+ pinctrl-0 = <&qup_i2c23_data_clk>;
+ pinctrl-names = "default";
- aggre_noc: interconnect@16e0000 {
- compatible = "qcom,kaanapali-aggre-noc";
- reg = <0x0 0x016e0000 0x0 0x42400>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
- <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
- <&rpmhcc RPMH_IPA_CLK>;
- };
+ #address-cells = <1>;
+ #size-cells = <0>;
- mmss_noc: interconnect@1780000 {
- compatible = "qcom,kaanapali-mmss-noc";
- reg = <0x0 0x01780000 0x0 0x5b800>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
+ status = "disabled";
+ };
};
pcie0: pcie@1c00000 {
@@ -1666,6 +3257,491 @@ tlmm: pinctrl@f100000 {
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
+ hub_i2c0_data_clk: hub-i2c0-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio66", "gpio67";
+ function = "i2chub0_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c1_data_clk: hub-i2c1-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio78", "gpio79";
+ function = "i2chub0_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c2_data_clk: hub-i2c2-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio68", "gpio69";
+ function = "i2chub0_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c3_data_clk: hub-i2c3-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio70", "gpio71";
+ function = "i2chub0_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c4_data_clk: hub-i2c4-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio72", "gpio73";
+ function = "i2chub0_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c0_data_clk: qup-i2c0-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio80", "gpio83";
+ function = "qup1_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio74", "gpio75";
+ function = "qup1_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio40", "gpio41";
+ function = "qup1_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio44", "gpio45";
+ function = "qup1_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio36", "gpio37";
+ function = "qup1_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio52", "gpio53";
+ function = "qup1_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio56", "gpio57";
+ function = "qup1_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c8_data_clk: qup-i2c8-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio0", "gpio1";
+ function = "qup2_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c9_data_clk: qup-i2c9-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio4", "gpio5";
+ function = "qup2_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c10_data_clk: qup-i2c10-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio117", "gpio118";
+ function = "qup2_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c11_data_clk: qup-i2c11-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio122", "gpio123";
+ function = "qup2_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c12_data_clk: qup-i2c12-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio208", "gpio209";
+ function = "qup2_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c13_data_clk: qup-i2c13-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio64", "gpio65";
+ function = "qup3_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c14_data_clk: qup-i2c14-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio8", "gpio9";
+ function = "qup3_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c15_data_clk: qup-i2c15-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio12", "gpio13";
+ function = "qup3_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c16_data_clk: qup-i2c16-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio16", "gpio17";
+ function = "qup3_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c17_data_clk: qup-i2c17-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio20", "gpio21";
+ function = "qup3_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c19_data_clk: qup-i2c19-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio48", "gpio49";
+ function = "qup4_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c20_data_clk: qup-i2c20-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio28", "gpio29";
+ function = "qup4_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c21_data_clk: qup-i2c21-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio32", "gpio33";
+ function = "qup4_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c22_data_clk: qup-i2c22-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio121", "gpio84";
+ function = "qup4_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c23_data_clk: qup-i2c23-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio161", "gpio162";
+ function = "qup4_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi0_cs: qup-spi0-cs-state {
+ pins = "gpio81";
+ function = "qup1_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi0_data_clk: qup-spi0-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio80", "gpio83", "gpio82";
+ function = "qup1_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi1_cs: qup-spi1-cs-state {
+ pins = "gpio77";
+ function = "qup1_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi1_data_clk: qup-spi1-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio74", "gpio75", "gpio76";
+ function = "qup1_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_cs: qup-spi2-cs-state {
+ pins = "gpio43";
+ function = "qup1_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_data_clk: qup-spi2-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio40", "gpio41", "gpio42";
+ function = "qup1_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi3_cs: qup-spi3-cs-state {
+ pins = "gpio47";
+ function = "qup1_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi3_data_clk: qup-spi3-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio44", "gpio45", "gpio46";
+ function = "qup1_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi4_cs: qup-spi4-cs-state {
+ pins = "gpio39";
+ function = "qup1_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi4_data_clk: qup-spi4-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio36", "gpio37", "gpio38";
+ function = "qup1_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_cs: qup-spi5-cs-state {
+ pins = "gpio55";
+ function = "qup1_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_data_clk: qup-spi5-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio52", "gpio53", "gpio54";
+ function = "qup1_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_cs: qup-spi6-cs-state {
+ pins = "gpio59";
+ function = "qup1_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_data_clk: qup-spi6-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio56", "gpio57", "gpio58";
+ function = "qup1_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi8_cs: qup-spi8-cs-state {
+ pins = "gpio3";
+ function = "qup2_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi8_data_clk: qup-spi8-data-clk-state {
+ /* MISO, MOSI, CLK */pins = "gpio0", "gpio1", "gpio2";
+ function = "qup2_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi9_cs: qup-spi9-cs-state {
+ pins = "gpio7";
+ function = "qup2_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi9_data_clk: qup-spi9-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio4", "gpio5", "gpio6";
+ function = "qup2_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi10_cs: qup-spi10-cs-state {
+ pins = "gpio120";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi10_data_clk: qup-spi10-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio117", "gpio118", "gpio119";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi11_cs: qup-spi11-cs-state {
+ pins = "gpio125";
+ function = "qup2_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi11_data_clk: qup-spi11-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio122", "gpio123", "gpio124";
+ function = "qup2_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi14_cs: qup-spi14-cs-state {
+ pins = "gpio11";
+ function = "qup3_se1";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ qup_spi14_data_clk: qup-spi14-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio8", "gpio9", "gpio10";
+ function = "qup3_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi15_cs: qup-spi15-cs-state {
+ pins = "gpio15";
+ function = "qup3_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi15_data_clk: qup-spi15-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio12", "gpio13", "gpio14";
+ function = "qup3_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi16_cs: qup-spi16-cs-state {
+ pins = "gpio19";
+ function = "qup3_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi16_data_clk: qup-spi16-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio16", "gpio17", "gpio18";
+ function = "qup3_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi17_cs: qup-spi17-cs-state {
+ pins = "gpio23";
+ function = "qup3_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi17_data_clk: qup-spi17-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio20", "gpio21", "gpio22";
+ function = "qup3_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi19_cs: qup-spi19-cs-state {
+ pins = "gpio51";
+ function = "qup4_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi19_data_clk: qup-spi19-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio48", "gpio49", "gpio50";
+ function = "qup4_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi20_cs: qup-spi20-cs-state {
+ pins = "gpio31";
+ function = "qup4_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi20_data_clk: qup-spi20-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio28", "gpio29", "gpio30";
+ function = "qup4_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi21_cs: qup-spi21-cs-state {
+ pins = "gpio35";
+ function = "qup4_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi21_data_clk: qup-spi21-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio32", "gpio33", "gpio34";
+ function = "qup4_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
qup_uart7_default: qup-uart7-state {
/* TX, RX */
pins = "gpio62", "gpio63";
@@ -1674,6 +3750,22 @@ qup_uart7_default: qup-uart7-state {
bias-disable;
};
+ qup_uart18_default: qup-uart18-default-state {
+ /* TX, RX */
+ pins = "gpio26", "gpio27";
+ function = "qup3_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart18_cts_rts: qup-uart18-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio24", "gpio25";
+ function = "qup3_se5";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
sdc2_default: sdc2-default-state {
clk-pins {
pins = "sdc2_clk";
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* Re: [PATCH 13/20] arm64: dts: qcom: kaanapali: Add QUPv3 configuration for serial engines
2025-09-25 0:17 ` [PATCH 13/20] arm64: dts: qcom: kaanapali: Add QUPv3 configuration for serial engines Jingyi Wang
@ 2025-09-25 12:28 ` Konrad Dybcio
2025-09-25 13:19 ` Krzysztof Kozlowski
` (2 more replies)
0 siblings, 3 replies; 135+ messages in thread
From: Konrad Dybcio @ 2025-09-25 12:28 UTC (permalink / raw)
To: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jyothi Kumar Seerapu
On 9/25/25 2:17 AM, Jingyi Wang wrote:
> From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>
> Add device tree support for QUPv3 serial engine protocols on Kaanapali.
> Kaanapali has 24 QUP serial engines across 4 QUP wrappers, each with
> support of GPI DMA engines, and it also includes 5 I2C hubs.
>
> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
> Co-developed-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
[...]
> + gpi_dma2: dma-controller@800000 {
> + compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma";
> + reg = <0x0 0x00800000 0x0 0x60000>;
> +
> + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>;
odd indentation (on almost all gpi_dma instances)
[...]
> - remoteproc_soccp: remoteproc-soccp@d00000 {
> - compatible = "qcom,kaanapali-soccp-pas";
> - reg = <0x0 0x00d00000 0x0 0x200000>;
> + i2c22: i2c@1a8c000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0x0 0x01a8c000 0x0 0x4000>;
>
> - interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
> - <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> - <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> - <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> - <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
> - <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>,
> - <&soccp_smp2p_in 10 IRQ_TYPE_EDGE_RISING>;
> - interrupt-names = "wdog",
> - "fatal",
> - "ready",
> - "handover",
> - "stop-ack",
> - "pong",
> - "wake-ack";
Please try to use git format-patch --patience
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 13/20] arm64: dts: qcom: kaanapali: Add QUPv3 configuration for serial engines
2025-09-25 12:28 ` Konrad Dybcio
@ 2025-09-25 13:19 ` Krzysztof Kozlowski
2025-09-29 3:05 ` Jingyi Wang
2025-09-29 5:42 ` Jingyi Wang
2025-09-29 6:41 ` Aiqun(Maria) Yu
2 siblings, 1 reply; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-25 13:19 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Jyothi Kumar Seerapu
On Thu, 25 Sept 2025 at 21:28, Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 9/25/25 2:17 AM, Jingyi Wang wrote:
> > From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
> >
> > Add device tree support for QUPv3 serial engine protocols on Kaanapali.
> > Kaanapali has 24 QUP serial engines across 4 QUP wrappers, each with
> > support of GPI DMA engines, and it also includes 5 I2C hubs.
> >
> > Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
> > Co-developed-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> > Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> > ---
>
> [...]
>
> > + gpi_dma2: dma-controller@800000 {
> > + compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma";
> > + reg = <0x0 0x00800000 0x0 0x60000>;
> > +
> > + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>;
>
> odd indentation (on almost all gpi_dma instances)
>
> [...]
>
> > - remoteproc_soccp: remoteproc-soccp@d00000 {
> > - compatible = "qcom,kaanapali-soccp-pas";
> > - reg = <0x0 0x00d00000 0x0 0x200000>;
> > + i2c22: i2c@1a8c000 {
> > + compatible = "qcom,geni-i2c";
> > + reg = <0x0 0x01a8c000 0x0 0x4000>;
> >
> > - interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
> > - <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> > - <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> > - <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> > - <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
> > - <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>,
> > - <&soccp_smp2p_in 10 IRQ_TYPE_EDGE_RISING>;
> > - interrupt-names = "wdog",
> > - "fatal",
> > - "ready",
> > - "handover",
> > - "stop-ack",
> > - "pong",
> > - "wake-ack";
>
> Please try to use git format-patch --patience
Well, maybe it worked help, but I claim the author did not review
their work before sending. If you remove lines you added, you clearly
wrote buggy patches without any sense of proper logical split. It's
not gits fault. It's author's fault.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 13/20] arm64: dts: qcom: kaanapali: Add QUPv3 configuration for serial engines
2025-09-25 13:19 ` Krzysztof Kozlowski
@ 2025-09-29 3:05 ` Jingyi Wang
0 siblings, 0 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-09-29 3:05 UTC (permalink / raw)
To: Krzysztof Kozlowski, Konrad Dybcio
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jyothi Kumar Seerapu
On 9/25/2025 9:19 PM, Krzysztof Kozlowski wrote:
> Well, maybe it worked help, but I claim the author did not review
> their work before sending. If you remove lines you added, you clearly
> wrote buggy patches without any sense of proper logical split. It's
> not gits fault. It's author's fault.
>
> Best regards,
> Krzysztof
This patch didn't remove lines added, it is because uart was added in the patch2,
adding other nodes for qup3 which match the same lines and cause deletion here.
Thanks,
Jingyi
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 13/20] arm64: dts: qcom: kaanapali: Add QUPv3 configuration for serial engines
2025-09-25 12:28 ` Konrad Dybcio
2025-09-25 13:19 ` Krzysztof Kozlowski
@ 2025-09-29 5:42 ` Jingyi Wang
2025-09-29 6:41 ` Aiqun(Maria) Yu
2 siblings, 0 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-09-29 5:42 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jyothi Kumar Seerapu
On 9/25/2025 8:28 PM, Konrad Dybcio wrote:
> On 9/25/25 2:17 AM, Jingyi Wang wrote:
>> From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>>
>> Add device tree support for QUPv3 serial engine protocols on Kaanapali.
>> Kaanapali has 24 QUP serial engines across 4 QUP wrappers, each with
>> support of GPI DMA engines, and it also includes 5 I2C hubs.
>>
>> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>> Co-developed-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>
> [...]
>
>> + gpi_dma2: dma-controller@800000 {
>> + compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma";
>> + reg = <0x0 0x00800000 0x0 0x60000>;
>> +
>> + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>;
>
> odd indentation (on almost all gpi_dma instances)
>
> [...]
>
will fix
Thanks,
Jingyi
>> - remoteproc_soccp: remoteproc-soccp@d00000 {
>> - compatible = "qcom,kaanapali-soccp-pas";
>> - reg = <0x0 0x00d00000 0x0 0x200000>;
>> + i2c22: i2c@1a8c000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0x0 0x01a8c000 0x0 0x4000>;
>>
>> - interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
>> - <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
>> - <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
>> - <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
>> - <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
>> - <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>,
>> - <&soccp_smp2p_in 10 IRQ_TYPE_EDGE_RISING>;
>> - interrupt-names = "wdog",
>> - "fatal",
>> - "ready",
>> - "handover",
>> - "stop-ack",
>> - "pong",
>> - "wake-ack";
>
> Please try to use git format-patch --patience
>
> Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 13/20] arm64: dts: qcom: kaanapali: Add QUPv3 configuration for serial engines
2025-09-25 12:28 ` Konrad Dybcio
2025-09-25 13:19 ` Krzysztof Kozlowski
2025-09-29 5:42 ` Jingyi Wang
@ 2025-09-29 6:41 ` Aiqun(Maria) Yu
2025-09-29 13:11 ` Konstantin Ryabitsev
2 siblings, 1 reply; 135+ messages in thread
From: Aiqun(Maria) Yu @ 2025-09-29 6:41 UTC (permalink / raw)
To: Konrad Dybcio, Jingyi Wang, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, tingwei.zhang,
trilok.soni, yijie.yang, Jyothi Kumar Seerapu
On 9/25/2025 8:28 PM, Konrad Dybcio wrote:
> On 9/25/25 2:17 AM, Jingyi Wang wrote:
>> From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>>
>> Add device tree support for QUPv3 serial engine protocols on Kaanapali.
>> Kaanapali has 24 QUP serial engines across 4 QUP wrappers, each with
>> support of GPI DMA engines, and it also includes 5 I2C hubs.
>>
>> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>> Co-developed-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>
> [...]
>
>> + gpi_dma2: dma-controller@800000 {
>> + compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma";
>> + reg = <0x0 0x00800000 0x0 0x60000>;
>> +
>> + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>;
>
> odd indentation (on almost all gpi_dma instances)
>
> [...]
>
>> - remoteproc_soccp: remoteproc-soccp@d00000 {
>> - compatible = "qcom,kaanapali-soccp-pas";
>> - reg = <0x0 0x00d00000 0x0 0x200000>;
>> + i2c22: i2c@1a8c000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0x0 0x01a8c000 0x0 0x4000>;
>>
>> - interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
>> - <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
>> - <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
>> - <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
>> - <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
>> - <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>,
>> - <&soccp_smp2p_in 10 IRQ_TYPE_EDGE_RISING>;
>> - interrupt-names = "wdog",
>> - "fatal",
>> - "ready",
>> - "handover",
>> - "stop-ack",
>> - "pong",
>> - "wake-ack";
>
> Please try to use git format-patch --patience
We’ve tried using git format-patch --patience, and it did help avoid the
deletion lines issue. However, when we send out patches using the B4
tool, the formatting still defaults to the standard behavior.
The challenge now is: how can we integrate the functionality of git
format-patch --patience into the B4 workflow?
Any ideas?>
> Konrad
--
Thx and BRs,
Aiqun(Maria) Yu
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 13/20] arm64: dts: qcom: kaanapali: Add QUPv3 configuration for serial engines
2025-09-29 6:41 ` Aiqun(Maria) Yu
@ 2025-09-29 13:11 ` Konstantin Ryabitsev
2025-09-30 2:14 ` Aiqun(Maria) Yu
0 siblings, 1 reply; 135+ messages in thread
From: Konstantin Ryabitsev @ 2025-09-29 13:11 UTC (permalink / raw)
To: Aiqun(Maria) Yu
Cc: Konrad Dybcio, Jingyi Wang, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel, tingwei.zhang, trilok.soni, yijie.yang,
Jyothi Kumar Seerapu
On Mon, Sep 29, 2025 at 02:41:27PM +0800, Aiqun(Maria) Yu wrote:
> We’ve tried using git format-patch --patience, and it did help avoid the
> deletion lines issue. However, when we send out patches using the B4
> tool, the formatting still defaults to the standard behavior.
> The challenge now is: how can we integrate the functionality of git
> format-patch --patience into the B4 workflow?
> Any ideas?>
You can set this in your .git/config:
[diff]
algorithm = patience
-K
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 13/20] arm64: dts: qcom: kaanapali: Add QUPv3 configuration for serial engines
2025-09-29 13:11 ` Konstantin Ryabitsev
@ 2025-09-30 2:14 ` Aiqun(Maria) Yu
0 siblings, 0 replies; 135+ messages in thread
From: Aiqun(Maria) Yu @ 2025-09-30 2:14 UTC (permalink / raw)
To: Konstantin Ryabitsev
Cc: Konrad Dybcio, Jingyi Wang, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel, tingwei.zhang, trilok.soni, yijie.yang,
Jyothi Kumar Seerapu
On 9/29/2025 9:11 PM, Konstantin Ryabitsev wrote:
> On Mon, Sep 29, 2025 at 02:41:27PM +0800, Aiqun(Maria) Yu wrote:
>> We’ve tried using git format-patch --patience, and it did help avoid the
>> deletion lines issue. However, when we send out patches using the B4
>> tool, the formatting still defaults to the standard behavior.
>> The challenge now is: how can we integrate the functionality of git
>> format-patch --patience into the B4 workflow?
>> Any ideas?>
>
> You can set this in your .git/config:
>
> [diff]
> algorithm = patience
>
Nice help, Thank you Konstantin!> -K
--
Thx and BRs,
Aiqun(Maria) Yu
^ permalink raw reply [flat|nested] 135+ messages in thread
* [PATCH 14/20] arm64: dts: qcom: kaanapali-mtp: Enable more features
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (12 preceding siblings ...)
2025-09-25 0:17 ` [PATCH 13/20] arm64: dts: qcom: kaanapali: Add QUPv3 configuration for serial engines Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-09-25 2:09 ` Dmitry Baryshkov
2025-09-25 8:03 ` Eugen Hristev
2025-09-25 0:17 ` [PATCH 15/20] arm64: dts: qcom: kaanapali-mtp: Enable modem Jingyi Wang
` (8 subsequent siblings)
22 siblings, 2 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang
Enable more features on Kaanapali MTP boards including PMIC peripherals,
bus, SDHCI, remoteprocs, USB, PCIE, WLAN and Bluetooth.
Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
(added USB), Manish Pandey(added SDHCI), Jishnu Prakash(added PMIC),
Qiang Yu(added PCIE), Yijie Yang(Added WLAN) and Zijun Hu(Added Bluetooth).
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 663 +++++++++++++++++++++++++++++
1 file changed, 663 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
index 9cf3158e2712..2949579481a9 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
@@ -5,9 +5,23 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "kaanapali.dtsi"
+#define PMH0110_D_E0_SID 3
+#define PMH0110_F_E0_SID 5
+#define PMH0110_G_E0_SID 6
+#define PMH0110_I_E0_SID 8
+#define PMH0104_J_E1_SID 9
+
+#include "pmk8850.dtsi"
+#include "pmh0101.dtsi"
+#include "pmh0110.dtsi"
+#include "pmh0104.dtsi"
+
/ {
model = "Qualcomm Technologies, Inc. Kaanapali MTP";
compatible = "qcom,kaanapali-mtp", "qcom,kaanapali";
@@ -15,6 +29,7 @@ / {
aliases {
serial0 = &uart7;
+ serial1 = &uart18;
};
chosen {
@@ -52,6 +67,304 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
clock-div = <2>;
};
};
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&key_vol_up_default>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ thermal-zones {
+ pmh0101-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pmh0101_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmh0104-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pmh0104_j_e1_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmh0110-d-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pmh0110_d_e0_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmh0110-f-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pmh0110_f_e0_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmh0110-g-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pmh0110_g_e0_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmh0110-i-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pmh0110_i_e0_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmd8028-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pmd8028_temp_alarm>;
+
+ trips {
+ pmd8028_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pmd8028_trip1: trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmih0108-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pmih0108_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmr735d-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pmr735d_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pm8010-m-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8010_m_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pm8010-n-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8010_n_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+ };
+
+ wcn7850-pmu {
+ compatible = "qcom,wcn7850-pmu";
+
+ pinctrl-0 = <&bt_default>, <&sw_ctrl_default>, <&wlan_en>;
+ pinctrl-names = "default";
+
+ bt-enable-gpios = <&pmh0104_j_e1_gpios 5 GPIO_ACTIVE_HIGH>;
+ wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <&vreg_s2j_0p8>;
+ vddio-supply = <&vreg_l2g_1p8>;
+ vddio1p2-supply = <&vreg_l3g_1p2>;
+ vddaon-supply = <&vreg_s7g_0p9>;
+ vdddig-supply = <&vreg_s1j_0p8>;
+ vddrfa1p2-supply = <&vreg_s7f_1p2>;
+ vddrfa1p8-supply = <&vreg_s8f_1p8>;
+
+ clocks = <&rpmhcc RPMH_RF_CLK1>;
+
+ regulators {
+ vreg_pmu_rfa_cmn: ldo0 {
+ regulator-name = "vreg_pmu_rfa_cmn";
+ };
+
+ vreg_pmu_aon_0p59: ldo1 {
+ regulator-name = "vreg_pmu_aon_0p59";
+ };
+
+ vreg_pmu_wlcx_0p8: ldo2 {
+ regulator-name = "vreg_pmu_wlcx_0p8";
+ };
+
+ vreg_pmu_wlmx_0p85: ldo3 {
+ regulator-name = "vreg_pmu_wlmx_0p85";
+ };
+
+ vreg_pmu_btcmx_0p85: ldo4 {
+ regulator-name = "vreg_pmu_btcmx_0p85";
+ };
+
+ vreg_pmu_rfa_0p8: ldo5 {
+ regulator-name = "vreg_pmu_rfa_0p8";
+ };
+
+ vreg_pmu_rfa_1p2: ldo6 {
+ regulator-name = "vreg_pmu_rfa_1p2";
+ };
+
+ vreg_pmu_rfa_1p8: ldo7 {
+ regulator-name = "vreg_pmu_rfa_1p8";
+ };
+
+ vreg_pmu_pcie_0p9: ldo8 {
+ regulator-name = "vreg_pmu_pcie_0p9";
+ };
+
+ vreg_pmu_pcie_1p8: ldo9 {
+ regulator-name = "vreg_pmu_pcie_1p8";
+ };
+ };
+ };
};
&apps_rsc {
@@ -674,6 +987,304 @@ vreg_l7n_3p3: ldo7 {
};
};
+&pmh0110_d_e0 {
+ status = "okay";
+};
+
+&pmh0110_f_e0 {
+ status = "okay";
+};
+
+&pmh0110_g_e0 {
+ status = "okay";
+};
+
+&pmh0110_i_e0 {
+ status = "okay";
+};
+
+&spmi_bus1 {
+ pmd8028: pmic@4 {
+ compatible = "qcom,pmd8028", "qcom,spmi-pmic";
+ reg = <0x4 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmd8028_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmd8028_gpios: gpio@8800 {
+ compatible = "qcom,pmd8028-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmd8028_gpios 0 0 4>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmih0108: pmic@7 {
+ compatible = "qcom,pmih0108", "qcom,spmi-pmic";
+ reg = <0x7 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmih0108_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmih0108_gpios: gpio@8800 {
+ compatible = "qcom,pmih0108-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmih0108_gpios 0 0 18>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pmih0108_eusb2_repeater: phy@fd00 {
+ compatible = "qcom,pm8550b-eusb2-repeater";
+ reg = <0xfd00>;
+ #phy-cells = <0>;
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+ };
+ };
+
+ pmr735d: pmic@a {
+ compatible = "qcom,pmr735d", "qcom,spmi-pmic";
+ reg = <0xa SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmr735d_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmr735d_gpios: gpio@8800 {
+ compatible = "qcom,pmr735d-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmr735d_gpios 0 0 2>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pm8010_m: pmic@c {
+ compatible = "qcom,pm8010", "qcom,spmi-pmic";
+ reg = <0xc SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8010_m_temp_alarm: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+ };
+
+ pm8010_n: pmic@d {
+ compatible = "qcom,pm8010", "qcom,spmi-pmic";
+ reg = <0xd SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8010_n_temp_alarm: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+ };
+};
+
+&pmh0101_flash {
+ status = "okay";
+
+ led-0 {
+ function = LED_FUNCTION_FLASH;
+ function-enumerator = <0>;
+ color = <LED_COLOR_ID_YELLOW>;
+ led-sources = <1>, <4>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <2000000>;
+ flash-max-timeout-us = <1280000>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_FLASH;
+ function-enumerator = <1>;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <2>, <3>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <2000000>;
+ flash-max-timeout-us = <1280000>;
+ };
+};
+
+&pmh0101_pwm {
+ status = "okay";
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_STATUS;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@3 {
+ reg = <3>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+};
+
+&tlmm {
+ wlan_en: wlan-en-state {
+ pins = "gpio16";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+
+ sw_ctrl_default: sw-ctrl-default-state {
+ pins = "gpio18";
+ function = "gpio";
+ bias-pull-down;
+ };
+
+ key_vol_up_default: key-vol-up-default-state {
+ pins = "gpio101";
+ function = "gpio";
+ output-disable;
+ bias-pull-up;
+ };
+
+ pcie0_default_state: pcie0-default-state {
+ clkreq-n-pins {
+ pins = "gpio103";
+ function = "pcie0_clk_req_n";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio102";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake-n-pins {
+ pins = "gpio104";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+};
+
+&pcie0 {
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l3i_0p8>;
+ vdda-pll-supply = <&vreg_l1d_1p2>;
+
+ status = "okay";
+};
+
+&pcieport0 {
+ wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
+
+ wifi@0 {
+ compatible = "pci17cb,1107";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+ vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+ };
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/kaanapali/adsp.mbn",
+ "qcom/kaanapali/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/kaanapali/cdsp.mbn",
+ "qcom/kaanapali/cdsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_soccp {
+ firmware-name = "qcom/kaanapali/soccp.mbn",
+ "qcom/kaanapali/soccp_dtb.mbn";
+};
+
+&sdhc_2 {
+ cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vreg_l9b_2p9>;
+ vqmmc-supply = <&vreg_l8b_1p8>;
+
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+
+ pinctrl-0 = <&sdc2_default>;
+ pinctrl-1 = <&sdc2_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+};
+
&tlmm {
gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */
<74 1>, /* eSE */
@@ -685,6 +1296,36 @@ &uart7 {
status = "okay";
};
+&pmh0104_j_e1_gpios {
+ bt_default: bt-default-state {
+ pins = "gpio5";
+ function = "normal";
+ input-disable;
+ output-enable;
+ output-low;
+ bias-disable;
+ power-source = <1>;
+ };
+};
+
+&uart18 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn7850-bt";
+
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+
+ max-speed = <3200000>;
+ };
+};
+
&ufs_mem_hc {
reset-gpios = <&tlmm 217 GPIO_ACTIVE_LOW>;
@@ -702,3 +1343,25 @@ &ufs_mem_phy {
status = "okay";
};
+
+&usb_1 {
+ dr_mode = "peripheral";
+
+ status = "okay";
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l4f_0p8>;
+ vdda12-supply = <&vreg_l1d_1p2>;
+
+ phys = <&pmih0108_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ vdda-phy-supply = <&vreg_l1d_1p2>;
+ vdda-pll-supply = <&vreg_l4f_0p8>;
+
+ status = "okay";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* Re: [PATCH 14/20] arm64: dts: qcom: kaanapali-mtp: Enable more features
2025-09-25 0:17 ` [PATCH 14/20] arm64: dts: qcom: kaanapali-mtp: Enable more features Jingyi Wang
@ 2025-09-25 2:09 ` Dmitry Baryshkov
2025-09-25 9:48 ` Konrad Dybcio
` (2 more replies)
2025-09-25 8:03 ` Eugen Hristev
1 sibling, 3 replies; 135+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 2:09 UTC (permalink / raw)
To: Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On Wed, Sep 24, 2025 at 05:17:31PM -0700, Jingyi Wang wrote:
> Enable more features on Kaanapali MTP boards including PMIC peripherals,
> bus, SDHCI, remoteprocs, USB, PCIE, WLAN and Bluetooth.
>
> Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
> (added USB), Manish Pandey(added SDHCI), Jishnu Prakash(added PMIC),
> Qiang Yu(added PCIE), Yijie Yang(Added WLAN) and Zijun Hu(Added Bluetooth).
>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 663 +++++++++++++++++++++++++++++
> 1 file changed, 663 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> index 9cf3158e2712..2949579481a9 100644
> --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> @@ -5,9 +5,23 @@
>
> /dts-v1/;
>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/linux-event-codes.h>
> +#include <dt-bindings/leds/common.h>
> #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> #include "kaanapali.dtsi"
>
> +#define PMH0110_D_E0_SID 3
> +#define PMH0110_F_E0_SID 5
> +#define PMH0110_G_E0_SID 6
> +#define PMH0110_I_E0_SID 8
> +#define PMH0104_J_E1_SID 9
> +
> +#include "pmk8850.dtsi"
> +#include "pmh0101.dtsi"
> +#include "pmh0110.dtsi"
> +#include "pmh0104.dtsi"
> +
> / {
> model = "Qualcomm Technologies, Inc. Kaanapali MTP";
> compatible = "qcom,kaanapali-mtp", "qcom,kaanapali";
> @@ -15,6 +29,7 @@ / {
>
> aliases {
> serial0 = &uart7;
> + serial1 = &uart18;
> };
>
> chosen {
> @@ -52,6 +67,304 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
> clock-div = <2>;
> };
> };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + pinctrl-0 = <&key_vol_up_default>;
> + pinctrl-names = "default";
> +
> + key-volume-up {
> + label = "Volume Up";
> + linux,code = <KEY_VOLUMEUP>;
> + gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
> + debounce-interval = <15>;
> + linux,can-disable;
> + wakeup-source;
> + };
> + };
> +
> + thermal-zones {
> + pmh0101-thermal {
> + polling-delay-passive = <100>;
> +
> + thermal-sensors = <&pmh0101_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pmh0104-thermal {
> + polling-delay-passive = <100>;
> +
> + thermal-sensors = <&pmh0104_j_e1_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pmh0110-d-thermal {
> + polling-delay-passive = <100>;
> +
> + thermal-sensors = <&pmh0110_d_e0_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pmh0110-f-thermal {
> + polling-delay-passive = <100>;
> +
> + thermal-sensors = <&pmh0110_f_e0_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pmh0110-g-thermal {
> + polling-delay-passive = <100>;
> +
> + thermal-sensors = <&pmh0110_g_e0_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pmh0110-i-thermal {
> + polling-delay-passive = <100>;
> +
> + thermal-sensors = <&pmh0110_i_e0_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pmd8028-thermal {
> + polling-delay-passive = <100>;
> + thermal-sensors = <&pmd8028_temp_alarm>;
> +
> + trips {
> + pmd8028_trip0: trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + pmd8028_trip1: trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pmih0108-thermal {
> + polling-delay-passive = <100>;
> + thermal-sensors = <&pmih0108_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pmr735d-thermal {
> + polling-delay-passive = <100>;
> +
> + thermal-sensors = <&pmr735d_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pm8010-m-thermal {
> + polling-delay-passive = <100>;
> +
> + thermal-sensors = <&pm8010_m_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pm8010-n-thermal {
> + polling-delay-passive = <100>;
> +
> + thermal-sensors = <&pm8010_n_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> + };
> +
> + wcn7850-pmu {
> + compatible = "qcom,wcn7850-pmu";
> +
> + pinctrl-0 = <&bt_default>, <&sw_ctrl_default>, <&wlan_en>;
> + pinctrl-names = "default";
> +
> + bt-enable-gpios = <&pmh0104_j_e1_gpios 5 GPIO_ACTIVE_HIGH>;
> + wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
> +
> + vdd-supply = <&vreg_s2j_0p8>;
> + vddio-supply = <&vreg_l2g_1p8>;
> + vddio1p2-supply = <&vreg_l3g_1p2>;
> + vddaon-supply = <&vreg_s7g_0p9>;
> + vdddig-supply = <&vreg_s1j_0p8>;
> + vddrfa1p2-supply = <&vreg_s7f_1p2>;
> + vddrfa1p8-supply = <&vreg_s8f_1p8>;
> +
> + clocks = <&rpmhcc RPMH_RF_CLK1>;
> +
> + regulators {
> + vreg_pmu_rfa_cmn: ldo0 {
> + regulator-name = "vreg_pmu_rfa_cmn";
> + };
> +
> + vreg_pmu_aon_0p59: ldo1 {
> + regulator-name = "vreg_pmu_aon_0p59";
> + };
> +
> + vreg_pmu_wlcx_0p8: ldo2 {
> + regulator-name = "vreg_pmu_wlcx_0p8";
> + };
> +
> + vreg_pmu_wlmx_0p85: ldo3 {
> + regulator-name = "vreg_pmu_wlmx_0p85";
> + };
> +
> + vreg_pmu_btcmx_0p85: ldo4 {
> + regulator-name = "vreg_pmu_btcmx_0p85";
> + };
> +
> + vreg_pmu_rfa_0p8: ldo5 {
> + regulator-name = "vreg_pmu_rfa_0p8";
> + };
> +
> + vreg_pmu_rfa_1p2: ldo6 {
> + regulator-name = "vreg_pmu_rfa_1p2";
> + };
> +
> + vreg_pmu_rfa_1p8: ldo7 {
> + regulator-name = "vreg_pmu_rfa_1p8";
> + };
> +
> + vreg_pmu_pcie_0p9: ldo8 {
> + regulator-name = "vreg_pmu_pcie_0p9";
> + };
> +
> + vreg_pmu_pcie_1p8: ldo9 {
> + regulator-name = "vreg_pmu_pcie_1p8";
> + };
> + };
> + };
> };
>
> &apps_rsc {
> @@ -674,6 +987,304 @@ vreg_l7n_3p3: ldo7 {
> };
> };
>
> +&pmh0110_d_e0 {
> + status = "okay";
> +};
> +
> +&pmh0110_f_e0 {
> + status = "okay";
> +};
> +
> +&pmh0110_g_e0 {
> + status = "okay";
> +};
> +
> +&pmh0110_i_e0 {
> + status = "okay";
> +};
> +
> +&spmi_bus1 {
> + pmd8028: pmic@4 {
> + compatible = "qcom,pmd8028", "qcom,spmi-pmic";
> + reg = <0x4 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pmd8028_temp_alarm: temp-alarm@a00 {
> + compatible = "qcom,spmi-temp-alarm";
> + reg = <0xa00>;
> + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
> + #thermal-sensor-cells = <0>;
> + };
> +
> + pmd8028_gpios: gpio@8800 {
> + compatible = "qcom,pmd8028-gpio", "qcom,spmi-gpio";
> + reg = <0x8800>;
> + gpio-controller;
> + gpio-ranges = <&pmd8028_gpios 0 0 4>;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> + pmih0108: pmic@7 {
> + compatible = "qcom,pmih0108", "qcom,spmi-pmic";
> + reg = <0x7 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pmih0108_temp_alarm: temp-alarm@a00 {
> + compatible = "qcom,spmi-temp-alarm";
> + reg = <0xa00>;
> + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
> + #thermal-sensor-cells = <0>;
> + };
> +
> + pmih0108_gpios: gpio@8800 {
> + compatible = "qcom,pmih0108-gpio", "qcom,spmi-gpio";
> + reg = <0x8800>;
> + gpio-controller;
> + gpio-ranges = <&pmih0108_gpios 0 0 18>;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + pmih0108_eusb2_repeater: phy@fd00 {
> + compatible = "qcom,pm8550b-eusb2-repeater";
> + reg = <0xfd00>;
> + #phy-cells = <0>;
> + vdd18-supply = <&vreg_l15b_1p8>;
> + vdd3-supply = <&vreg_l5b_3p1>;
> + };
> + };
> +
> + pmr735d: pmic@a {
> + compatible = "qcom,pmr735d", "qcom,spmi-pmic";
> + reg = <0xa SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pmr735d_temp_alarm: temp-alarm@a00 {
> + compatible = "qcom,spmi-temp-alarm";
> + reg = <0xa00>;
> + interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
> + #thermal-sensor-cells = <0>;
> + };
> +
> + pmr735d_gpios: gpio@8800 {
> + compatible = "qcom,pmr735d-gpio", "qcom,spmi-gpio";
> + reg = <0x8800>;
> + gpio-controller;
> + gpio-ranges = <&pmr735d_gpios 0 0 2>;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> + pm8010_m: pmic@c {
> + compatible = "qcom,pm8010", "qcom,spmi-pmic";
> + reg = <0xc SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pm8010_m_temp_alarm: temp-alarm@2400 {
> + compatible = "qcom,spmi-temp-alarm";
> + reg = <0x2400>;
> + interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
> + #thermal-sensor-cells = <0>;
> + };
> + };
> +
> + pm8010_n: pmic@d {
> + compatible = "qcom,pm8010", "qcom,spmi-pmic";
> + reg = <0xd SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pm8010_n_temp_alarm: temp-alarm@2400 {
> + compatible = "qcom,spmi-temp-alarm";
> + reg = <0x2400>;
> + interrupts = <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
> + #thermal-sensor-cells = <0>;
> + };
> + };
> +};
> +
> +&pmh0101_flash {
spmi > pmh0101_flash
> + status = "okay";
> +
> + led-0 {
> + function = LED_FUNCTION_FLASH;
> + function-enumerator = <0>;
> + color = <LED_COLOR_ID_YELLOW>;
> + led-sources = <1>, <4>;
> + led-max-microamp = <500000>;
> + flash-max-microamp = <2000000>;
> + flash-max-timeout-us = <1280000>;
> + };
> +
> + led-1 {
> + function = LED_FUNCTION_FLASH;
> + function-enumerator = <1>;
> + color = <LED_COLOR_ID_WHITE>;
> + led-sources = <2>, <3>;
> + led-max-microamp = <500000>;
> + flash-max-microamp = <2000000>;
> + flash-max-timeout-us = <1280000>;
> + };
> +};
> +
> +&pmh0101_pwm {
> + status = "okay";
> +
> + multi-led {
> + color = <LED_COLOR_ID_RGB>;
> + function = LED_FUNCTION_STATUS;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + led@1 {
> + reg = <1>;
> + color = <LED_COLOR_ID_RED>;
> + };
> +
> + led@2 {
> + reg = <2>;
> + color = <LED_COLOR_ID_GREEN>;
> + };
> +
> + led@3 {
> + reg = <3>;
> + color = <LED_COLOR_ID_BLUE>;
> + };
> + };
> +};
> +
> +&tlmm {
> + wlan_en: wlan-en-state {
> + pins = "gpio16";
> + function = "gpio";
> + drive-strength = <8>;
> + bias-pull-down;
> + };
Why are the TLMM pin entries sorted?
> +
> + sw_ctrl_default: sw-ctrl-default-state {
> + pins = "gpio18";
> + function = "gpio";
> + bias-pull-down;
> + };
> +
> + key_vol_up_default: key-vol-up-default-state {
> + pins = "gpio101";
> + function = "gpio";
> + output-disable;
> + bias-pull-up;
> + };
> +
> + pcie0_default_state: pcie0-default-state {
> + clkreq-n-pins {
> + pins = "gpio103";
> + function = "pcie0_clk_req_n";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + perst-n-pins {
> + pins = "gpio102";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + wake-n-pins {
> + pins = "gpio104";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +};
> +
> +&pcie0 {
This is also in the wrong place. Please keep the nodes sorted.
> + pinctrl-0 = <&pcie0_default_state>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> +};
> +
> +&pcie0_phy {
> + vdda-phy-supply = <&vreg_l3i_0p8>;
> + vdda-pll-supply = <&vreg_l1d_1p2>;
> +
> + status = "okay";
> +};
> +
> @@ -702,3 +1343,25 @@ &ufs_mem_phy {
>
> status = "okay";
> };
> +
> +&usb_1 {
> + dr_mode = "peripheral";
Is it really peripheral-only?
> +
> + status = "okay";
> +};
> +
> +&usb_1_hsphy {
> + vdd-supply = <&vreg_l4f_0p8>;
> + vdda12-supply = <&vreg_l1d_1p2>;
> +
> + phys = <&pmih0108_eusb2_repeater>;
> +
> + status = "okay";
> +};
> +
> +&usb_dp_qmpphy {
> + vdda-phy-supply = <&vreg_l1d_1p2>;
> + vdda-pll-supply = <&vreg_l4f_0p8>;
> +
> + status = "okay";
> +};
>
> --
> 2.25.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 14/20] arm64: dts: qcom: kaanapali-mtp: Enable more features
2025-09-25 2:09 ` Dmitry Baryshkov
@ 2025-09-25 9:48 ` Konrad Dybcio
2025-09-26 9:11 ` Ronak Raheja
2025-09-29 3:24 ` Jingyi Wang
2 siblings, 0 replies; 135+ messages in thread
From: Konrad Dybcio @ 2025-09-25 9:48 UTC (permalink / raw)
To: Dmitry Baryshkov, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On 9/25/25 4:09 AM, Dmitry Baryshkov wrote:
> On Wed, Sep 24, 2025 at 05:17:31PM -0700, Jingyi Wang wrote:
>> Enable more features on Kaanapali MTP boards including PMIC peripherals,
>> bus, SDHCI, remoteprocs, USB, PCIE, WLAN and Bluetooth.
>>
>> Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
>> (added USB), Manish Pandey(added SDHCI), Jishnu Prakash(added PMIC),
>> Qiang Yu(added PCIE), Yijie Yang(Added WLAN) and Zijun Hu(Added Bluetooth).
>>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
[...]
>> +&tlmm {
>> + wlan_en: wlan-en-state {
>> + pins = "gpio16";
>> + function = "gpio";
>> + drive-strength = <8>;
>> + bias-pull-down;
>> + };
>
> Why are the TLMM pin entries sorted?
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-nodes
"""
For a few node types, they can be ordered by the main property, e.g.
pin configuration states ordered by value of “pins” property.
"""
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 14/20] arm64: dts: qcom: kaanapali-mtp: Enable more features
2025-09-25 2:09 ` Dmitry Baryshkov
2025-09-25 9:48 ` Konrad Dybcio
@ 2025-09-26 9:11 ` Ronak Raheja
2025-09-26 11:44 ` Konrad Dybcio
2025-09-26 13:46 ` Dmitry Baryshkov
2025-09-29 3:24 ` Jingyi Wang
2 siblings, 2 replies; 135+ messages in thread
From: Ronak Raheja @ 2025-09-26 9:11 UTC (permalink / raw)
To: Dmitry Baryshkov, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On 9/24/2025 7:09 PM, Dmitry Baryshkov wrote:
> On Wed, Sep 24, 2025 at 05:17:31PM -0700, Jingyi Wang wrote:
>> Enable more features on Kaanapali MTP boards including PMIC peripherals,
>> bus, SDHCI, remoteprocs, USB, PCIE, WLAN and Bluetooth.
>>
>> Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
>> (added USB), Manish Pandey(added SDHCI), Jishnu Prakash(added PMIC),
>> Qiang Yu(added PCIE), Yijie Yang(Added WLAN) and Zijun Hu(Added Bluetooth).
>>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
[...]
>> +&usb_1 {
>> + dr_mode = "peripheral";
>
> Is it really peripheral-only?
>
For this initial submission, we haven't yet defined the USB role detection
infrastructure, so it didn't make sense to include dual-role now. The
controller supports it, but without the connector bindings and role switch
implementation, it would be non-functional.
Thanks,
Ronak
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 14/20] arm64: dts: qcom: kaanapali-mtp: Enable more features
2025-09-26 9:11 ` Ronak Raheja
@ 2025-09-26 11:44 ` Konrad Dybcio
2025-09-26 13:46 ` Dmitry Baryshkov
1 sibling, 0 replies; 135+ messages in thread
From: Konrad Dybcio @ 2025-09-26 11:44 UTC (permalink / raw)
To: Ronak Raheja, Dmitry Baryshkov, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On 9/26/25 11:11 AM, Ronak Raheja wrote:
>
> On 9/24/2025 7:09 PM, Dmitry Baryshkov wrote:
>> On Wed, Sep 24, 2025 at 05:17:31PM -0700, Jingyi Wang wrote:
>>> Enable more features on Kaanapali MTP boards including PMIC peripherals,
>>> bus, SDHCI, remoteprocs, USB, PCIE, WLAN and Bluetooth.
>>>
>>> Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
>>> (added USB), Manish Pandey(added SDHCI), Jishnu Prakash(added PMIC),
>>> Qiang Yu(added PCIE), Yijie Yang(Added WLAN) and Zijun Hu(Added Bluetooth).
>>>
>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>>> ---
>
> [...]
>
>>> +&usb_1 {
>>> + dr_mode = "peripheral";
>>
>> Is it really peripheral-only?
>>
>
> For this initial submission, we haven't yet defined the USB role detection
> infrastructure, so it didn't make sense to include dual-role now. The
> controller supports it, but without the connector bindings and role switch
> implementation, it would be non-functional.
I see an internal patch adding pmic-glink.. and I see no reason this
wasn't brought together with this version
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 14/20] arm64: dts: qcom: kaanapali-mtp: Enable more features
2025-09-26 9:11 ` Ronak Raheja
2025-09-26 11:44 ` Konrad Dybcio
@ 2025-09-26 13:46 ` Dmitry Baryshkov
1 sibling, 0 replies; 135+ messages in thread
From: Dmitry Baryshkov @ 2025-09-26 13:46 UTC (permalink / raw)
To: Ronak Raheja
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang
On Fri, Sep 26, 2025 at 02:11:16AM -0700, Ronak Raheja wrote:
>
> On 9/24/2025 7:09 PM, Dmitry Baryshkov wrote:
> > On Wed, Sep 24, 2025 at 05:17:31PM -0700, Jingyi Wang wrote:
> >> Enable more features on Kaanapali MTP boards including PMIC peripherals,
> >> bus, SDHCI, remoteprocs, USB, PCIE, WLAN and Bluetooth.
> >>
> >> Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
> >> (added USB), Manish Pandey(added SDHCI), Jishnu Prakash(added PMIC),
> >> Qiang Yu(added PCIE), Yijie Yang(Added WLAN) and Zijun Hu(Added Bluetooth).
> >>
> >> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> >> ---
>
> [...]
>
> >> +&usb_1 {
> >> + dr_mode = "peripheral";
> >
> > Is it really peripheral-only?
> >
>
> For this initial submission, we haven't yet defined the USB role detection
> infrastructure, so it didn't make sense to include dual-role now. The
> controller supports it, but without the connector bindings and role switch
> implementation, it would be non-functional.
It would be nice to explain this in the commit message.
>
> Thanks,
> Ronak
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 14/20] arm64: dts: qcom: kaanapali-mtp: Enable more features
2025-09-25 2:09 ` Dmitry Baryshkov
2025-09-25 9:48 ` Konrad Dybcio
2025-09-26 9:11 ` Ronak Raheja
@ 2025-09-29 3:24 ` Jingyi Wang
2 siblings, 0 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-09-29 3:24 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On 9/25/2025 10:09 AM, Dmitry Baryshkov wrote:
> On Wed, Sep 24, 2025 at 05:17:31PM -0700, Jingyi Wang wrote:
>> Enable more features on Kaanapali MTP boards including PMIC peripherals,
>> bus, SDHCI, remoteprocs, USB, PCIE, WLAN and Bluetooth.
>>
>> Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
>> (added USB), Manish Pandey(added SDHCI), Jishnu Prakash(added PMIC),
>> Qiang Yu(added PCIE), Yijie Yang(Added WLAN) and Zijun Hu(Added Bluetooth).
>>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 663 +++++++++++++++++++++++++++++
>> 1 file changed, 663 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>> index 9cf3158e2712..2949579481a9 100644
>> --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>> +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>> @@ -5,9 +5,23 @@
>>
>> /dts-v1/;
>>
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/input/linux-event-codes.h>
>> +#include <dt-bindings/leds/common.h>
>> #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>> #include "kaanapali.dtsi"
>>
>> +#define PMH0110_D_E0_SID 3
>> +#define PMH0110_F_E0_SID 5
>> +#define PMH0110_G_E0_SID 6
>> +#define PMH0110_I_E0_SID 8
>> +#define PMH0104_J_E1_SID 9
>> +
>> +#include "pmk8850.dtsi"
>> +#include "pmh0101.dtsi"
>> +#include "pmh0110.dtsi"
>> +#include "pmh0104.dtsi"
>> +
>> / {
>> model = "Qualcomm Technologies, Inc. Kaanapali MTP";
>> compatible = "qcom,kaanapali-mtp", "qcom,kaanapali";
>> @@ -15,6 +29,7 @@ / {
>>
>> aliases {
>> serial0 = &uart7;
>> + serial1 = &uart18;
>> };
>>
>> chosen {
>> @@ -52,6 +67,304 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
>> clock-div = <2>;
>> };
>> };
>> +
>> + gpio-keys {
>> + compatible = "gpio-keys";
>> +
>> + pinctrl-0 = <&key_vol_up_default>;
>> + pinctrl-names = "default";
>> +
>> + key-volume-up {
>> + label = "Volume Up";
>> + linux,code = <KEY_VOLUMEUP>;
>> + gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
>> + debounce-interval = <15>;
>> + linux,can-disable;
>> + wakeup-source;
>> + };
>> + };
>> +
>> + thermal-zones {
>> + pmh0101-thermal {
>> + polling-delay-passive = <100>;
>> +
>> + thermal-sensors = <&pmh0101_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "hot";
>> + };
>> + };
>> + };
>> +
>> + pmh0104-thermal {
>> + polling-delay-passive = <100>;
>> +
>> + thermal-sensors = <&pmh0104_j_e1_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "hot";
>> + };
>> + };
>> + };
>> +
>> + pmh0110-d-thermal {
>> + polling-delay-passive = <100>;
>> +
>> + thermal-sensors = <&pmh0110_d_e0_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "hot";
>> + };
>> + };
>> + };
>> +
>> + pmh0110-f-thermal {
>> + polling-delay-passive = <100>;
>> +
>> + thermal-sensors = <&pmh0110_f_e0_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "hot";
>> + };
>> + };
>> + };
>> +
>> + pmh0110-g-thermal {
>> + polling-delay-passive = <100>;
>> +
>> + thermal-sensors = <&pmh0110_g_e0_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "hot";
>> + };
>> + };
>> + };
>> +
>> + pmh0110-i-thermal {
>> + polling-delay-passive = <100>;
>> +
>> + thermal-sensors = <&pmh0110_i_e0_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "hot";
>> + };
>> + };
>> + };
>> +
>> + pmd8028-thermal {
>> + polling-delay-passive = <100>;
>> + thermal-sensors = <&pmd8028_temp_alarm>;
>> +
>> + trips {
>> + pmd8028_trip0: trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + pmd8028_trip1: trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "hot";
>> + };
>> + };
>> + };
>> +
>> + pmih0108-thermal {
>> + polling-delay-passive = <100>;
>> + thermal-sensors = <&pmih0108_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "hot";
>> + };
>> + };
>> + };
>> +
>> + pmr735d-thermal {
>> + polling-delay-passive = <100>;
>> +
>> + thermal-sensors = <&pmr735d_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "hot";
>> + };
>> + };
>> + };
>> +
>> + pm8010-m-thermal {
>> + polling-delay-passive = <100>;
>> +
>> + thermal-sensors = <&pm8010_m_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "hot";
>> + };
>> + };
>> + };
>> +
>> + pm8010-n-thermal {
>> + polling-delay-passive = <100>;
>> +
>> + thermal-sensors = <&pm8010_n_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "hot";
>> + };
>> + };
>> + };
>> + };
>> +
>> + wcn7850-pmu {
>> + compatible = "qcom,wcn7850-pmu";
>> +
>> + pinctrl-0 = <&bt_default>, <&sw_ctrl_default>, <&wlan_en>;
>> + pinctrl-names = "default";
>> +
>> + bt-enable-gpios = <&pmh0104_j_e1_gpios 5 GPIO_ACTIVE_HIGH>;
>> + wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
>> +
>> + vdd-supply = <&vreg_s2j_0p8>;
>> + vddio-supply = <&vreg_l2g_1p8>;
>> + vddio1p2-supply = <&vreg_l3g_1p2>;
>> + vddaon-supply = <&vreg_s7g_0p9>;
>> + vdddig-supply = <&vreg_s1j_0p8>;
>> + vddrfa1p2-supply = <&vreg_s7f_1p2>;
>> + vddrfa1p8-supply = <&vreg_s8f_1p8>;
>> +
>> + clocks = <&rpmhcc RPMH_RF_CLK1>;
>> +
>> + regulators {
>> + vreg_pmu_rfa_cmn: ldo0 {
>> + regulator-name = "vreg_pmu_rfa_cmn";
>> + };
>> +
>> + vreg_pmu_aon_0p59: ldo1 {
>> + regulator-name = "vreg_pmu_aon_0p59";
>> + };
>> +
>> + vreg_pmu_wlcx_0p8: ldo2 {
>> + regulator-name = "vreg_pmu_wlcx_0p8";
>> + };
>> +
>> + vreg_pmu_wlmx_0p85: ldo3 {
>> + regulator-name = "vreg_pmu_wlmx_0p85";
>> + };
>> +
>> + vreg_pmu_btcmx_0p85: ldo4 {
>> + regulator-name = "vreg_pmu_btcmx_0p85";
>> + };
>> +
>> + vreg_pmu_rfa_0p8: ldo5 {
>> + regulator-name = "vreg_pmu_rfa_0p8";
>> + };
>> +
>> + vreg_pmu_rfa_1p2: ldo6 {
>> + regulator-name = "vreg_pmu_rfa_1p2";
>> + };
>> +
>> + vreg_pmu_rfa_1p8: ldo7 {
>> + regulator-name = "vreg_pmu_rfa_1p8";
>> + };
>> +
>> + vreg_pmu_pcie_0p9: ldo8 {
>> + regulator-name = "vreg_pmu_pcie_0p9";
>> + };
>> +
>> + vreg_pmu_pcie_1p8: ldo9 {
>> + regulator-name = "vreg_pmu_pcie_1p8";
>> + };
>> + };
>> + };
>> };
>>
>> &apps_rsc {
>> @@ -674,6 +987,304 @@ vreg_l7n_3p3: ldo7 {
>> };
>> };
>>
>> +&pmh0110_d_e0 {
>> + status = "okay";
>> +};
>> +
>> +&pmh0110_f_e0 {
>> + status = "okay";
>> +};
>> +
>> +&pmh0110_g_e0 {
>> + status = "okay";
>> +};
>> +
>> +&pmh0110_i_e0 {
>> + status = "okay";
>> +};
>> +
>> +&spmi_bus1 {
>> + pmd8028: pmic@4 {
>> + compatible = "qcom,pmd8028", "qcom,spmi-pmic";
>> + reg = <0x4 SPMI_USID>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + pmd8028_temp_alarm: temp-alarm@a00 {
>> + compatible = "qcom,spmi-temp-alarm";
>> + reg = <0xa00>;
>> + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
>> + #thermal-sensor-cells = <0>;
>> + };
>> +
>> + pmd8028_gpios: gpio@8800 {
>> + compatible = "qcom,pmd8028-gpio", "qcom,spmi-gpio";
>> + reg = <0x8800>;
>> + gpio-controller;
>> + gpio-ranges = <&pmd8028_gpios 0 0 4>;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> + };
>> +
>> + pmih0108: pmic@7 {
>> + compatible = "qcom,pmih0108", "qcom,spmi-pmic";
>> + reg = <0x7 SPMI_USID>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + pmih0108_temp_alarm: temp-alarm@a00 {
>> + compatible = "qcom,spmi-temp-alarm";
>> + reg = <0xa00>;
>> + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
>> + #thermal-sensor-cells = <0>;
>> + };
>> +
>> + pmih0108_gpios: gpio@8800 {
>> + compatible = "qcom,pmih0108-gpio", "qcom,spmi-gpio";
>> + reg = <0x8800>;
>> + gpio-controller;
>> + gpio-ranges = <&pmih0108_gpios 0 0 18>;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + pmih0108_eusb2_repeater: phy@fd00 {
>> + compatible = "qcom,pm8550b-eusb2-repeater";
>> + reg = <0xfd00>;
>> + #phy-cells = <0>;
>> + vdd18-supply = <&vreg_l15b_1p8>;
>> + vdd3-supply = <&vreg_l5b_3p1>;
>> + };
>> + };
>> +
>> + pmr735d: pmic@a {
>> + compatible = "qcom,pmr735d", "qcom,spmi-pmic";
>> + reg = <0xa SPMI_USID>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + pmr735d_temp_alarm: temp-alarm@a00 {
>> + compatible = "qcom,spmi-temp-alarm";
>> + reg = <0xa00>;
>> + interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
>> + #thermal-sensor-cells = <0>;
>> + };
>> +
>> + pmr735d_gpios: gpio@8800 {
>> + compatible = "qcom,pmr735d-gpio", "qcom,spmi-gpio";
>> + reg = <0x8800>;
>> + gpio-controller;
>> + gpio-ranges = <&pmr735d_gpios 0 0 2>;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> + };
>> +
>> + pm8010_m: pmic@c {
>> + compatible = "qcom,pm8010", "qcom,spmi-pmic";
>> + reg = <0xc SPMI_USID>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + pm8010_m_temp_alarm: temp-alarm@2400 {
>> + compatible = "qcom,spmi-temp-alarm";
>> + reg = <0x2400>;
>> + interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
>> + #thermal-sensor-cells = <0>;
>> + };
>> + };
>> +
>> + pm8010_n: pmic@d {
>> + compatible = "qcom,pm8010", "qcom,spmi-pmic";
>> + reg = <0xd SPMI_USID>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + pm8010_n_temp_alarm: temp-alarm@2400 {
>> + compatible = "qcom,spmi-temp-alarm";
>> + reg = <0x2400>;
>> + interrupts = <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
>> + #thermal-sensor-cells = <0>;
>> + };
>> + };
>> +};
>> +
>> +&pmh0101_flash {
>
> spmi > pmh0101_flash
>
will fix
>> + status = "okay";
>> +
>> + led-0 {
>> + function = LED_FUNCTION_FLASH;
>> + function-enumerator = <0>;
>> + color = <LED_COLOR_ID_YELLOW>;
>> + led-sources = <1>, <4>;
>> + led-max-microamp = <500000>;
>> + flash-max-microamp = <2000000>;
>> + flash-max-timeout-us = <1280000>;
>> + };
>> +
>> + led-1 {
>> + function = LED_FUNCTION_FLASH;
>> + function-enumerator = <1>;
>> + color = <LED_COLOR_ID_WHITE>;
>> + led-sources = <2>, <3>;
>> + led-max-microamp = <500000>;
>> + flash-max-microamp = <2000000>;
>> + flash-max-timeout-us = <1280000>;
>> + };
>> +};
>> +
>> +&pmh0101_pwm {
>> + status = "okay";
>> +
>> + multi-led {
>> + color = <LED_COLOR_ID_RGB>;
>> + function = LED_FUNCTION_STATUS;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + led@1 {
>> + reg = <1>;
>> + color = <LED_COLOR_ID_RED>;
>> + };
>> +
>> + led@2 {
>> + reg = <2>;
>> + color = <LED_COLOR_ID_GREEN>;
>> + };
>> +
>> + led@3 {
>> + reg = <3>;
>> + color = <LED_COLOR_ID_BLUE>;
>> + };
>> + };
>> +};
>> +
>> +&tlmm {
>> + wlan_en: wlan-en-state {
>> + pins = "gpio16";
>> + function = "gpio";
>> + drive-strength = <8>;
>> + bias-pull-down;
>> + };
>
> Why are the TLMM pin entries sorted?
>
>> +
>> + sw_ctrl_default: sw-ctrl-default-state {
>> + pins = "gpio18";
>> + function = "gpio";
>> + bias-pull-down;
>> + };
>> +
>> + key_vol_up_default: key-vol-up-default-state {
>> + pins = "gpio101";
>> + function = "gpio";
>> + output-disable;
>> + bias-pull-up;
>> + };
>> +
>> + pcie0_default_state: pcie0-default-state {
>> + clkreq-n-pins {
>> + pins = "gpio103";
>> + function = "pcie0_clk_req_n";
>> + drive-strength = <2>;
>> + bias-pull-up;
>> + };
>> +
>> + perst-n-pins {
>> + pins = "gpio102";
>> + function = "gpio";
>> + drive-strength = <2>;
>> + bias-disable;
>> + };
>> +
>> + wake-n-pins {
>> + pins = "gpio104";
>> + function = "gpio";
>> + drive-strength = <2>;
>> + bias-pull-up;
>> + };
>> + };
>> +};
>> +
>> +&pcie0 {
>
> This is also in the wrong place. Please keep the nodes sorted.
>
will fix
>> + pinctrl-0 = <&pcie0_default_state>;
>> + pinctrl-names = "default";
>> +
>> + status = "okay";
>> +};
>> +
>> +&pcie0_phy {
>> + vdda-phy-supply = <&vreg_l3i_0p8>;
>> + vdda-pll-supply = <&vreg_l1d_1p2>;
>> +
>> + status = "okay";
>> +};
>> +
>> @@ -702,3 +1343,25 @@ &ufs_mem_phy {
>>
>> status = "okay";
>> };
>> +
>> +&usb_1 {
>> + dr_mode = "peripheral";
>
> Is it really peripheral-only?
>
>> +
>> + status = "okay";
>> +};
>> +
>> +&usb_1_hsphy {
>> + vdd-supply = <&vreg_l4f_0p8>;
>> + vdda12-supply = <&vreg_l1d_1p2>;
>> +
>> + phys = <&pmih0108_eusb2_repeater>;
>> +
>> + status = "okay";
>> +};
>> +
>> +&usb_dp_qmpphy {
>> + vdda-phy-supply = <&vreg_l1d_1p2>;
>> + vdda-pll-supply = <&vreg_l4f_0p8>;
>> +
>> + status = "okay";
>> +};
>>
>> --
>> 2.25.1
>>
>
Thanks,
Jingyi
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 14/20] arm64: dts: qcom: kaanapali-mtp: Enable more features
2025-09-25 0:17 ` [PATCH 14/20] arm64: dts: qcom: kaanapali-mtp: Enable more features Jingyi Wang
2025-09-25 2:09 ` Dmitry Baryshkov
@ 2025-09-25 8:03 ` Eugen Hristev
2025-10-09 13:54 ` Jishnu Prakash
1 sibling, 1 reply; 135+ messages in thread
From: Eugen Hristev @ 2025-09-25 8:03 UTC (permalink / raw)
To: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang
On 9/25/25 03:17, Jingyi Wang wrote:
> Enable more features on Kaanapali MTP boards including PMIC peripherals,
> bus, SDHCI, remoteprocs, USB, PCIE, WLAN and Bluetooth.
>
> Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
> (added USB), Manish Pandey(added SDHCI), Jishnu Prakash(added PMIC),
> Qiang Yu(added PCIE), Yijie Yang(Added WLAN) and Zijun Hu(Added Bluetooth).
>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 663 +++++++++++++++++++++++++++++
> 1 file changed, 663 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> index 9cf3158e2712..2949579481a9 100644
> --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> @@ -5,9 +5,23 @@
>
> /dts-v1/;
>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/linux-event-codes.h>
> +#include <dt-bindings/leds/common.h>
> #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> #include "kaanapali.dtsi"
>
> +#define PMH0110_D_E0_SID 3
> +#define PMH0110_F_E0_SID 5
> +#define PMH0110_G_E0_SID 6
> +#define PMH0110_I_E0_SID 8
> +#define PMH0104_J_E1_SID 9
> +
> +#include "pmk8850.dtsi"
> +#include "pmh0101.dtsi"
> +#include "pmh0110.dtsi"
> +#include "pmh0104.dtsi"
> +
> / {
> model = "Qualcomm Technologies, Inc. Kaanapali MTP";
> compatible = "qcom,kaanapali-mtp", "qcom,kaanapali";
> @@ -15,6 +29,7 @@ / {
>
> aliases {
> serial0 = &uart7;
> + serial1 = &uart18;
> };
>
> chosen {
> @@ -52,6 +67,304 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
> clock-div = <2>;
> };
> };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + pinctrl-0 = <&key_vol_up_default>;
> + pinctrl-names = "default";
> +
> + key-volume-up {
> + label = "Volume Up";
> + linux,code = <KEY_VOLUMEUP>;
> + gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
> + debounce-interval = <15>;
> + linux,can-disable;
> + wakeup-source;
> + };
> + };
> +
> + thermal-zones {
> + pmh0101-thermal {
> + polling-delay-passive = <100>;
> +
> + thermal-sensors = <&pmh0101_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pmh0104-thermal {
> + polling-delay-passive = <100>;
> +
> + thermal-sensors = <&pmh0104_j_e1_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pmh0110-d-thermal {
> + polling-delay-passive = <100>;
> +
> + thermal-sensors = <&pmh0110_d_e0_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pmh0110-f-thermal {
> + polling-delay-passive = <100>;
> +
> + thermal-sensors = <&pmh0110_f_e0_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pmh0110-g-thermal {
> + polling-delay-passive = <100>;
> +
> + thermal-sensors = <&pmh0110_g_e0_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pmh0110-i-thermal {
> + polling-delay-passive = <100>;
> +
> + thermal-sensors = <&pmh0110_i_e0_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pmd8028-thermal {
> + polling-delay-passive = <100>;
> + thermal-sensors = <&pmd8028_temp_alarm>;
> +
> + trips {
> + pmd8028_trip0: trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + pmd8028_trip1: trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pmih0108-thermal {
> + polling-delay-passive = <100>;
> + thermal-sensors = <&pmih0108_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pmr735d-thermal {
> + polling-delay-passive = <100>;
> +
> + thermal-sensors = <&pmr735d_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pm8010-m-thermal {
> + polling-delay-passive = <100>;
> +
> + thermal-sensors = <&pm8010_m_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> +
> + pm8010-n-thermal {
> + polling-delay-passive = <100>;
> +
> + thermal-sensors = <&pm8010_n_temp_alarm>;
> +
> + trips {
> + trip0 {
> + temperature = <95000>;
> + hysteresis = <0>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "hot";
> + };
> + };
> + };
> + };
> +
> + wcn7850-pmu {
> + compatible = "qcom,wcn7850-pmu";
> +
> + pinctrl-0 = <&bt_default>, <&sw_ctrl_default>, <&wlan_en>;
> + pinctrl-names = "default";
> +
> + bt-enable-gpios = <&pmh0104_j_e1_gpios 5 GPIO_ACTIVE_HIGH>;
> + wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
> +
> + vdd-supply = <&vreg_s2j_0p8>;
> + vddio-supply = <&vreg_l2g_1p8>;
> + vddio1p2-supply = <&vreg_l3g_1p2>;
> + vddaon-supply = <&vreg_s7g_0p9>;
> + vdddig-supply = <&vreg_s1j_0p8>;
> + vddrfa1p2-supply = <&vreg_s7f_1p2>;
> + vddrfa1p8-supply = <&vreg_s8f_1p8>;
> +
> + clocks = <&rpmhcc RPMH_RF_CLK1>;
> +
> + regulators {
> + vreg_pmu_rfa_cmn: ldo0 {
> + regulator-name = "vreg_pmu_rfa_cmn";
> + };
> +
> + vreg_pmu_aon_0p59: ldo1 {
> + regulator-name = "vreg_pmu_aon_0p59";
> + };
> +
> + vreg_pmu_wlcx_0p8: ldo2 {
> + regulator-name = "vreg_pmu_wlcx_0p8";
> + };
> +
> + vreg_pmu_wlmx_0p85: ldo3 {
> + regulator-name = "vreg_pmu_wlmx_0p85";
> + };
> +
> + vreg_pmu_btcmx_0p85: ldo4 {
> + regulator-name = "vreg_pmu_btcmx_0p85";
> + };
> +
> + vreg_pmu_rfa_0p8: ldo5 {
> + regulator-name = "vreg_pmu_rfa_0p8";
> + };
> +
> + vreg_pmu_rfa_1p2: ldo6 {
> + regulator-name = "vreg_pmu_rfa_1p2";
> + };
> +
> + vreg_pmu_rfa_1p8: ldo7 {
> + regulator-name = "vreg_pmu_rfa_1p8";
> + };
> +
> + vreg_pmu_pcie_0p9: ldo8 {
> + regulator-name = "vreg_pmu_pcie_0p9";
> + };
> +
> + vreg_pmu_pcie_1p8: ldo9 {
> + regulator-name = "vreg_pmu_pcie_1p8";
> + };
> + };
> + };
> };
>
> &apps_rsc {
> @@ -674,6 +987,304 @@ vreg_l7n_3p3: ldo7 {
> };
> };
>
> +&pmh0110_d_e0 {
> + status = "okay";
> +};
> +
> +&pmh0110_f_e0 {
> + status = "okay";
> +};
> +
> +&pmh0110_g_e0 {
> + status = "okay";
> +};
> +
> +&pmh0110_i_e0 {
> + status = "okay";
> +};
> +
> +&spmi_bus1 {
> + pmd8028: pmic@4 {
> + compatible = "qcom,pmd8028", "qcom,spmi-pmic";
> + reg = <0x4 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pmd8028_temp_alarm: temp-alarm@a00 {
> + compatible = "qcom,spmi-temp-alarm";
> + reg = <0xa00>;
> + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
> + #thermal-sensor-cells = <0>;
> + };
> +
> + pmd8028_gpios: gpio@8800 {
> + compatible = "qcom,pmd8028-gpio", "qcom,spmi-gpio";
> + reg = <0x8800>;
> + gpio-controller;
> + gpio-ranges = <&pmd8028_gpios 0 0 4>;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> + pmih0108: pmic@7 {
> + compatible = "qcom,pmih0108", "qcom,spmi-pmic";
> + reg = <0x7 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pmih0108_temp_alarm: temp-alarm@a00 {
> + compatible = "qcom,spmi-temp-alarm";
> + reg = <0xa00>;
> + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
> + #thermal-sensor-cells = <0>;
> + };
> +
> + pmih0108_gpios: gpio@8800 {
> + compatible = "qcom,pmih0108-gpio", "qcom,spmi-gpio";
> + reg = <0x8800>;
> + gpio-controller;
> + gpio-ranges = <&pmih0108_gpios 0 0 18>;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + pmih0108_eusb2_repeater: phy@fd00 {
> + compatible = "qcom,pm8550b-eusb2-repeater";
> + reg = <0xfd00>;
> + #phy-cells = <0>;
> + vdd18-supply = <&vreg_l15b_1p8>;
> + vdd3-supply = <&vreg_l5b_3p1>;
> + };
> + };
> +
> + pmr735d: pmic@a {
Hi,
The PMR735D is available in pmr735d_a.dtsi
Can we find a way to reuse that include file instead of duplicating it
here ?
> + compatible = "qcom,pmr735d", "qcom,spmi-pmic";
> + reg = <0xa SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pmr735d_temp_alarm: temp-alarm@a00 {
> + compatible = "qcom,spmi-temp-alarm";
> + reg = <0xa00>;
> + interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
> + #thermal-sensor-cells = <0>;
> + };
> +
> + pmr735d_gpios: gpio@8800 {
> + compatible = "qcom,pmr735d-gpio", "qcom,spmi-gpio";
> + reg = <0x8800>;
> + gpio-controller;
> + gpio-ranges = <&pmr735d_gpios 0 0 2>;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
[...]
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 14/20] arm64: dts: qcom: kaanapali-mtp: Enable more features
2025-09-25 8:03 ` Eugen Hristev
@ 2025-10-09 13:54 ` Jishnu Prakash
2025-10-09 14:58 ` Eugen Hristev
0 siblings, 1 reply; 135+ messages in thread
From: Jishnu Prakash @ 2025-10-09 13:54 UTC (permalink / raw)
To: Eugen Hristev, Jingyi Wang, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang
Hi Eugen,
On 9/25/2025 1:33 PM, Eugen Hristev wrote:
>
>
> On 9/25/25 03:17, Jingyi Wang wrote:
>> Enable more features on Kaanapali MTP boards including PMIC peripherals,
>> bus, SDHCI, remoteprocs, USB, PCIE, WLAN and Bluetooth.
>>
>> Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
>> (added USB), Manish Pandey(added SDHCI), Jishnu Prakash(added PMIC),
>> Qiang Yu(added PCIE), Yijie Yang(Added WLAN) and Zijun Hu(Added Bluetooth).
>>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 663 +++++++++++++++++++++++++++++
>> 1 file changed, 663 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>> index 9cf3158e2712..2949579481a9 100644
>> --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>> +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>> @@ -5,9 +5,23 @@
>>
...
>> +
>> +&spmi_bus1 {
>> + pmd8028: pmic@4 {
>> + compatible = "qcom,pmd8028", "qcom,spmi-pmic";
>> + reg = <0x4 SPMI_USID>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + pmd8028_temp_alarm: temp-alarm@a00 {
>> + compatible = "qcom,spmi-temp-alarm";
>> + reg = <0xa00>;
>> + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
>> + #thermal-sensor-cells = <0>;
>> + };
>> +
>> + pmd8028_gpios: gpio@8800 {
>> + compatible = "qcom,pmd8028-gpio", "qcom,spmi-gpio";
>> + reg = <0x8800>;
>> + gpio-controller;
>> + gpio-ranges = <&pmd8028_gpios 0 0 4>;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> + };
>> +
>> + pmih0108: pmic@7 {
>> + compatible = "qcom,pmih0108", "qcom,spmi-pmic";
>> + reg = <0x7 SPMI_USID>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + pmih0108_temp_alarm: temp-alarm@a00 {
>> + compatible = "qcom,spmi-temp-alarm";
>> + reg = <0xa00>;
>> + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
>> + #thermal-sensor-cells = <0>;
>> + };
>> +
>> + pmih0108_gpios: gpio@8800 {
>> + compatible = "qcom,pmih0108-gpio", "qcom,spmi-gpio";
>> + reg = <0x8800>;
>> + gpio-controller;
>> + gpio-ranges = <&pmih0108_gpios 0 0 18>;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + pmih0108_eusb2_repeater: phy@fd00 {
>> + compatible = "qcom,pm8550b-eusb2-repeater";
>> + reg = <0xfd00>;
>> + #phy-cells = <0>;
>> + vdd18-supply = <&vreg_l15b_1p8>;
>> + vdd3-supply = <&vreg_l5b_3p1>;
>> + };
>> + };
>> +
>> + pmr735d: pmic@a {
>
> Hi,
>
> The PMR735D is available in pmr735d_a.dtsi
>
> Can we find a way to reuse that include file instead of duplicating it
> here ?
In pmr735d_a.dtsi, the peripherals are added under the parent phandle
"spmi_bus", which was commonly used in older SoCs having only a single
bus under the PMIC arbiter, but in Kaanapali, there are two buses
present under the PMIC arbiter, with phandles "spmi_bus0" and "spmi_bus1",
so we cannot include the file as it is.
Thanks,
Jishnu
>
>> + compatible = "qcom,pmr735d", "qcom,spmi-pmic";
>> + reg = <0xa SPMI_USID>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + pmr735d_temp_alarm: temp-alarm@a00 {
>> + compatible = "qcom,spmi-temp-alarm";
>> + reg = <0xa00>;
>> + interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
>> + #thermal-sensor-cells = <0>;
>> + };
>> +
>> + pmr735d_gpios: gpio@8800 {
>> + compatible = "qcom,pmr735d-gpio", "qcom,spmi-gpio";
>> + reg = <0x8800>;
>> + gpio-controller;
>> + gpio-ranges = <&pmr735d_gpios 0 0 2>;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> + };
>> +
>
>
> [...]
>
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 14/20] arm64: dts: qcom: kaanapali-mtp: Enable more features
2025-10-09 13:54 ` Jishnu Prakash
@ 2025-10-09 14:58 ` Eugen Hristev
2025-10-09 16:28 ` Dmitry Baryshkov
0 siblings, 1 reply; 135+ messages in thread
From: Eugen Hristev @ 2025-10-09 14:58 UTC (permalink / raw)
To: Jishnu Prakash, Jingyi Wang, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang
On 10/9/25 16:54, Jishnu Prakash wrote:
> Hi Eugen,
>
> On 9/25/2025 1:33 PM, Eugen Hristev wrote:
>>
>>
>> On 9/25/25 03:17, Jingyi Wang wrote:
>>> Enable more features on Kaanapali MTP boards including PMIC peripherals,
>>> bus, SDHCI, remoteprocs, USB, PCIE, WLAN and Bluetooth.
>>>
>>> Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
>>> (added USB), Manish Pandey(added SDHCI), Jishnu Prakash(added PMIC),
>>> Qiang Yu(added PCIE), Yijie Yang(Added WLAN) and Zijun Hu(Added Bluetooth).
>>>
>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 663 +++++++++++++++++++++++++++++
>>> 1 file changed, 663 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>>> index 9cf3158e2712..2949579481a9 100644
>>> --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>>> +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>>> @@ -5,9 +5,23 @@
>>>
>
> ...
>
>>> +
>>> +&spmi_bus1 {
>>> + pmd8028: pmic@4 {
>>> + compatible = "qcom,pmd8028", "qcom,spmi-pmic";
>>> + reg = <0x4 SPMI_USID>;
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + pmd8028_temp_alarm: temp-alarm@a00 {
>>> + compatible = "qcom,spmi-temp-alarm";
>>> + reg = <0xa00>;
>>> + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
>>> + #thermal-sensor-cells = <0>;
>>> + };
>>> +
>>> + pmd8028_gpios: gpio@8800 {
>>> + compatible = "qcom,pmd8028-gpio", "qcom,spmi-gpio";
>>> + reg = <0x8800>;
>>> + gpio-controller;
>>> + gpio-ranges = <&pmd8028_gpios 0 0 4>;
>>> + #gpio-cells = <2>;
>>> + interrupt-controller;
>>> + #interrupt-cells = <2>;
>>> + };
>>> + };
>>> +
>>> + pmih0108: pmic@7 {
>>> + compatible = "qcom,pmih0108", "qcom,spmi-pmic";
>>> + reg = <0x7 SPMI_USID>;
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + pmih0108_temp_alarm: temp-alarm@a00 {
>>> + compatible = "qcom,spmi-temp-alarm";
>>> + reg = <0xa00>;
>>> + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
>>> + #thermal-sensor-cells = <0>;
>>> + };
>>> +
>>> + pmih0108_gpios: gpio@8800 {
>>> + compatible = "qcom,pmih0108-gpio", "qcom,spmi-gpio";
>>> + reg = <0x8800>;
>>> + gpio-controller;
>>> + gpio-ranges = <&pmih0108_gpios 0 0 18>;
>>> + #gpio-cells = <2>;
>>> + interrupt-controller;
>>> + #interrupt-cells = <2>;
>>> + };
>>> +
>>> + pmih0108_eusb2_repeater: phy@fd00 {
>>> + compatible = "qcom,pm8550b-eusb2-repeater";
>>> + reg = <0xfd00>;
>>> + #phy-cells = <0>;
>>> + vdd18-supply = <&vreg_l15b_1p8>;
>>> + vdd3-supply = <&vreg_l5b_3p1>;
>>> + };
>>> + };
>>> +
>>> + pmr735d: pmic@a {
>>
>> Hi,
>>
>> The PMR735D is available in pmr735d_a.dtsi
>>
>> Can we find a way to reuse that include file instead of duplicating it
>> here ?
>
> In pmr735d_a.dtsi, the peripherals are added under the parent phandle
> "spmi_bus", which was commonly used in older SoCs having only a single
> bus under the PMIC arbiter, but in Kaanapali, there are two buses
> present under the PMIC arbiter, with phandles "spmi_bus0" and "spmi_bus1",
> so we cannot include the file as it is.
>
I know the problem. I disagree with using include files in one case, and
having the PMIC in the dts in the other case.
So there has to be a unified way to handle this in all cases.
Eugen
> Thanks,
> Jishnu
>
>>
>>> + compatible = "qcom,pmr735d", "qcom,spmi-pmic";
>>> + reg = <0xa SPMI_USID>;
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + pmr735d_temp_alarm: temp-alarm@a00 {
>>> + compatible = "qcom,spmi-temp-alarm";
>>> + reg = <0xa00>;
>>> + interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
>>> + #thermal-sensor-cells = <0>;
>>> + };
>>> +
>>> + pmr735d_gpios: gpio@8800 {
>>> + compatible = "qcom,pmr735d-gpio", "qcom,spmi-gpio";
>>> + reg = <0x8800>;
>>> + gpio-controller;
>>> + gpio-ranges = <&pmr735d_gpios 0 0 2>;
>>> + #gpio-cells = <2>;
>>> + interrupt-controller;
>>> + #interrupt-cells = <2>;
>>> + };
>>> + };
>>> +
>>
>>
>> [...]
>>
>
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 14/20] arm64: dts: qcom: kaanapali-mtp: Enable more features
2025-10-09 14:58 ` Eugen Hristev
@ 2025-10-09 16:28 ` Dmitry Baryshkov
2025-10-10 10:54 ` Jishnu Prakash
0 siblings, 1 reply; 135+ messages in thread
From: Dmitry Baryshkov @ 2025-10-09 16:28 UTC (permalink / raw)
To: Eugen Hristev
Cc: Jishnu Prakash, Jingyi Wang, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni,
yijie.yang
On Thu, Oct 09, 2025 at 05:58:03PM +0300, Eugen Hristev wrote:
>
>
> On 10/9/25 16:54, Jishnu Prakash wrote:
> > Hi Eugen,
> >
> > On 9/25/2025 1:33 PM, Eugen Hristev wrote:
> >>
> >>
> >> On 9/25/25 03:17, Jingyi Wang wrote:
> >>> Enable more features on Kaanapali MTP boards including PMIC peripherals,
> >>> bus, SDHCI, remoteprocs, USB, PCIE, WLAN and Bluetooth.
> >>>
> >>> Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
> >>> (added USB), Manish Pandey(added SDHCI), Jishnu Prakash(added PMIC),
> >>> Qiang Yu(added PCIE), Yijie Yang(Added WLAN) and Zijun Hu(Added Bluetooth).
> >>>
> >>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> >>> ---
> >>> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 663 +++++++++++++++++++++++++++++
> >>> 1 file changed, 663 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> >>> index 9cf3158e2712..2949579481a9 100644
> >>> --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> >>> +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> >>> @@ -5,9 +5,23 @@
> >>>
> >
> > ...
> >
> >>> +
> >>> +&spmi_bus1 {
> >>> + pmd8028: pmic@4 {
> >>> + compatible = "qcom,pmd8028", "qcom,spmi-pmic";
> >>> + reg = <0x4 SPMI_USID>;
> >>> + #address-cells = <1>;
> >>> + #size-cells = <0>;
> >>> +
> >>> + pmd8028_temp_alarm: temp-alarm@a00 {
> >>> + compatible = "qcom,spmi-temp-alarm";
> >>> + reg = <0xa00>;
> >>> + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
> >>> + #thermal-sensor-cells = <0>;
> >>> + };
> >>> +
> >>> + pmd8028_gpios: gpio@8800 {
> >>> + compatible = "qcom,pmd8028-gpio", "qcom,spmi-gpio";
> >>> + reg = <0x8800>;
> >>> + gpio-controller;
> >>> + gpio-ranges = <&pmd8028_gpios 0 0 4>;
> >>> + #gpio-cells = <2>;
> >>> + interrupt-controller;
> >>> + #interrupt-cells = <2>;
> >>> + };
> >>> + };
> >>> +
> >>> + pmih0108: pmic@7 {
> >>> + compatible = "qcom,pmih0108", "qcom,spmi-pmic";
> >>> + reg = <0x7 SPMI_USID>;
> >>> + #address-cells = <1>;
> >>> + #size-cells = <0>;
> >>> +
> >>> + pmih0108_temp_alarm: temp-alarm@a00 {
> >>> + compatible = "qcom,spmi-temp-alarm";
> >>> + reg = <0xa00>;
> >>> + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
> >>> + #thermal-sensor-cells = <0>;
> >>> + };
> >>> +
> >>> + pmih0108_gpios: gpio@8800 {
> >>> + compatible = "qcom,pmih0108-gpio", "qcom,spmi-gpio";
> >>> + reg = <0x8800>;
> >>> + gpio-controller;
> >>> + gpio-ranges = <&pmih0108_gpios 0 0 18>;
> >>> + #gpio-cells = <2>;
> >>> + interrupt-controller;
> >>> + #interrupt-cells = <2>;
> >>> + };
> >>> +
> >>> + pmih0108_eusb2_repeater: phy@fd00 {
> >>> + compatible = "qcom,pm8550b-eusb2-repeater";
> >>> + reg = <0xfd00>;
> >>> + #phy-cells = <0>;
> >>> + vdd18-supply = <&vreg_l15b_1p8>;
> >>> + vdd3-supply = <&vreg_l5b_3p1>;
> >>> + };
> >>> + };
> >>> +
> >>> + pmr735d: pmic@a {
> >>
> >> Hi,
> >>
> >> The PMR735D is available in pmr735d_a.dtsi
> >>
> >> Can we find a way to reuse that include file instead of duplicating it
> >> here ?
> >
> > In pmr735d_a.dtsi, the peripherals are added under the parent phandle
> > "spmi_bus", which was commonly used in older SoCs having only a single
> > bus under the PMIC arbiter, but in Kaanapali, there are two buses
> > present under the PMIC arbiter, with phandles "spmi_bus0" and "spmi_bus1",
> > so we cannot include the file as it is.
> >
>
> I know the problem. I disagree with using include files in one case, and
> having the PMIC in the dts in the other case.
>
> So there has to be a unified way to handle this in all cases.
Rework SPMI PMICs to follow the approach started by Johan for PM8008. I
think this is the way to go.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 14/20] arm64: dts: qcom: kaanapali-mtp: Enable more features
2025-10-09 16:28 ` Dmitry Baryshkov
@ 2025-10-10 10:54 ` Jishnu Prakash
2025-10-10 14:02 ` Eugen Hristev
0 siblings, 1 reply; 135+ messages in thread
From: Jishnu Prakash @ 2025-10-10 10:54 UTC (permalink / raw)
To: Dmitry Baryshkov, Eugen Hristev
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang
Hi Dmitry and Eugen,
On 10/9/2025 9:58 PM, Dmitry Baryshkov wrote:
> On Thu, Oct 09, 2025 at 05:58:03PM +0300, Eugen Hristev wrote:
>>
>>
>> On 10/9/25 16:54, Jishnu Prakash wrote:
>>> Hi Eugen,
>>>
>>> On 9/25/2025 1:33 PM, Eugen Hristev wrote:
>>>>
>>>>
>>>> On 9/25/25 03:17, Jingyi Wang wrote:
>>>>> Enable more features on Kaanapali MTP boards including PMIC peripherals,
>>>>> bus, SDHCI, remoteprocs, USB, PCIE, WLAN and Bluetooth.
>>>>>
>>>>> Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
>>>>> (added USB), Manish Pandey(added SDHCI), Jishnu Prakash(added PMIC),
>>>>> Qiang Yu(added PCIE), Yijie Yang(Added WLAN) and Zijun Hu(Added Bluetooth).
>>>>>
>>>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>>>>> ---
>>>>> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 663 +++++++++++++++++++++++++++++
>>>>> 1 file changed, 663 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>>>>> index 9cf3158e2712..2949579481a9 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>>>>> +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>>>>> @@ -5,9 +5,23 @@
>>>>>
>>>
>>> ...
>>>
>>>>> +
>>>>> +&spmi_bus1 {
>>>>> + pmd8028: pmic@4 {
>>>>> + compatible = "qcom,pmd8028", "qcom,spmi-pmic";
>>>>> + reg = <0x4 SPMI_USID>;
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> +
>>>>> + pmd8028_temp_alarm: temp-alarm@a00 {
>>>>> + compatible = "qcom,spmi-temp-alarm";
>>>>> + reg = <0xa00>;
>>>>> + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
>>>>> + #thermal-sensor-cells = <0>;
>>>>> + };
>>>>> +
>>>>> + pmd8028_gpios: gpio@8800 {
>>>>> + compatible = "qcom,pmd8028-gpio", "qcom,spmi-gpio";
>>>>> + reg = <0x8800>;
>>>>> + gpio-controller;
>>>>> + gpio-ranges = <&pmd8028_gpios 0 0 4>;
>>>>> + #gpio-cells = <2>;
>>>>> + interrupt-controller;
>>>>> + #interrupt-cells = <2>;
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + pmih0108: pmic@7 {
>>>>> + compatible = "qcom,pmih0108", "qcom,spmi-pmic";
>>>>> + reg = <0x7 SPMI_USID>;
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> +
>>>>> + pmih0108_temp_alarm: temp-alarm@a00 {
>>>>> + compatible = "qcom,spmi-temp-alarm";
>>>>> + reg = <0xa00>;
>>>>> + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
>>>>> + #thermal-sensor-cells = <0>;
>>>>> + };
>>>>> +
>>>>> + pmih0108_gpios: gpio@8800 {
>>>>> + compatible = "qcom,pmih0108-gpio", "qcom,spmi-gpio";
>>>>> + reg = <0x8800>;
>>>>> + gpio-controller;
>>>>> + gpio-ranges = <&pmih0108_gpios 0 0 18>;
>>>>> + #gpio-cells = <2>;
>>>>> + interrupt-controller;
>>>>> + #interrupt-cells = <2>;
>>>>> + };
>>>>> +
>>>>> + pmih0108_eusb2_repeater: phy@fd00 {
>>>>> + compatible = "qcom,pm8550b-eusb2-repeater";
>>>>> + reg = <0xfd00>;
>>>>> + #phy-cells = <0>;
>>>>> + vdd18-supply = <&vreg_l15b_1p8>;
>>>>> + vdd3-supply = <&vreg_l5b_3p1>;
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + pmr735d: pmic@a {
>>>>
>>>> Hi,
>>>>
>>>> The PMR735D is available in pmr735d_a.dtsi
>>>>
>>>> Can we find a way to reuse that include file instead of duplicating it
>>>> here ?
>>>
>>> In pmr735d_a.dtsi, the peripherals are added under the parent phandle
>>> "spmi_bus", which was commonly used in older SoCs having only a single
>>> bus under the PMIC arbiter, but in Kaanapali, there are two buses
>>> present under the PMIC arbiter, with phandles "spmi_bus0" and "spmi_bus1",
>>> so we cannot include the file as it is.
>>>
>>
>> I know the problem. I disagree with using include files in one case, and
>> having the PMIC in the dts in the other case.
>>
>> So there has to be a unified way to handle this in all cases.
>
> Rework SPMI PMICs to follow the approach started by Johan for PM8008. I
> think this is the way to go.
>
We got a recommendation from Krzysztof recently here for Glymur:
https://lore.kernel.org/all/b784387b-5744-422e-92f5-3d575a24d01c@kernel.org/
For PMH0110, he suggested we could keep different DTSI files per SoC,
like pmh0110-kaanapali.dtsi and pmh0110-glymur.dtsi.
We could follow a similar approach on Kaanapali, to
#include the following files in the .dts file:
pmk8850.dtsi
pmh0101.dtsi
pmh0110-kaanapali.dtsi
pmh0104-kaanapali.dtsi
pmd8028-kaanapali.dtsi
pmih0108-kaanapali.dtsi
pmr735d-kaanapali.dtsi
pm8010-kaanapali.dtsi
The first two files are new and common with Glymur,so they
do not have the SoC name suffix.
Hope this is fine, please let us know if you see any issue.
Thanks,
Jishnu
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 14/20] arm64: dts: qcom: kaanapali-mtp: Enable more features
2025-10-10 10:54 ` Jishnu Prakash
@ 2025-10-10 14:02 ` Eugen Hristev
2025-10-13 16:21 ` Kamal Wadhwa
0 siblings, 1 reply; 135+ messages in thread
From: Eugen Hristev @ 2025-10-10 14:02 UTC (permalink / raw)
To: Jishnu Prakash, Dmitry Baryshkov
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang
On 10/10/25 13:54, Jishnu Prakash wrote:
> Hi Dmitry and Eugen,
>
> On 10/9/2025 9:58 PM, Dmitry Baryshkov wrote:
>> On Thu, Oct 09, 2025 at 05:58:03PM +0300, Eugen Hristev wrote:
>>>
>>>
>>> On 10/9/25 16:54, Jishnu Prakash wrote:
>>>> Hi Eugen,
>>>>
>>>> On 9/25/2025 1:33 PM, Eugen Hristev wrote:
>>>>>
>>>>>
>>>>> On 9/25/25 03:17, Jingyi Wang wrote:
>>>>>> Enable more features on Kaanapali MTP boards including PMIC peripherals,
>>>>>> bus, SDHCI, remoteprocs, USB, PCIE, WLAN and Bluetooth.
>>>>>>
>>>>>> Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
>>>>>> (added USB), Manish Pandey(added SDHCI), Jishnu Prakash(added PMIC),
>>>>>> Qiang Yu(added PCIE), Yijie Yang(Added WLAN) and Zijun Hu(Added Bluetooth).
>>>>>>
>>>>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>>>>>> ---
>>>>>> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 663 +++++++++++++++++++++++++++++
>>>>>> 1 file changed, 663 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>>>>>> index 9cf3158e2712..2949579481a9 100644
>>>>>> --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>>>>>> +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>>>>>> @@ -5,9 +5,23 @@
>>>>>>
>>>>
>>>> ...
>>>>
>>>>>> +
>>>>>> +&spmi_bus1 {
>>>>>> + pmd8028: pmic@4 {
>>>>>> + compatible = "qcom,pmd8028", "qcom,spmi-pmic";
>>>>>> + reg = <0x4 SPMI_USID>;
>>>>>> + #address-cells = <1>;
>>>>>> + #size-cells = <0>;
>>>>>> +
>>>>>> + pmd8028_temp_alarm: temp-alarm@a00 {
>>>>>> + compatible = "qcom,spmi-temp-alarm";
>>>>>> + reg = <0xa00>;
>>>>>> + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
>>>>>> + #thermal-sensor-cells = <0>;
>>>>>> + };
>>>>>> +
>>>>>> + pmd8028_gpios: gpio@8800 {
>>>>>> + compatible = "qcom,pmd8028-gpio", "qcom,spmi-gpio";
>>>>>> + reg = <0x8800>;
>>>>>> + gpio-controller;
>>>>>> + gpio-ranges = <&pmd8028_gpios 0 0 4>;
>>>>>> + #gpio-cells = <2>;
>>>>>> + interrupt-controller;
>>>>>> + #interrupt-cells = <2>;
>>>>>> + };
>>>>>> + };
>>>>>> +
>>>>>> + pmih0108: pmic@7 {
>>>>>> + compatible = "qcom,pmih0108", "qcom,spmi-pmic";
>>>>>> + reg = <0x7 SPMI_USID>;
>>>>>> + #address-cells = <1>;
>>>>>> + #size-cells = <0>;
>>>>>> +
>>>>>> + pmih0108_temp_alarm: temp-alarm@a00 {
>>>>>> + compatible = "qcom,spmi-temp-alarm";
>>>>>> + reg = <0xa00>;
>>>>>> + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
>>>>>> + #thermal-sensor-cells = <0>;
>>>>>> + };
>>>>>> +
>>>>>> + pmih0108_gpios: gpio@8800 {
>>>>>> + compatible = "qcom,pmih0108-gpio", "qcom,spmi-gpio";
>>>>>> + reg = <0x8800>;
>>>>>> + gpio-controller;
>>>>>> + gpio-ranges = <&pmih0108_gpios 0 0 18>;
>>>>>> + #gpio-cells = <2>;
>>>>>> + interrupt-controller;
>>>>>> + #interrupt-cells = <2>;
>>>>>> + };
>>>>>> +
>>>>>> + pmih0108_eusb2_repeater: phy@fd00 {
>>>>>> + compatible = "qcom,pm8550b-eusb2-repeater";
>>>>>> + reg = <0xfd00>;
>>>>>> + #phy-cells = <0>;
>>>>>> + vdd18-supply = <&vreg_l15b_1p8>;
>>>>>> + vdd3-supply = <&vreg_l5b_3p1>;
>>>>>> + };
>>>>>> + };
>>>>>> +
>>>>>> + pmr735d: pmic@a {
>>>>>
>>>>> Hi,
>>>>>
>>>>> The PMR735D is available in pmr735d_a.dtsi
>>>>>
>>>>> Can we find a way to reuse that include file instead of duplicating it
>>>>> here ?
>>>>
>>>> In pmr735d_a.dtsi, the peripherals are added under the parent phandle
>>>> "spmi_bus", which was commonly used in older SoCs having only a single
>>>> bus under the PMIC arbiter, but in Kaanapali, there are two buses
>>>> present under the PMIC arbiter, with phandles "spmi_bus0" and "spmi_bus1",
>>>> so we cannot include the file as it is.
>>>>
>>>
>>> I know the problem. I disagree with using include files in one case, and
>>> having the PMIC in the dts in the other case.
>>>
>>> So there has to be a unified way to handle this in all cases.
>>
>> Rework SPMI PMICs to follow the approach started by Johan for PM8008. I
>> think this is the way to go.
>>
>
> We got a recommendation from Krzysztof recently here for Glymur:
> https://lore.kernel.org/all/b784387b-5744-422e-92f5-3d575a24d01c@kernel.org/
>
> For PMH0110, he suggested we could keep different DTSI files per SoC,
> like pmh0110-kaanapali.dtsi and pmh0110-glymur.dtsi.
>
> We could follow a similar approach on Kaanapali, to
> #include the following files in the .dts file:
>
> pmk8850.dtsi
> pmh0101.dtsi
> pmh0110-kaanapali.dtsi
> pmh0104-kaanapali.dtsi
> pmd8028-kaanapali.dtsi
> pmih0108-kaanapali.dtsi
> pmr735d-kaanapali.dtsi
> pm8010-kaanapali.dtsi
>
> The first two files are new and common with Glymur,so they
> do not have the SoC name suffix.
>
> Hope this is fine, please let us know if you see any issue.
I would like it to be consistent, you would have to rename the old
pmr735d.dtsi into pmr735d-whatever-soc-was-using-it.dtsi in another
patch, and then create pmr735d-kaanpali.dtsi for kaanapali.
Does this look good ?
>
> Thanks,
> Jishnu
>
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 14/20] arm64: dts: qcom: kaanapali-mtp: Enable more features
2025-10-10 14:02 ` Eugen Hristev
@ 2025-10-13 16:21 ` Kamal Wadhwa
0 siblings, 0 replies; 135+ messages in thread
From: Kamal Wadhwa @ 2025-10-13 16:21 UTC (permalink / raw)
To: Eugen Hristev
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
kamal.wadhwa
Hi Eugen,
On Fri, Oct 10, 2025 at 05:02:54PM +0300, Eugen Hristev wrote:
>
>
> On 10/10/25 13:54, Jishnu Prakash wrote:
> > Hi Dmitry and Eugen,
> >
> > On 10/9/2025 9:58 PM, Dmitry Baryshkov wrote:
> >> On Thu, Oct 09, 2025 at 05:58:03PM +0300, Eugen Hristev wrote:
> >>>
> >>>
> >>> On 10/9/25 16:54, Jishnu Prakash wrote:
> >>>> Hi Eugen,
> >>>>
> >>>> On 9/25/2025 1:33 PM, Eugen Hristev wrote:
> >>>>>
> >>>>>
> >>>>> On 9/25/25 03:17, Jingyi Wang wrote:
> >>>>>> Enable more features on Kaanapali MTP boards including PMIC peripherals,
> >>>>>> bus, SDHCI, remoteprocs, USB, PCIE, WLAN and Bluetooth.
> >>>>>>
> >>>>>> Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
> >>>>>> (added USB), Manish Pandey(added SDHCI), Jishnu Prakash(added PMIC),
> >>>>>> Qiang Yu(added PCIE), Yijie Yang(Added WLAN) and Zijun Hu(Added Bluetooth).
> >>>>>>
> >>>>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> >>>>>> ---
> >>>>>> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 663 +++++++++++++++++++++++++++++
> >>>>>> 1 file changed, 663 insertions(+)
> >>>>>>
> >>>>>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> >>>>>> index 9cf3158e2712..2949579481a9 100644
> >>>>>> --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> >>>>>> +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> >>>>>> @@ -5,9 +5,23 @@
> >>>>>>
> >>>>
> >>>> ...
> >>>>
> >>>>>> +
> >>>>>> +&spmi_bus1 {
> >>>>>> + pmd8028: pmic@4 {
> >>>>>> + compatible = "qcom,pmd8028", "qcom,spmi-pmic";
> >>>>>> + reg = <0x4 SPMI_USID>;
> >>>>>> + #address-cells = <1>;
> >>>>>> + #size-cells = <0>;
> >>>>>> +
> >>>>>> + pmd8028_temp_alarm: temp-alarm@a00 {
> >>>>>> + compatible = "qcom,spmi-temp-alarm";
> >>>>>> + reg = <0xa00>;
> >>>>>> + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
> >>>>>> + #thermal-sensor-cells = <0>;
> >>>>>> + };
> >>>>>> +
> >>>>>> + pmd8028_gpios: gpio@8800 {
> >>>>>> + compatible = "qcom,pmd8028-gpio", "qcom,spmi-gpio";
> >>>>>> + reg = <0x8800>;
> >>>>>> + gpio-controller;
> >>>>>> + gpio-ranges = <&pmd8028_gpios 0 0 4>;
> >>>>>> + #gpio-cells = <2>;
> >>>>>> + interrupt-controller;
> >>>>>> + #interrupt-cells = <2>;
> >>>>>> + };
> >>>>>> + };
> >>>>>> +
> >>>>>> + pmih0108: pmic@7 {
> >>>>>> + compatible = "qcom,pmih0108", "qcom,spmi-pmic";
> >>>>>> + reg = <0x7 SPMI_USID>;
> >>>>>> + #address-cells = <1>;
> >>>>>> + #size-cells = <0>;
> >>>>>> +
> >>>>>> + pmih0108_temp_alarm: temp-alarm@a00 {
> >>>>>> + compatible = "qcom,spmi-temp-alarm";
> >>>>>> + reg = <0xa00>;
> >>>>>> + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
> >>>>>> + #thermal-sensor-cells = <0>;
> >>>>>> + };
> >>>>>> +
> >>>>>> + pmih0108_gpios: gpio@8800 {
> >>>>>> + compatible = "qcom,pmih0108-gpio", "qcom,spmi-gpio";
> >>>>>> + reg = <0x8800>;
> >>>>>> + gpio-controller;
> >>>>>> + gpio-ranges = <&pmih0108_gpios 0 0 18>;
> >>>>>> + #gpio-cells = <2>;
> >>>>>> + interrupt-controller;
> >>>>>> + #interrupt-cells = <2>;
> >>>>>> + };
> >>>>>> +
> >>>>>> + pmih0108_eusb2_repeater: phy@fd00 {
> >>>>>> + compatible = "qcom,pm8550b-eusb2-repeater";
> >>>>>> + reg = <0xfd00>;
> >>>>>> + #phy-cells = <0>;
> >>>>>> + vdd18-supply = <&vreg_l15b_1p8>;
> >>>>>> + vdd3-supply = <&vreg_l5b_3p1>;
> >>>>>> + };
> >>>>>> + };
> >>>>>> +
> >>>>>> + pmr735d: pmic@a {
> >>>>>
> >>>>> Hi,
> >>>>>
> >>>>> The PMR735D is available in pmr735d_a.dtsi
> >>>>>
> >>>>> Can we find a way to reuse that include file instead of duplicating it
> >>>>> here ?
> >>>>
> >>>> In pmr735d_a.dtsi, the peripherals are added under the parent phandle
> >>>> "spmi_bus", which was commonly used in older SoCs having only a single
> >>>> bus under the PMIC arbiter, but in Kaanapali, there are two buses
> >>>> present under the PMIC arbiter, with phandles "spmi_bus0" and "spmi_bus1",
> >>>> so we cannot include the file as it is.
> >>>>
> >>>
> >>> I know the problem. I disagree with using include files in one case, and
> >>> having the PMIC in the dts in the other case.
> >>>
> >>> So there has to be a unified way to handle this in all cases.
> >>
> >> Rework SPMI PMICs to follow the approach started by Johan for PM8008. I
> >> think this is the way to go.
> >>
> >
> > We got a recommendation from Krzysztof recently here for Glymur:
> > https://lore.kernel.org/all/b784387b-5744-422e-92f5-3d575a24d01c@kernel.org/
> >
> > For PMH0110, he suggested we could keep different DTSI files per SoC,
> > like pmh0110-kaanapali.dtsi and pmh0110-glymur.dtsi.
> >
> > We could follow a similar approach on Kaanapali, to
> > #include the following files in the .dts file:
> >
> > pmk8850.dtsi
> > pmh0101.dtsi
> > pmh0110-kaanapali.dtsi
> > pmh0104-kaanapali.dtsi
> > pmd8028-kaanapali.dtsi
> > pmih0108-kaanapali.dtsi
> > pmr735d-kaanapali.dtsi
> > pm8010-kaanapali.dtsi
> >
> > The first two files are new and common with Glymur,so they
> > do not have the SoC name suffix.
> >
> > Hope this is fine, please let us know if you see any issue.
>
> I would like it to be consistent, you would have to rename the old
> pmr735d.dtsi into pmr735d-whatever-soc-was-using-it.dtsi in another
> patch, and then create pmr735d-kaanpali.dtsi for kaanapali.
>
> Does this look good ?
Currently we were thinking to name PMIC dtsi based on below criteria:
- pmic.dtsi can be used `as-is` (common bus-id/spmi-id) for more than
one SoC -> use filename without SoC suffix.
- If there is a delta between two SoCs (old existing pmic file mismatch
busid/spmi-ids) for same PMIC -> have SoC-specific PMIC files.
IMO, This will be sligtly better to identify
- which pmic dtsi is older and have common placement on bus, sid and
other properties for multiple targets.
- Which pmic's have deviated away and landed late on the upstream
NOTE: We have good number of examples where pmics are re-used as-is
with same bus-id and spmi-id eg- pmk8550, pmk8350 etc. So we want to
suffix the target only if the target is not first one to use it and
deviated from the first version, where reuse is not possible.
On the other hand, to align to your request we may have to fix this
retrospectively for all pmics as lot of older pmic.dtsi also will fall
in same catagory, then just simply adding a SoC specific pmic version.
And also losing this (above described) understanding of the `history
and common design` of each pmic.dtsi file.
Does this justification works? Please let us know if you still see
any problems with this naming critria, or we can improve it still?
> >
> > Thanks,
> > Jishnu
> >
Regards,
Kamal
^ permalink raw reply [flat|nested] 135+ messages in thread
* [PATCH 15/20] arm64: dts: qcom: kaanapali-mtp: Enable modem
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (13 preceding siblings ...)
2025-09-25 0:17 ` [PATCH 14/20] arm64: dts: qcom: kaanapali-mtp: Enable more features Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-09-25 2:10 ` Dmitry Baryshkov
2025-09-25 14:06 ` Bjorn Andersson
2025-09-25 0:17 ` [PATCH 16/20] arm64: dts: qcom: kaanapali: Add QRD board Jingyi Wang
` (7 subsequent siblings)
22 siblings, 2 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang
Enable the MODEM on Kaanapali MTP board.
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
index 2949579481a9..8d1b3278389e 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
@@ -1263,6 +1263,14 @@ &remoteproc_cdsp {
status = "okay";
};
+&remoteproc_mpss {
+ firmware-name = "qcom/kaanapali/modem.mbn",
+ "qcom/kaanapali/modem_dtb.mbn";
+
+ /* Modem crashes after some time for OEMPD load failure */
+ status = "fail";
+};
+
&remoteproc_soccp {
firmware-name = "qcom/kaanapali/soccp.mbn",
"qcom/kaanapali/soccp_dtb.mbn";
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* Re: [PATCH 15/20] arm64: dts: qcom: kaanapali-mtp: Enable modem
2025-09-25 0:17 ` [PATCH 15/20] arm64: dts: qcom: kaanapali-mtp: Enable modem Jingyi Wang
@ 2025-09-25 2:10 ` Dmitry Baryshkov
2025-09-29 3:28 ` Jingyi Wang
2025-09-25 14:06 ` Bjorn Andersson
1 sibling, 1 reply; 135+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 2:10 UTC (permalink / raw)
To: Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On Wed, Sep 24, 2025 at 05:17:32PM -0700, Jingyi Wang wrote:
> Enable the MODEM on Kaanapali MTP board.
>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> index 2949579481a9..8d1b3278389e 100644
> --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> @@ -1263,6 +1263,14 @@ &remoteproc_cdsp {
> status = "okay";
> };
>
> +&remoteproc_mpss {
> + firmware-name = "qcom/kaanapali/modem.mbn",
> + "qcom/kaanapali/modem_dtb.mbn";
> +
> + /* Modem crashes after some time for OEMPD load failure */
> + status = "fail";
I can't call this 'enable'. Why is it crashing?
> +};
> +
> &remoteproc_soccp {
> firmware-name = "qcom/kaanapali/soccp.mbn",
> "qcom/kaanapali/soccp_dtb.mbn";
>
> --
> 2.25.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 15/20] arm64: dts: qcom: kaanapali-mtp: Enable modem
2025-09-25 2:10 ` Dmitry Baryshkov
@ 2025-09-29 3:28 ` Jingyi Wang
0 siblings, 0 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-09-29 3:28 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On 9/25/2025 10:10 AM, Dmitry Baryshkov wrote:
> On Wed, Sep 24, 2025 at 05:17:32PM -0700, Jingyi Wang wrote:
>> Enable the MODEM on Kaanapali MTP board.
>>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>> index 2949579481a9..8d1b3278389e 100644
>> --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>> +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>> @@ -1263,6 +1263,14 @@ &remoteproc_cdsp {
>> status = "okay";
>> };
>>
>> +&remoteproc_mpss {
>> + firmware-name = "qcom/kaanapali/modem.mbn",
>> + "qcom/kaanapali/modem_dtb.mbn";
>> +
>> + /* Modem crashes after some time for OEMPD load failure */
>> + status = "fail";
>
> I can't call this 'enable'. Why is it crashing?
>
We see it crash after running for sometime, it was following what SM8750 do
to mark it failed.
However, we will follow that Bjorn suggest, omit this patch or enable it in
next version
Thanks,
Jingyi
>> +};
>> +
>> &remoteproc_soccp {
>> firmware-name = "qcom/kaanapali/soccp.mbn",
>> "qcom/kaanapali/soccp_dtb.mbn";
>>
>> --
>> 2.25.1
>>
>
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 15/20] arm64: dts: qcom: kaanapali-mtp: Enable modem
2025-09-25 0:17 ` [PATCH 15/20] arm64: dts: qcom: kaanapali-mtp: Enable modem Jingyi Wang
2025-09-25 2:10 ` Dmitry Baryshkov
@ 2025-09-25 14:06 ` Bjorn Andersson
2025-09-29 3:29 ` Jingyi Wang
1 sibling, 1 reply; 135+ messages in thread
From: Bjorn Andersson @ 2025-09-25 14:06 UTC (permalink / raw)
To: Jingyi Wang
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang
On Wed, Sep 24, 2025 at 05:17:32PM -0700, Jingyi Wang wrote:
> Enable the MODEM on Kaanapali MTP board.
>
Please omit this until you have gotten it to work, and if that happens
before resubmitting "arm64: dts: qcom: kaanapali-mtp: Enable more
features" squash it into that.
PS. The patch adds a failed node, but the commit message doesn't
describe that, or mention that it is broken.
Thanks,
Bjorn
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> index 2949579481a9..8d1b3278389e 100644
> --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
> @@ -1263,6 +1263,14 @@ &remoteproc_cdsp {
> status = "okay";
> };
>
> +&remoteproc_mpss {
> + firmware-name = "qcom/kaanapali/modem.mbn",
> + "qcom/kaanapali/modem_dtb.mbn";
> +
> + /* Modem crashes after some time for OEMPD load failure */
> + status = "fail";
> +};
> +
> &remoteproc_soccp {
> firmware-name = "qcom/kaanapali/soccp.mbn",
> "qcom/kaanapali/soccp_dtb.mbn";
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 15/20] arm64: dts: qcom: kaanapali-mtp: Enable modem
2025-09-25 14:06 ` Bjorn Andersson
@ 2025-09-29 3:29 ` Jingyi Wang
0 siblings, 0 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-09-29 3:29 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang
On 9/25/2025 10:06 PM, Bjorn Andersson wrote:
> On Wed, Sep 24, 2025 at 05:17:32PM -0700, Jingyi Wang wrote:
>> Enable the MODEM on Kaanapali MTP board.
>>
>
> Please omit this until you have gotten it to work, and if that happens
> before resubmitting "arm64: dts: qcom: kaanapali-mtp: Enable more
> features" squash it into that.
>
>
> PS. The patch adds a failed node, but the commit message doesn't
> describe that, or mention that it is broken.
>
> Thanks,
> Bjorn
>
Well noted.
Thanks,
Jingyi
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>> index 2949579481a9..8d1b3278389e 100644
>> --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>> +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
>> @@ -1263,6 +1263,14 @@ &remoteproc_cdsp {
>> status = "okay";
>> };
>>
>> +&remoteproc_mpss {
>> + firmware-name = "qcom/kaanapali/modem.mbn",
>> + "qcom/kaanapali/modem_dtb.mbn";
>> +
>> + /* Modem crashes after some time for OEMPD load failure */
>> + status = "fail";
>> +};
>> +
>> &remoteproc_soccp {
>> firmware-name = "qcom/kaanapali/soccp.mbn",
>> "qcom/kaanapali/soccp_dtb.mbn";
>>
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 135+ messages in thread
* [PATCH 16/20] arm64: dts: qcom: kaanapali: Add QRD board
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (14 preceding siblings ...)
2025-09-25 0:17 ` [PATCH 15/20] arm64: dts: qcom: kaanapali-mtp: Enable modem Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-09-25 2:15 ` Dmitry Baryshkov
2025-09-25 0:17 ` [PATCH 17/20] arm64: dts: qcom: kaanapali: Add support for audio Jingyi Wang
` (6 subsequent siblings)
22 siblings, 1 reply; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang
Add support for Qualcomm Kaanapali QRD board which enables booting to
shell with uart console, UFS, PMIC peripherals, bus, SDHCI, remoteprocs,
USB, PCIE, WLAN and Bluetooth.
Written with help from Jishnu Prakash (added rpmhpd nodes), Nitin Rawat
(added ufs), Jyothi Kumar Seerapu(added bus), Ronak Raheja (added USB),
Manish Pandey(added SDHCI), Jishnu Prakash(added PMIC), Qiang Yu
(added PCIE), Yijie Yang(Added WLAN) and Zijun Hu(Added Bluetooth).
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 1212 ++++++++++++++++++++++++++++
2 files changed, 1213 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 7edfa5fa00fc..da9ef255073c 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb
dtb-$(CONFIG_ARCH_QCOM) += kaanapali-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM) += kaanapali-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb
lemans-evk-camera-csi1-imx577-dtbs := lemans-evk.dtb lemans-evk-camera-csi1-imx577.dtbo
diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
new file mode 100644
index 000000000000..5900812c74a5
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
@@ -0,0 +1,1212 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "kaanapali.dtsi"
+
+#define PMH0110_D_E0_SID 3
+#define PMH0110_F_E0_SID 5
+#define PMH0110_G_E0_SID 6
+#define PMH0110_I_E0_SID 8
+#define PMH0104_J_E1_SID 9
+
+#include "pmk8850.dtsi"
+#include "pmh0101.dtsi"
+#include "pmh0110.dtsi"
+#include "pmh0104.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Kaanapali QRD";
+ compatible = "qcom,kaanapali-qrd", "qcom,kaanapali";
+ chassis-type = "handset";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <76800000>;
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32764>;
+ #clock-cells = <0>;
+ };
+
+ bi_tcxo_div2: bi-tcxo-div2-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK_A>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&key_vol_up_default>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ thermal-zones {
+ pmh0101-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pmh0101_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmh0104-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pmh0104_j_e1_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmh0110-d-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pmh0110_d_e0_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmh0110-f-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pmh0110_f_e0_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmh0110-g-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pmh0110_g_e0_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmh0110-i-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pmh0110_i_e0_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmd8028-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pmd8028_temp_alarm>;
+
+ trips {
+ pmd8028_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pmd8028_trip1: trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmih0108-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pmih0108_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmr735d-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pmr735d_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pm8010-m-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8010_m_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pm8010-n-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8010_n_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pmh0101-rpmh-regulators";
+
+ qcom,pmic-id = "B_E0";
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <4000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <3552000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3048000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l4b_1p8: ldo4 {
+ regulator-name = "vreg_l4b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3148000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10b_1p8: ldo10 {
+ regulator-name = "vreg_l10b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l11b_1p0: ldo11 {
+ regulator-name = "vreg_l11b_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1292000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18b_1p2: ldo18 {
+ regulator-name = "vreg_l18b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+
+ qcom,pmic-id = "D_E0";
+
+ vreg_s10d_1p0: smps10 {
+ regulator-name = "vreg_s10d_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1d_1p2: ldo1 {
+ regulator-name = "vreg_l1d_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1256000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l2d_0p9: ldo2 {
+ regulator-name = "vreg_l2d_0p9";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <958000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l3d_0p8: ldo3 {
+ regulator-name = "vreg_l3d_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l4d_1p2: ldo4 {
+ regulator-name = "vreg_l4d_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+
+ qcom,pmic-id = "F_E0";
+
+ vreg_s6f_0p5: smps6 {
+ regulator-name = "vreg_s6f_0p5";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <570000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s7f_1p2: smps7 {
+ regulator-name = "vreg_s7f_1p2";
+ regulator-min-microvolt = <1224000>;
+ regulator-max-microvolt = <1372000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s8f_1p8: smps8 {
+ regulator-name = "vreg_s8f_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_1p2: ldo1 {
+ regulator-name = "vreg_l1f_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l2f_1p2: ldo2 {
+ regulator-name = "vreg_l2f_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l3f_0p8: ldo3 {
+ regulator-name = "vreg_l3f_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <936000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l4f_0p8: ldo4 {
+ regulator-name = "vreg_l4f_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+
+ qcom,pmic-id = "G_E0";
+
+ vreg_s7g_0p9: smps7 {
+ regulator-name = "vreg_s7g_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s9g_1p0: smps9 {
+ regulator-name = "vreg_s9g_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1g_1p2: ldo1 {
+ regulator-name = "vreg_l1g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l2g_1p8: ldo2 {
+ regulator-name = "vreg_l2g_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l4g_0p9: ldo4 {
+ regulator-name = "vreg_l4g_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+
+ qcom,pmic-id = "I_E0";
+
+ vreg_s7i_0p9: smps7 {
+ regulator-name = "vreg_s7i_0p9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <972000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2i_1p2: ldo2 {
+ regulator-name = "vreg_l2i_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l3i_0p8: ldo3 {
+ regulator-name = "vreg_l3i_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pmh0104-rpmh-regulators";
+
+ qcom,pmic-id = "J_E1";
+
+ vreg_s1j_0p8: smps1 {
+ regulator-name = "vreg_s1j_0p8";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2j_0p8: smps2 {
+ regulator-name = "vreg_s2j_0p8";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3j_1p2: smps3 {
+ regulator-name = "vreg_s3j_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4j_0p7: smps4 {
+ regulator-name = "vreg_s4j_0p7";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pmr735d-rpmh-regulators";
+
+ qcom,pmic-id = "K_E1";
+
+ vreg_l1k_0p8: ldo1 {
+ regulator-name = "vreg_l1k_0p8";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2k_0p7: ldo2 {
+ regulator-name = "vreg_l2k_0p7";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3k_1p2: ldo3 {
+ regulator-name = "vreg_l3k_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4k_1p0: ldo4 {
+ regulator-name = "vreg_l4k_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5k_0p7: ldo5 {
+ regulator-name = "vreg_l5k_0p7";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6k_1p7: ldo6 {
+ regulator-name = "vreg_l6k_1p7";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7k_0p7: ldo7 {
+ regulator-name = "vreg_l7k_0p7";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <848000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+
+ qcom,pmic-id = "M_E1";
+
+ vreg_l1m_1p0: ldo1 {
+ regulator-name = "vreg_l1m_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m_1p0: ldo2 {
+ regulator-name = "vreg_l2m_1p0";
+ regulator-min-microvolt = <1096000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m_2p8: ldo3 {
+ regulator-name = "vreg_l3m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m_2p2: ldo4 {
+ regulator-name = "vreg_l4m_2p2";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m_2p8: ldo6 {
+ regulator-name = "vreg_l6m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p8: ldo7 {
+ regulator-name = "vreg_l7m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-8 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+
+ qcom,pmic-id = "N_E1";
+
+ vreg_l1n_1p1: ldo1 {
+ regulator-name = "vreg_l1n_1p1";
+ regulator-min-microvolt = <1096000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n_1p2: ldo2 {
+ regulator-name = "vreg_l2n_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n_1p8: ldo3 {
+ regulator-name = "vreg_l3n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n_1p8: ldo4 {
+ regulator-name = "vreg_l4n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n_2p8: ldo5 {
+ regulator-name = "vreg_l5n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n_2p8: ldo6 {
+ regulator-name = "vreg_l6n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n_3p3: ldo7 {
+ regulator-name = "vreg_l7n_3p3";
+ regulator-min-microvolt = <3304000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&pmh0110_d_e0 {
+ status = "okay";
+};
+
+&pmh0110_f_e0 {
+ status = "okay";
+};
+
+&pmh0110_g_e0 {
+ status = "okay";
+};
+
+&pmh0110_i_e0 {
+ status = "okay";
+};
+
+&spmi_bus1 {
+ pmd8028: pmic@4 {
+ compatible = "qcom,pmd8028", "qcom,spmi-pmic";
+ reg = <0x4 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmd8028_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmd8028_gpios: gpio@8800 {
+ compatible = "qcom,pmd8028-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmd8028_gpios 0 0 4>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmih0108: pmic@7 {
+ compatible = "qcom,pmih0108", "qcom,spmi-pmic";
+ reg = <0x7 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmih0108_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmih0108_gpios: gpio@8800 {
+ compatible = "qcom,pmih0108-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmih0108_gpios 0 0 18>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pmih0108_eusb2_repeater: phy@fd00 {
+ compatible = "qcom,pm8550b-eusb2-repeater";
+ reg = <0xfd00>;
+ #phy-cells = <0>;
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+ };
+ };
+
+ pmr735d: pmic@a {
+ compatible = "qcom,pmr735d", "qcom,spmi-pmic";
+ reg = <0xa SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmr735d_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmr735d_gpios: gpio@8800 {
+ compatible = "qcom,pmr735d-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmr735d_gpios 0 0 2>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pm8010_m: pmic@c {
+ compatible = "qcom,pm8010", "qcom,spmi-pmic";
+ reg = <0xc SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8010_m_temp_alarm: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+ };
+
+ pm8010_n: pmic@d {
+ compatible = "qcom,pm8010", "qcom,spmi-pmic";
+ reg = <0xd SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8010_n_temp_alarm: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+ };
+};
+
+&pmh0101_flash {
+ status = "okay";
+
+ led-0 {
+ function = LED_FUNCTION_FLASH;
+ function-enumerator = <0>;
+ color = <LED_COLOR_ID_YELLOW>;
+ led-sources = <1>, <4>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <2000000>;
+ flash-max-timeout-us = <1280000>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_FLASH;
+ function-enumerator = <1>;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <2>, <3>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <2000000>;
+ flash-max-timeout-us = <1280000>;
+ };
+};
+
+&pmh0101_pwm {
+ status = "okay";
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_STATUS;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@3 {
+ reg = <3>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+};
+
+&tlmm {
+ key_vol_up_default: key-vol-up-default-state {
+ pins = "gpio101";
+ function = "gpio";
+ output-disable;
+ bias-pull-up;
+ };
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/kaanapali/adsp.mbn",
+ "qcom/kaanapali/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/kaanapali/cdsp.mbn",
+ "qcom/kaanapali/cdsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/kaanapali/modem.mbn",
+ "qcom/kaanapali/modem_dtb.mbn";
+
+ /* Modem crashes after some time for OEMPD load failure */
+ status = "fail";
+};
+
+&remoteproc_soccp {
+ firmware-name = "qcom/kaanapali/soccp.mbn",
+ "qcom/kaanapali/soccp_dtb.mbn";
+};
+
+&sdhc_2 {
+ cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vreg_l9b_2p9>;
+ vqmmc-supply = <&vreg_l8b_1p8>;
+
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+
+ pinctrl-0 = <&sdc2_default>;
+ pinctrl-1 = <&sdc2_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */
+ <74 1>, /* eSE */
+ <119 2>, /* SoCCP */
+ <144 4>; /* CXM UART */
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 217 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1200000>;
+ vccq-supply = <&vreg_l4d_1p2>;
+ vccq-max-microamp = <1200000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l4g_0p9>;
+ vdda-pll-supply = <&vreg_l1d_1p2>;
+
+ status = "okay";
+};
+
+&usb_1 {
+ dr_mode = "peripheral";
+
+ status = "okay";
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l4f_0p8>;
+ vdda12-supply = <&vreg_l1d_1p2>;
+
+ phys = <&pmih0108_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ vdda-phy-supply = <&vreg_l1d_1p2>;
+ vdda-pll-supply = <&vreg_l4f_0p8>;
+
+ status = "okay";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* Re: [PATCH 16/20] arm64: dts: qcom: kaanapali: Add QRD board
2025-09-25 0:17 ` [PATCH 16/20] arm64: dts: qcom: kaanapali: Add QRD board Jingyi Wang
@ 2025-09-25 2:15 ` Dmitry Baryshkov
2025-09-29 3:29 ` Jingyi Wang
0 siblings, 1 reply; 135+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 2:15 UTC (permalink / raw)
To: Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On Wed, Sep 24, 2025 at 05:17:33PM -0700, Jingyi Wang wrote:
> Add support for Qualcomm Kaanapali QRD board which enables booting to
> shell with uart console, UFS, PMIC peripherals, bus, SDHCI, remoteprocs,
> USB, PCIE, WLAN and Bluetooth.
>
> Written with help from Jishnu Prakash (added rpmhpd nodes), Nitin Rawat
> (added ufs), Jyothi Kumar Seerapu(added bus), Ronak Raheja (added USB),
> Manish Pandey(added SDHCI), Jishnu Prakash(added PMIC), Qiang Yu
> (added PCIE), Yijie Yang(Added WLAN) and Zijun Hu(Added Bluetooth).
>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 1212 ++++++++++++++++++++++++++++
> 2 files changed, 1213 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 7edfa5fa00fc..da9ef255073c 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb
> dtb-$(CONFIG_ARCH_QCOM) += kaanapali-mtp.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += kaanapali-qrd.dtb
> dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb
>
> lemans-evk-camera-csi1-imx577-dtbs := lemans-evk.dtb lemans-evk-camera-csi1-imx577.dtbo
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
> new file mode 100644
> index 000000000000..5900812c74a5
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
> @@ -0,0 +1,1212 @@
> +// SPDX-License-Identifier: BSD-3-Clause
Please sort the nodes in the file. You got two entries for tlmm, for
example.
> +&usb_1 {
> + dr_mode = "peripheral";
Is it?
> +
> + status = "okay";
> +};
> +
> +&usb_1_hsphy {
> + vdd-supply = <&vreg_l4f_0p8>;
> + vdda12-supply = <&vreg_l1d_1p2>;
> +
> + phys = <&pmih0108_eusb2_repeater>;
> +
> + status = "okay";
> +};
> +
> +&usb_dp_qmpphy {
> + vdda-phy-supply = <&vreg_l1d_1p2>;
> + vdda-pll-supply = <&vreg_l4f_0p8>;
> +
> + status = "okay";
> +};
>
> --
> 2.25.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 16/20] arm64: dts: qcom: kaanapali: Add QRD board
2025-09-25 2:15 ` Dmitry Baryshkov
@ 2025-09-29 3:29 ` Jingyi Wang
0 siblings, 0 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-09-29 3:29 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On 9/25/2025 10:15 AM, Dmitry Baryshkov wrote:
> On Wed, Sep 24, 2025 at 05:17:33PM -0700, Jingyi Wang wrote:
>> Add support for Qualcomm Kaanapali QRD board which enables booting to
>> shell with uart console, UFS, PMIC peripherals, bus, SDHCI, remoteprocs,
>> USB, PCIE, WLAN and Bluetooth.
>>
>> Written with help from Jishnu Prakash (added rpmhpd nodes), Nitin Rawat
>> (added ufs), Jyothi Kumar Seerapu(added bus), Ronak Raheja (added USB),
>> Manish Pandey(added SDHCI), Jishnu Prakash(added PMIC), Qiang Yu
>> (added PCIE), Yijie Yang(Added WLAN) and Zijun Hu(Added Bluetooth).
>>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 1212 ++++++++++++++++++++++++++++
>> 2 files changed, 1213 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 7edfa5fa00fc..da9ef255073c 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += kaanapali-mtp.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += kaanapali-qrd.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb
>>
>> lemans-evk-camera-csi1-imx577-dtbs := lemans-evk.dtb lemans-evk-camera-csi1-imx577.dtbo
>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
>> new file mode 100644
>> index 000000000000..5900812c74a5
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
>> @@ -0,0 +1,1212 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>
> Please sort the nodes in the file. You got two entries for tlmm, for
> example.
>
will fix
Thanks,
Jingyi
>> +&usb_1 {
>> + dr_mode = "peripheral";
>
> Is it?
>
>> +
>> + status = "okay";
>> +};
>> +
>> +&usb_1_hsphy {
>> + vdd-supply = <&vreg_l4f_0p8>;
>> + vdda12-supply = <&vreg_l1d_1p2>;
>> +
>> + phys = <&pmih0108_eusb2_repeater>;
>> +
>> + status = "okay";
>> +};
>> +
>> +&usb_dp_qmpphy {
>> + vdda-phy-supply = <&vreg_l1d_1p2>;
>> + vdda-pll-supply = <&vreg_l4f_0p8>;
>> +
>> + status = "okay";
>> +};
>>
>> --
>> 2.25.1
>>
>
^ permalink raw reply [flat|nested] 135+ messages in thread
* [PATCH 17/20] arm64: dts: qcom: kaanapali: Add support for audio
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (15 preceding siblings ...)
2025-09-25 0:17 ` [PATCH 16/20] arm64: dts: qcom: kaanapali: Add QRD board Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-09-25 12:30 ` Konrad Dybcio
2025-09-25 0:17 ` [PATCH 18/20] arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC) Jingyi Wang
` (5 subsequent siblings)
22 siblings, 1 reply; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang, Prasad Kumpatla
From: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
Introduce audio support for Kaanapali SoC by adding LPASS macro codecs,
TLMM pin controller and SoundWire controller with similar hardware
implementation to SM8750 platform. Also add GPR (Generic Pack Router) node
along with support for APM (Audio Process Manager) and PRM
(Proxy Resource Manager) audio services.
Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 396 ++++++++++++++++++++++++++++++++
1 file changed, 396 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 182044f61142..6aa8dedbb196 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -17,6 +17,8 @@
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/soc/qcom,gpr.h>
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
/ {
interrupt-parent = <&intc>;
@@ -2839,6 +2841,400 @@ compute-cb@7 {
dma-coherent;
};
};
+
+ gpr {
+ compatible = "qcom,gpr";
+ qcom,glink-channels = "adsp_apps";
+ qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+ qcom,intents = <512 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ q6apm: service@1 {
+ compatible = "qcom,q6apm";
+ reg = <GPR_APM_MODULE_IID>;
+ #sound-dai-cells = <0>;
+ qcom,protection-domain = "avs/audio",
+ "msm/adsp/audio_pd";
+
+ q6apmbedai: bedais {
+ compatible = "qcom,q6apm-lpass-dais";
+ #sound-dai-cells = <1>;
+ };
+
+ q6apmdai: dais {
+ compatible = "qcom,q6apm-dais";
+ iommus = <&apps_smmu 0x1001 0x80>,
+ <&apps_smmu 0x1041 0x20>;
+ };
+ };
+
+ q6prm: service@2 {
+ compatible = "qcom,q6prm";
+ reg = <GPR_PRM_MODULE_IID>;
+ qcom,protection-domain = "avs/audio",
+ "msm/adsp/audio_pd";
+
+ q6prmcc: clock-controller {
+ compatible = "qcom,q6prm-lpass-clocks";
+ #clock-cells = <2>;
+ };
+ };
+ };
+ };
+ };
+
+ lpass_wsa2macro: codec@6aa0000 {
+ compatible = "qcom,kaanapali-lpass-wsa-macro",
+ "qcom,sm8550-lpass-wsa-macro";
+ reg = <0x0 0x06aa0000 0x0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK
+ LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&lpass_vamacro>;
+ clock-names = "mclk",
+ "macro",
+ "dcodec",
+ "fsgen";
+
+ #clock-cells = <0>;
+ clock-output-names = "wsa2-mclk";
+ #sound-dai-cells = <1>;
+ };
+
+ swr3: soundwire@6ab0000 {
+ compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0";
+ reg = <0 0x06ab0000 0 0x10000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&lpass_wsa2macro>;
+ clock-names = "iface";
+ label = "WSA2";
+
+ pinctrl-0 = <&wsa2_swr_active>;
+ pinctrl-names = "default";
+
+ qcom,din-ports = <4>;
+ qcom,dout-ports = <9>;
+
+ qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f
+ 0x18f 0xff 0xff 0x0f 0x0f 0xff
+ 0x31f>;
+ qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00
+ 0xff 0xff 0x06 0x0d 0xff 0x00>;
+ qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08
+ 0xff 0xff 0xff 0xff 0xff 0x0f>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08
+ 0xff 0xff 0xff 0xff 0xff 0x0f>;
+ qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08
+ 0xff 0xff 0xff 0xff 0xff 0x18>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00
+ 0x00 0x00 0x01 0x01 0x00 0x00>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
+
+ lpass_rxmacro: codec@6ac0000 {
+ compatible = "qcom,kaanapali-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
+ reg = <0x0 0x06ac0000 0x0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK
+ LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&lpass_vamacro>;
+ clock-names = "mclk",
+ "macro",
+ "dcodec",
+ "fsgen";
+
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ #sound-dai-cells = <1>;
+ };
+
+ swr1: soundwire@6ad0000 {
+ compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0";
+ reg = <0 0x06ad0000 0 0x10000>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&lpass_rxmacro>;
+ clock-names = "iface";
+ label = "RX";
+
+ pinctrl-0 = <&rx_swr_active>;
+ pinctrl-names = "default";
+
+ qcom,din-ports = <1>;
+ qcom,dout-ports = <11>;
+
+ qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f
+ 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff
+ 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff
+ 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff
+ 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff
+ 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff
+ 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff
+ 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff
+ 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff
+ 0xff 0xff 0xff 0xff 0xff>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
+
+ lpass_txmacro: codec@6ae0000 {
+ compatible = "qcom,kaanapali-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
+ reg = <0x0 0x06ae0000 0x0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&lpass_vamacro>;
+ clock-names = "mclk",
+ "macro",
+ "dcodec",
+ "fsgen";
+
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ #sound-dai-cells = <1>;
+ };
+
+ lpass_wsamacro: codec@6b00000 {
+ compatible = "qcom,kaanapali-lpass-wsa-macro",
+ "qcom,sm8550-lpass-wsa-macro";
+ reg = <0x0 0x06b00000 0x0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK
+ LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&lpass_vamacro>;
+ clock-names = "mclk",
+ "macro",
+ "dcodec",
+ "fsgen";
+
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ #sound-dai-cells = <1>;
+ };
+
+ swr0: soundwire@6b10000 {
+ compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0";
+ reg = <0 0x06b10000 0 0x10000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&lpass_wsamacro>;
+ clock-names = "iface";
+ label = "WSA";
+
+ pinctrl-0 = <&wsa_swr_active>;
+ pinctrl-names = "default";
+
+ qcom,din-ports = <4>;
+ qcom,dout-ports = <9>;
+
+ qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f
+ 0x18f 0xff 0xff 0x0f 0x0f 0xff
+ 0x31f>;
+ qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00
+ 0xff 0xff 0x06 0x0d 0xff 0x00>;
+ qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08
+ 0xff 0xff 0xff 0xff 0xff 0x0f>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08
+ 0xff 0xff 0xff 0xff 0xff 0x0f>;
+ qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08
+ 0xff 0xff 0xff 0xff 0xff 0x18>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00
+ 0x00 0x00 0x01 0x01 0x00 0x00>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
+
+ swr2: soundwire@7630000 {
+ compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0";
+ reg = <0 0x07630000 0 0x10000>;
+ interrupts-extended = <&intc GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 40 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "core", "wakeup";
+ clocks = <&lpass_txmacro>;
+ clock-names = "iface";
+ label = "TX";
+
+ pinctrl-0 = <&tx_swr_active>;
+ pinctrl-names = "default";
+
+ qcom,din-ports = <4>;
+ qcom,dout-ports = <0>;
+ qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
+ qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
+
+ lpass_vamacro: codec@7660000 {
+ compatible = "qcom,kaanapali-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
+ reg = <0 0x07660000 0 0x2000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "mclk", "macro", "dcodec";
+
+ #clock-cells = <0>;
+ clock-output-names = "fsgen";
+ #sound-dai-cells = <1>;
+ };
+
+ lpass_tlmm: pinctrl@7760000 {
+ compatible = "qcom,sm8750-lpass-lpi-pinctrl",
+ "qcom,sm8650-lpass-lpi-pinctrl";
+ reg = <0 0x07760000 0 0x20000>;
+
+ clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "audio";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 23>;
+
+ tx_swr_active: tx-swr-active-state {
+ clk-pins {
+ pins = "gpio0";
+ function = "swr_tx_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio1", "gpio2", "gpio14";
+ function = "swr_tx_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_active: rx-swr-active-state {
+ clk-pins {
+ pins = "gpio3";
+ function = "swr_rx_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio4", "gpio5";
+ function = "swr_rx_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ dmic01_default: dmic01-default-state {
+ clk-pins {
+ pins = "gpio6";
+ function = "dmic1_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ data-pins {
+ pins = "gpio7";
+ function = "dmic1_data";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ dmic23_default: dmic23-default-state {
+ clk-pins {
+ pins = "gpio8";
+ function = "dmic2_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ data-pins {
+ pins = "gpio9";
+ function = "dmic2_data";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ wsa_swr_active: wsa-swr-active-state {
+ clk-pins {
+ pins = "gpio10";
+ function = "wsa_swr_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio11";
+ function = "wsa_swr_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ wsa2_swr_active: wsa2-swr-active-state {
+ clk-pins {
+ pins = "gpio15";
+ function = "wsa2_swr_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio16";
+ function = "wsa2_swr_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* Re: [PATCH 17/20] arm64: dts: qcom: kaanapali: Add support for audio
2025-09-25 0:17 ` [PATCH 17/20] arm64: dts: qcom: kaanapali: Add support for audio Jingyi Wang
@ 2025-09-25 12:30 ` Konrad Dybcio
0 siblings, 0 replies; 135+ messages in thread
From: Konrad Dybcio @ 2025-09-25 12:30 UTC (permalink / raw)
To: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Prasad Kumpatla
On 9/25/25 2:17 AM, Jingyi Wang wrote:
> From: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>
> Introduce audio support for Kaanapali SoC by adding LPASS macro codecs,
> TLMM pin controller and SoundWire controller with similar hardware
> implementation to SM8750 platform. Also add GPR (Generic Pack Router) node
> along with support for APM (Audio Process Manager) and PRM
> (Proxy Resource Manager) audio services.
>
> Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread
* [PATCH 18/20] arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC)
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (16 preceding siblings ...)
2025-09-25 0:17 ` [PATCH 17/20] arm64: dts: qcom: kaanapali: Add support for audio Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-09-25 12:30 ` Konrad Dybcio
2025-09-25 13:26 ` Krzysztof Kozlowski
2025-09-25 0:17 ` [PATCH 19/20] arm64: dts: qcom: kaanapali: Add support for camss Jingyi Wang
` (4 subsequent siblings)
22 siblings, 2 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang, Prasad Kumpatla
From: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
Add support for audio on the Kaanapali MTP platform by introducing device
tree nodes for WSA8845 smart speaker amplifier for playback, DMIC
microphone for capture, and sound card routing. The WCD9395 codec is add
to supply MIC-BIAS, for enabling onboard microphone capture.
Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 226 +++++++++++++++++++++++++++++
1 file changed, 226 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
index 8d1b3278389e..759414b87146 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
@@ -84,6 +84,87 @@ key-volume-up {
};
};
+ sound {
+ compatible = "qcom,kaanapali-sndcard", "qcom,sm8450-sndcard";
+ model = "Kaanapali-MTP";
+
+ audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC2", "MIC BIAS2",
+ "VA DMIC0", "MIC BIAS1",
+ "VA DMIC1", "MIC BIAS1",
+ "VA DMIC2", "MIC BIAS3",
+ "VA DMIC3", "MIC BIAS3",
+ "TX SWR_INPUT1", "ADC2_OUTPUT";
+
+ wcd-playback-dai-link {
+ link-name = "WCD Playback";
+
+ codec {
+ sound-dai = <&wcd939x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wcd-capture-dai-link {
+ link-name = "WCD Capture";
+
+ codec {
+ sound-dai = <&wcd939x 1>, <&swr2 0>, <&lpass_txmacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wsa-dai-link {
+ link-name = "WSA Playback";
+
+ codec {
+ sound-dai = <&north_spkr>, <&south_spkr>, <&swr0 0>,
+ <&lpass_wsamacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ va-dai-link {
+ link-name = "VA Capture";
+
+ codec {
+ sound-dai = <&lpass_vamacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+ };
+
thermal-zones {
pmh0101-thermal {
polling-delay-passive = <100>;
@@ -304,6 +385,34 @@ trip1 {
};
};
+ wcd939x: audio-codec {
+ compatible = "qcom,wcd9395-codec", "qcom,wcd9390-codec";
+
+ pinctrl-0 = <&wcd_default>;
+ pinctrl-names = "default";
+
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+ qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000
+ 500000 500000 500000 500000>;
+ qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+ qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+ qcom,rx-device = <&wcd_rx>;
+ qcom,tx-device = <&wcd_tx>;
+
+ reset-gpios = <&tlmm 161 GPIO_ACTIVE_LOW>;
+
+ vdd-buck-supply = <&vreg_l15b_1p8>;
+ vdd-rxtx-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l15b_1p8>;
+ vdd-mic-bias-supply = <&vreg_bob1>;
+ vdd-px-supply = <&vreg_l1g_1p2>;
+
+ #sound-dai-cells = <1>;
+ };
+
wcn7850-pmu {
compatible = "qcom,wcn7850-pmu";
@@ -987,6 +1096,14 @@ vreg_l7n_3p3: ldo7 {
};
};
+&lpass_vamacro {
+ pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
+ pinctrl-names = "default";
+
+ vdd-micb-supply = <&vreg_l10b_1p8>;
+ qcom,dmic-sample-rate = <4800000>;
+};
+
&pmh0110_d_e0 {
status = "okay";
};
@@ -1164,6 +1281,94 @@ led@3 {
};
};
+&swr0 {
+ status = "okay";
+
+ /* WSA8845, Speaker North */
+ north_spkr: speaker@0,0 {
+ compatible = "sdw20217020400";
+ reg = <0 0>;
+ pinctrl-0 = <&spkr_0_sd_n_active>;
+ pinctrl-names = "default";
+ powerdown-gpios = <&tlmm 76 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrLeft";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l2i_1p2>;
+
+ /*
+ * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L)
+ * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP)
+ * WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST)
+ * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
+ * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI)
+ * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
+ */
+ qcom,port-mapping = <1 2 3 7 10 13>;
+ };
+
+ /* WSA8845, Speaker South */
+ south_spkr: speaker@0,1 {
+ compatible = "sdw20217020400";
+ reg = <0 1>;
+ pinctrl-0 = <&spkr_1_sd_n_active>;
+ pinctrl-names = "default";
+ powerdown-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrRight";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l2i_1p2>;
+
+ /*
+ * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R)
+ * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP)
+ * WSA8845 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST)
+ * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
+ * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI)
+ * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
+ */
+ qcom,port-mapping = <4 5 6 7 11 13>;
+ };
+};
+
+&swr1 {
+ status = "okay";
+
+ /* WCD9395 RX */
+ wcd_rx: codec@0,4 {
+ compatible = "sdw20217010e00";
+ reg = <0 4>;
+
+ /*
+ * WCD9395 RX Port 1 (HPH_L/R) <=> SWR1 Port 1 (HPH_L/R)
+ * WCD9395 RX Port 2 (CLSH) <=> SWR1 Port 2 (CLSH)
+ * WCD9395 RX Port 3 (COMP_L/R) <=> SWR1 Port 3 (COMP_L/R)
+ * WCD9395 RX Port 4 (LO) <=> SWR1 Port 4 (LO)
+ * WCD9395 RX Port 5 (DSD_L/R) <=> SWR1 Port 5 (DSD_L/R)
+ * WCD9395 RX Port 6 (HIFI_PCM_L/R) <=> SWR1 Port 9 (HIFI_PCM_L/R)
+ */
+ qcom,rx-port-mapping = <1 2 3 4 5 9>;
+ };
+};
+
+&swr2 {
+ status = "okay";
+
+ /* WCD9395 TX */
+ wcd_tx: codec@0,3 {
+ compatible = "sdw20217010e00";
+ reg = <0 3>;
+
+ /*
+ * WCD9395 TX Port 1 (ADC1,2,3,4) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3)
+ * WCD9395 TX Port 2 (ADC3,4 & DMIC0,1) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3)
+ * WCD9395 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 (TX SWR_INPUT 4,5,6,7)
+ * WCD9395 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 (TX SWR_INPUT 8,9,10,11)
+ */
+ qcom,tx-port-mapping = <2 2 3 4>;
+ };
+};
+
&tlmm {
wlan_en: wlan-en-state {
pins = "gpio16";
@@ -1178,6 +1383,20 @@ sw_ctrl_default: sw-ctrl-default-state {
bias-pull-down;
};
+ spkr_0_sd_n_active: spkr-0-sd-n-active-state {
+ pins = "gpio76";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ spkr_1_sd_n_active: spkr-1-sd-n-active-state {
+ pins = "gpio77";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
key_vol_up_default: key-vol-up-default-state {
pins = "gpio101";
function = "gpio";
@@ -1207,6 +1426,13 @@ wake-n-pins {
bias-pull-up;
};
};
+
+ wcd_default: wcd-reset-n-active-state {
+ pins = "gpio161";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
};
&pcie0 {
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* Re: [PATCH 18/20] arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC)
2025-09-25 0:17 ` [PATCH 18/20] arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC) Jingyi Wang
@ 2025-09-25 12:30 ` Konrad Dybcio
2025-09-25 13:26 ` Krzysztof Kozlowski
1 sibling, 0 replies; 135+ messages in thread
From: Konrad Dybcio @ 2025-09-25 12:30 UTC (permalink / raw)
To: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Prasad Kumpatla
On 9/25/25 2:17 AM, Jingyi Wang wrote:
> From: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>
> Add support for audio on the Kaanapali MTP platform by introducing device
> tree nodes for WSA8845 smart speaker amplifier for playback, DMIC
> microphone for capture, and sound card routing. The WCD9395 codec is add
> to supply MIC-BIAS, for enabling onboard microphone capture.
>
> Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 18/20] arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC)
2025-09-25 0:17 ` [PATCH 18/20] arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC) Jingyi Wang
2025-09-25 12:30 ` Konrad Dybcio
@ 2025-09-25 13:26 ` Krzysztof Kozlowski
2025-09-30 12:06 ` Prasad Kumpatla
1 sibling, 1 reply; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-25 13:26 UTC (permalink / raw)
To: Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Prasad Kumpatla
On Thu, 25 Sept 2025 at 09:18, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
>
> From: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>
> Add support for audio on the Kaanapali MTP platform by introducing device
> tree nodes for WSA8845 smart speaker amplifier for playback, DMIC
> microphone for capture, and sound card routing. The WCD9395 codec is add
> to supply MIC-BIAS, for enabling onboard microphone capture.
>
> Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 226 +++++++++++++++++++++++++++++
> 1 file changed, 226 insertions(+)
>
Audio is not a separate feature from USB. It's simply incomplete
picture which is wrong for case of submitting everything at once.
Either you release early, release often (which I asked you many
times), or you submit complete work.
You don't understand how your own SoC is organized and create fake
split and inflated patch count just, as someone admitted, to have LWN
stats.
This work is incomplete, so please start organizing patches per
logical features, not per your patch count and company KPI
.
NAK, incomplete patch and previously communicated as non working
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 18/20] arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC)
2025-09-25 13:26 ` Krzysztof Kozlowski
@ 2025-09-30 12:06 ` Prasad Kumpatla
2025-10-06 8:48 ` Krzysztof Kozlowski
0 siblings, 1 reply; 135+ messages in thread
From: Prasad Kumpatla @ 2025-09-30 12:06 UTC (permalink / raw)
To: Krzysztof Kozlowski, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On 9/25/2025 6:56 PM, Krzysztof Kozlowski wrote:
> On Thu, 25 Sept 2025 at 09:18, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
>> From: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>>
>> Add support for audio on the Kaanapali MTP platform by introducing device
>> tree nodes for WSA8845 smart speaker amplifier for playback, DMIC
>> microphone for capture, and sound card routing. The WCD9395 codec is add
>> to supply MIC-BIAS, for enabling onboard microphone capture.
>>
>> Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 226 +++++++++++++++++++++++++++++
>> 1 file changed, 226 insertions(+)
>>
> Audio is not a separate feature from USB.
I didn't understand this, Could you please help me to provide more
context on it?
Is this regarding Audio over Type-c?
> It's simply incomplete
> picture which is wrong for case of submitting everything at once.
> Either you release early, release often (which I asked you many
> times), or you submit complete work.
These patches enable usecase for Speaker playback and On-board-Mic
Capture. Do you consider is there is anything need to do to make it
complete ?
>
> You don't understand how your own SoC is organized and create fake
> split and inflated patch count just, as someone admitted, to have LWN
> stats.
>
> This work is incomplete, so please start organizing patches per
> logical features, not per your patch count and company KPI
> .
> NAK, incomplete patch and previously communicated as non working
Earlier there is an issue with SWR-TX interrupt configuration so did not
work. As i fixed/configured
interrupt, it worked and validated on Kaanapali-MTP.
Thanks,
Prasad
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 18/20] arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC)
2025-09-30 12:06 ` Prasad Kumpatla
@ 2025-10-06 8:48 ` Krzysztof Kozlowski
2025-10-08 10:20 ` Konrad Dybcio
0 siblings, 1 reply; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-06 8:48 UTC (permalink / raw)
To: Prasad Kumpatla, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On 30/09/2025 21:06, Prasad Kumpatla wrote:
>
> On 9/25/2025 6:56 PM, Krzysztof Kozlowski wrote:
>> On Thu, 25 Sept 2025 at 09:18, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
>>> From: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>>>
>>> Add support for audio on the Kaanapali MTP platform by introducing device
>>> tree nodes for WSA8845 smart speaker amplifier for playback, DMIC
>>> microphone for capture, and sound card routing. The WCD9395 codec is add
>>> to supply MIC-BIAS, for enabling onboard microphone capture.
>>>
>>> Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 226 +++++++++++++++++++++++++++++
>>> 1 file changed, 226 insertions(+)
>>>
>> Audio is not a separate feature from USB.
>
> I didn't understand this, Could you please help me to provide more
> context on it?
> Is this regarding Audio over Type-c?
USB depends on ADSP, so your split of patches into separate audio commit
is just incorrect.
>
>> It's simply incomplete
>> picture which is wrong for case of submitting everything at once.
>> Either you release early, release often (which I asked you many
>> times), or you submit complete work.
And here I explained why.
>
> These patches enable usecase for Speaker playback and On-board-Mic
> Capture. Do you consider is there is anything need to do to make it
> complete ?
Yes, please squash patches.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 18/20] arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC)
2025-10-06 8:48 ` Krzysztof Kozlowski
@ 2025-10-08 10:20 ` Konrad Dybcio
2025-10-08 10:51 ` Krzysztof Kozlowski
0 siblings, 1 reply; 135+ messages in thread
From: Konrad Dybcio @ 2025-10-08 10:20 UTC (permalink / raw)
To: Krzysztof Kozlowski, Prasad Kumpatla, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On 10/6/25 10:48 AM, Krzysztof Kozlowski wrote:
> On 30/09/2025 21:06, Prasad Kumpatla wrote:
>>
>> On 9/25/2025 6:56 PM, Krzysztof Kozlowski wrote:
>>> On Thu, 25 Sept 2025 at 09:18, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
>>>> From: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>>>>
>>>> Add support for audio on the Kaanapali MTP platform by introducing device
>>>> tree nodes for WSA8845 smart speaker amplifier for playback, DMIC
>>>> microphone for capture, and sound card routing. The WCD9395 codec is add
>>>> to supply MIC-BIAS, for enabling onboard microphone capture.
>>>>
>>>> Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 226 +++++++++++++++++++++++++++++
>>>> 1 file changed, 226 insertions(+)
>>>>
>>> Audio is not a separate feature from USB.
>>
>> I didn't understand this, Could you please help me to provide more
>> context on it?
>> Is this regarding Audio over Type-c?
>
> USB depends on ADSP, so your split of patches into separate audio commit
> is just incorrect.
No, this is no longer the case on Kaanapali.
PMIC_GLINK is now served by the SoCCP rproc
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 18/20] arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC)
2025-10-08 10:20 ` Konrad Dybcio
@ 2025-10-08 10:51 ` Krzysztof Kozlowski
2025-10-08 11:30 ` Konrad Dybcio
0 siblings, 1 reply; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-08 10:51 UTC (permalink / raw)
To: Konrad Dybcio, Prasad Kumpatla, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On 08/10/2025 19:20, Konrad Dybcio wrote:
> On 10/6/25 10:48 AM, Krzysztof Kozlowski wrote:
>> On 30/09/2025 21:06, Prasad Kumpatla wrote:
>>>
>>> On 9/25/2025 6:56 PM, Krzysztof Kozlowski wrote:
>>>> On Thu, 25 Sept 2025 at 09:18, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
>>>>> From: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>>>>>
>>>>> Add support for audio on the Kaanapali MTP platform by introducing device
>>>>> tree nodes for WSA8845 smart speaker amplifier for playback, DMIC
>>>>> microphone for capture, and sound card routing. The WCD9395 codec is add
>>>>> to supply MIC-BIAS, for enabling onboard microphone capture.
>>>>>
>>>>> Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>>>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>>>>> ---
>>>>> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 226 +++++++++++++++++++++++++++++
>>>>> 1 file changed, 226 insertions(+)
>>>>>
>>>> Audio is not a separate feature from USB.
>>>
>>> I didn't understand this, Could you please help me to provide more
>>> context on it?
>>> Is this regarding Audio over Type-c?
>>
>> USB depends on ADSP, so your split of patches into separate audio commit
>> is just incorrect.
>
> No, this is no longer the case on Kaanapali.
>
> PMIC_GLINK is now served by the SoCCP rproc
Hm, ok.... so there is no WCD93xx USB mux anymore?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 18/20] arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC)
2025-10-08 10:51 ` Krzysztof Kozlowski
@ 2025-10-08 11:30 ` Konrad Dybcio
2025-10-08 23:50 ` Krzysztof Kozlowski
0 siblings, 1 reply; 135+ messages in thread
From: Konrad Dybcio @ 2025-10-08 11:30 UTC (permalink / raw)
To: Krzysztof Kozlowski, Prasad Kumpatla, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On 10/8/25 12:51 PM, Krzysztof Kozlowski wrote:
> On 08/10/2025 19:20, Konrad Dybcio wrote:
>> On 10/6/25 10:48 AM, Krzysztof Kozlowski wrote:
>>> On 30/09/2025 21:06, Prasad Kumpatla wrote:
>>>>
>>>> On 9/25/2025 6:56 PM, Krzysztof Kozlowski wrote:
>>>>> On Thu, 25 Sept 2025 at 09:18, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
>>>>>> From: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>>>>>>
>>>>>> Add support for audio on the Kaanapali MTP platform by introducing device
>>>>>> tree nodes for WSA8845 smart speaker amplifier for playback, DMIC
>>>>>> microphone for capture, and sound card routing. The WCD9395 codec is add
>>>>>> to supply MIC-BIAS, for enabling onboard microphone capture.
>>>>>>
>>>>>> Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>>>>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>>>>>> ---
>>>>>> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 226 +++++++++++++++++++++++++++++
>>>>>> 1 file changed, 226 insertions(+)
>>>>>>
>>>>> Audio is not a separate feature from USB.
>>>>
>>>> I didn't understand this, Could you please help me to provide more
>>>> context on it?
>>>> Is this regarding Audio over Type-c?
>>>
>>> USB depends on ADSP, so your split of patches into separate audio commit
>>> is just incorrect.
>>
>> No, this is no longer the case on Kaanapali.
>>
>> PMIC_GLINK is now served by the SoCCP rproc
>
> Hm, ok.... so there is no WCD93xx USB mux anymore?
I see there's a WCD9395 onboard which has that hw block
I'll try to find some schematics to confirm..
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 18/20] arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC)
2025-10-08 11:30 ` Konrad Dybcio
@ 2025-10-08 23:50 ` Krzysztof Kozlowski
2025-10-27 9:39 ` Konrad Dybcio
0 siblings, 1 reply; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-08 23:50 UTC (permalink / raw)
To: Konrad Dybcio, Prasad Kumpatla, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On 08/10/2025 20:30, Konrad Dybcio wrote:
> On 10/8/25 12:51 PM, Krzysztof Kozlowski wrote:
>> On 08/10/2025 19:20, Konrad Dybcio wrote:
>>> On 10/6/25 10:48 AM, Krzysztof Kozlowski wrote:
>>>> On 30/09/2025 21:06, Prasad Kumpatla wrote:
>>>>>
>>>>> On 9/25/2025 6:56 PM, Krzysztof Kozlowski wrote:
>>>>>> On Thu, 25 Sept 2025 at 09:18, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
>>>>>>> From: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>>>>>>>
>>>>>>> Add support for audio on the Kaanapali MTP platform by introducing device
>>>>>>> tree nodes for WSA8845 smart speaker amplifier for playback, DMIC
>>>>>>> microphone for capture, and sound card routing. The WCD9395 codec is add
>>>>>>> to supply MIC-BIAS, for enabling onboard microphone capture.
>>>>>>>
>>>>>>> Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>>>>>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>>>>>>> ---
>>>>>>> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 226 +++++++++++++++++++++++++++++
>>>>>>> 1 file changed, 226 insertions(+)
>>>>>>>
>>>>>> Audio is not a separate feature from USB.
>>>>>
>>>>> I didn't understand this, Could you please help me to provide more
>>>>> context on it?
>>>>> Is this regarding Audio over Type-c?
>>>>
>>>> USB depends on ADSP, so your split of patches into separate audio commit
>>>> is just incorrect.
>>>
>>> No, this is no longer the case on Kaanapali.
>>>
>>> PMIC_GLINK is now served by the SoCCP rproc
>>
>> Hm, ok.... so there is no WCD93xx USB mux anymore?
>
> I see there's a WCD9395 onboard which has that hw block
>
> I'll try to find some schematics to confirm..
I think I was checking this some time ago and design was the same as in
SM8750 and SM8650, so with WCD9395 USB mux. You could argue that WCD9395
WCD mux has separate interface than audio part, but it is still the same
device, thus that is why I think USB and audio are still related.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 18/20] arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC)
2025-10-08 23:50 ` Krzysztof Kozlowski
@ 2025-10-27 9:39 ` Konrad Dybcio
0 siblings, 0 replies; 135+ messages in thread
From: Konrad Dybcio @ 2025-10-27 9:39 UTC (permalink / raw)
To: Krzysztof Kozlowski, Prasad Kumpatla, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On 10/9/25 1:50 AM, Krzysztof Kozlowski wrote:
> On 08/10/2025 20:30, Konrad Dybcio wrote:
>> On 10/8/25 12:51 PM, Krzysztof Kozlowski wrote:
>>> On 08/10/2025 19:20, Konrad Dybcio wrote:
>>>> On 10/6/25 10:48 AM, Krzysztof Kozlowski wrote:
>>>>> On 30/09/2025 21:06, Prasad Kumpatla wrote:
>>>>>>
>>>>>> On 9/25/2025 6:56 PM, Krzysztof Kozlowski wrote:
>>>>>>> On Thu, 25 Sept 2025 at 09:18, Jingyi Wang <jingyi.wang@oss.qualcomm.com> wrote:
>>>>>>>> From: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>>>>>>>>
>>>>>>>> Add support for audio on the Kaanapali MTP platform by introducing device
>>>>>>>> tree nodes for WSA8845 smart speaker amplifier for playback, DMIC
>>>>>>>> microphone for capture, and sound card routing. The WCD9395 codec is add
>>>>>>>> to supply MIC-BIAS, for enabling onboard microphone capture.
>>>>>>>>
>>>>>>>> Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
>>>>>>>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>>>>>>>> ---
>>>>>>>> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 226 +++++++++++++++++++++++++++++
>>>>>>>> 1 file changed, 226 insertions(+)
>>>>>>>>
>>>>>>> Audio is not a separate feature from USB.
>>>>>>
>>>>>> I didn't understand this, Could you please help me to provide more
>>>>>> context on it?
>>>>>> Is this regarding Audio over Type-c?
>>>>>
>>>>> USB depends on ADSP, so your split of patches into separate audio commit
>>>>> is just incorrect.
>>>>
>>>> No, this is no longer the case on Kaanapali.
>>>>
>>>> PMIC_GLINK is now served by the SoCCP rproc
>>>
>>> Hm, ok.... so there is no WCD93xx USB mux anymore?
>>
>> I see there's a WCD9395 onboard which has that hw block
>>
>> I'll try to find some schematics to confirm..
>
> I think I was checking this some time ago and design was the same as in
> SM8750 and SM8650, so with WCD9395 USB mux. You could argue that WCD9395
> WCD mux has separate interface than audio part, but it is still the same
> device, thus that is why I think USB and audio are still related.
I found a schematic for the MTP.
The WCD9395 mux is still in place
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread
* [PATCH 19/20] arm64: dts: qcom: kaanapali: Add support for camss
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (17 preceding siblings ...)
2025-09-25 0:17 ` [PATCH 18/20] arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC) Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-09-25 0:17 ` [PATCH 20/20] arm64: dts: qcom: kaanapali: Add iris video node Jingyi Wang
` (3 subsequent siblings)
22 siblings, 0 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang, Hangxiang Ma
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add support for the camera subsystem on the Kaanapali Qualcomm SoC. This
includes bringing up the CSIPHY, CSID, VFE/RDI interfaces.
Kaanapali provides
- 3 x VFE, 5 RDI per VFE
- 2 x VFE Lite, 4 RDI per VFE
- 3 x CSID
- 2 x CSID Lite
- 6 x CSI PHY
Written with help from Taniya Das(added camera clk nodes).
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 502 ++++++++++++++++++++++++++++++++
1 file changed, 502 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 6aa8dedbb196..a95274fa3c31 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -3,6 +3,8 @@
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
+#include <dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h>
+#include <dt-bindings/clock/qcom,kaanapali-camcc.h>
#include <dt-bindings/clock/qcom,kaanapali-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
@@ -1673,6 +1675,25 @@ aggre_noc: interconnect@16e0000 {
<&rpmhcc RPMH_IPA_CLK>;
};
+ cambistmclkcc: clock-controller@1760000 {
+ compatible = "qcom,kaanapali-cambistmclkcc";
+ reg = <0x0 0x1760000 0x0 0x6000>;
+
+ clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>,
+ <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&sleep_clk>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
mmss_noc: interconnect@1780000 {
compatible = "qcom,kaanapali-mmss-noc";
reg = <0x0 0x01780000 0x0 0x5b800>;
@@ -3380,6 +3401,295 @@ usb_dp_qmpphy_dp_in: endpoint {
};
};
+ camss: isp@9253000 {
+ compatible = "qcom,kaanapali-camss";
+
+ reg = <0x0 0x09253000 0x0 0x5e80>,
+ <0x0 0x09263000 0x0 0x5e80>,
+ <0x0 0x09273000 0x0 0x5e80>,
+ <0x0 0x092d3000 0x0 0x3880>,
+ <0x0 0x092e7000 0x0 0x3880>,
+ <0x0 0x09523000 0x0 0x2000>,
+ <0x0 0x09525000 0x0 0x2000>,
+ <0x0 0x09527000 0x0 0x2000>,
+ <0x0 0x09529000 0x0 0x2000>,
+ <0x0 0x0952b000 0x0 0x2000>,
+ <0x0 0x0952d000 0x0 0x2000>,
+ <0x0 0x09151000 0x0 0x20000>,
+ <0x0 0x09171000 0x0 0x20000>,
+ <0x0 0x09191000 0x0 0x20000>,
+ <0x0 0x092dc000 0x0 0x1300>,
+ <0x0 0x092f0000 0x0 0x1300>;
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "csiphy5",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY5_CLK>,
+ <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+ clock-names = "camnoc_nrt_axi",
+ "camnoc_rt_axi",
+ "camnoc_rt_vfe0",
+ "camnoc_rt_vfe1",
+ "camnoc_rt_vfe2",
+ "camnoc_rt_vfe_lite",
+ "cam_top_ahb",
+ "cam_top_fast_ahb",
+ "csid",
+ "csid_csiphy_rx",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer",
+ "csiphy4",
+ "csiphy4_timer",
+ "csiphy5",
+ "csiphy5_timer",
+ "gcc_hf_axi",
+ "qdss_debug_xo",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid";
+
+ interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "csiphy5",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_0_mnoc";
+
+ iommus = <&apps_smmu 0x1c00 0x00>;
+
+ power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
+ <&camcc CAM_CC_TFE_1_GDSC>,
+ <&camcc CAM_CC_TFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "tfe0",
+ "tfe1",
+ "tfe2",
+ "top";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ };
+ };
+ };
+
+ cci0: cci@941b000 {
+ compatible = "qcom,kaanapali-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0941b000 0x0 0x1000>;
+ interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>;
+ clock-names = "cam_top_ahb", "cci";
+ pinctrl-0 = <&cci0_0_default &cci0_1_default>;
+ pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@941c000 {
+ compatible = "qcom,kaanapali-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0941c000 0x0 0x1000>;
+ interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK>;
+ clock-names = "cam_top_ahb", "cci";
+ pinctrl-0 = <&cci1_0_default &cci1_1_default>;
+ pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci2: cci@941d000 {
+ compatible = "qcom,kaanapali-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0941d000 0x0 0x1000>;
+ interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CCI_2_CLK>;
+ clock-names = "cam_top_ahb", "cci";
+ pinctrl-0 = <&cci2_0_default &cci2_1_default>;
+ pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci2_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci2_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ camcc: clock-controller@956d000 {
+ compatible = "qcom,kaanapali-camcc";
+ reg = <0x0 0x956d000 0x0 0x80000>;
+
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&sleep_clk>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
usb_1: usb@a600000 {
compatible = "qcom,kaanapali-dwc3", "qcom,snps-dwc3";
reg = <0x0 0x0a600000 0x0 0xfc100>;
@@ -3653,6 +3963,198 @@ tlmm: pinctrl@f100000 {
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
+ cci0_0_default: cci0-0-default-state {
+ sda-pins {
+ pins = "gpio109";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio110";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci0_0_sleep: cci0-0-sleep-state {
+ sda-pins {
+ pins = "gpio109";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio110";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci0_1_default: cci0-1-default-state {
+ sda-pins {
+ pins = "gpio111";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio112";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci0_1_sleep: cci0-1-sleep-state {
+ sda-pins {
+ pins = "gpio111";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio112";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_0_default: cci1-0-default-state {
+ sda-pins {
+ pins = "gpio113";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio114";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci1_0_sleep: cci1-0-sleep-state {
+ sda-pins {
+ pins = "gpio113";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio114";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_1_default: cci1-1-default-state {
+ sda-pins {
+ pins = "gpio107";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio160";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci1_1_sleep: cci1-1-sleep-state {
+ sda-pins {
+ pins = "gpio107";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio160";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci2_0_default: cci2-0-default-state {
+ sda-pins {
+ pins = "gpio108";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio149";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci2_0_sleep: cci2-0-sleep-state {
+ sda-pins {
+ pins = "gpio108";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio149";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci2_1_default: cci2-1-default-state {
+ sda-pins {
+ pins = "gpio115";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio116";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci2_1_sleep: cci2-1-sleep-state {
+ sda-pins {
+ pins = "gpio115";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio116";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
hub_i2c0_data_clk: hub-i2c0-data-clk-state {
/* SDA, SCL */
pins = "gpio66", "gpio67";
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* [PATCH 20/20] arm64: dts: qcom: kaanapali: Add iris video node
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (18 preceding siblings ...)
2025-09-25 0:17 ` [PATCH 19/20] arm64: dts: qcom: kaanapali: Add support for camss Jingyi Wang
@ 2025-09-25 0:17 ` Jingyi Wang
2025-10-07 2:17 ` Krzysztof Kozlowski
2025-10-08 8:30 ` Konrad Dybcio
2025-09-25 14:12 ` [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Rob Herring (Arm)
` (2 subsequent siblings)
22 siblings, 2 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:17 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Jingyi Wang, Vikash Garodia
Add DT node for the kaanapali iris video node.
Written with help from Taniya Das(added videocc node).
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
1 file changed, 155 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index a95274fa3c31..23c4fd9a753b 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h>
#include <dt-bindings/clock/qcom,kaanapali-camcc.h>
#include <dt-bindings/clock/qcom,kaanapali-gcc.h>
+#include <dt-bindings/clock/qcom,kaanapali-videocc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
#include <dt-bindings/dma/qcom-gpi.h>
@@ -2707,6 +2708,160 @@ tcsrcc: clock-controller@1fd5044 {
#reset-cells = <1>;
};
+ iris: video-codec@2000000 {
+ compatible = "qcom,kaanapali-iris";
+
+ reg = <0x0 0x02000000 0x0 0xf0000>;
+
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
+ <&videocc VIDEO_CC_MVS0_GDSC>,
+ <&videocc VIDEO_CC_MVS0_VPP0_GDSC>,
+ <&videocc VIDEO_CC_MVS0_VPP1_GDSC>,
+ <&videocc VIDEO_CC_MVS0A_GDSC>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "vpp0",
+ "vpp1",
+ "apv",
+ "mxc",
+ "mmcx";
+
+ operating-points-v2 = <&iris_opp_table>;
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&videocc VIDEO_CC_MVS0C_CLK>,
+ <&videocc VIDEO_CC_MVS0_CLK>,
+ <&gcc GCC_VIDEO_AXI1_CLK>,
+ <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>,
+ <&videocc VIDEO_CC_MVS0_FREERUN_CLK>,
+ <&videocc VIDEO_CC_MVS0B_CLK>,
+ <&videocc VIDEO_CC_MVS0_VPP0_CLK>,
+ <&videocc VIDEO_CC_MVS0_VPP1_CLK>,
+ <&videocc VIDEO_CC_MVS0A_CLK>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core",
+ "iface1",
+ "core_freerun",
+ "vcodec0_core_freerun",
+ "vcodec_bse",
+ "vcodec_vpp0",
+ "vcodec_vpp1",
+ "vcodec_apv";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ memory-region = <&video_mem>;
+
+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+ <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>;
+ reset-names = "bus0",
+ "bus1",
+ "core_freerun_reset",
+ "vcodec0_core_freerun_reset";
+
+ iommus = <&apps_smmu 0x1940 0x0>,
+ <&apps_smmu 0x1943 0x0>,
+ <&apps_smmu 0x1944 0x0>,
+ <&apps_smmu 0x1a20 0x0>;
+
+ dma-coherent;
+
+ /*
+ * IRIS firmware is signed by vendors, only
+ * enable on boards where the proper signed firmware
+ * is available.
+ */
+ status = "disabled";
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000 240000000
+ 240000000 360000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000 338000000
+ 338000000 507000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-420000000 {
+ opp-hz = /bits/ 64 <420000000 420000000
+ 420000000 630000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000 444000000
+ 444000000 666000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-533000000 {
+ opp-hz = /bits/ 64 <533000000 533000000
+ 533000000 800000000>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-630000000 {
+ opp-hz = /bits/ 64 <630000000 630000000
+ 630000000 1104000000>;
+ required-opps = <&rpmhpd_opp_turbo>,
+ <&rpmhpd_opp_turbo>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000 630000000
+ 630000000 1260000000>;
+ required-opps = <&rpmhpd_opp_turbo_l0>,
+ <&rpmhpd_opp_turbo_l0>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000 630000000
+ 850000000 1260000000>;
+ required-opps = <&rpmhpd_opp_turbo_l1>,
+ <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
+
+ videocc: clock-controller@20f0000 {
+ compatible = "qcom,kaanapali-videocc";
+ reg = <0x0 0x20f0000 0x0 0x10000>;
+ clocks = <&bi_tcxo_div2>,
+ <&gcc GCC_VIDEO_AHB_CLK>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,kaanapali-mpss-pas", "qcom,sm8750-mpss-pas";
reg = <0x0 0x04080000 0x0 0x10000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 135+ messages in thread* Re: [PATCH 20/20] arm64: dts: qcom: kaanapali: Add iris video node
2025-09-25 0:17 ` [PATCH 20/20] arm64: dts: qcom: kaanapali: Add iris video node Jingyi Wang
@ 2025-10-07 2:17 ` Krzysztof Kozlowski
2025-10-08 8:30 ` Konrad Dybcio
1 sibling, 0 replies; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-07 2:17 UTC (permalink / raw)
To: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Vikash Garodia
On 25/09/2025 09:17, Jingyi Wang wrote:
> Add DT node for the kaanapali iris video node.
>
> Written with help from Taniya Das(added videocc node).
>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
That's not a separate patch. Squash it.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 20/20] arm64: dts: qcom: kaanapali: Add iris video node
2025-09-25 0:17 ` [PATCH 20/20] arm64: dts: qcom: kaanapali: Add iris video node Jingyi Wang
2025-10-07 2:17 ` Krzysztof Kozlowski
@ 2025-10-08 8:30 ` Konrad Dybcio
1 sibling, 0 replies; 135+ messages in thread
From: Konrad Dybcio @ 2025-10-08 8:30 UTC (permalink / raw)
To: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Vikash Garodia
On 9/25/25 2:17 AM, Jingyi Wang wrote:
> Add DT node for the kaanapali iris video node.
>
> Written with help from Taniya Das(added videocc node).
>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
I think you might have lost Vikash's authorship here
[...]
> + videocc: clock-controller@20f0000 {
> + compatible = "qcom,kaanapali-videocc";
> + reg = <0x0 0x20f0000 0x0 0x10000>;
> + clocks = <&bi_tcxo_div2>,
> + <&gcc GCC_VIDEO_AHB_CLK>;
> +
> + power-domains = <&rpmhpd RPMHPD_MMCX>,
> + <&rpmhpd RPMHPD_MXC>;
> + required-opps = <&rpmhpd_opp_low_svs>,
> + <&rpmhpd_opp_low_svs>;
I see that the PLLs can operate at LOWSVS_D1 at the same frequencies
as they do at LOWSVS, although they need _SVS to fully stretch their
legs
I think we can do _D1 here? +Taniya?
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (19 preceding siblings ...)
2025-09-25 0:17 ` [PATCH 20/20] arm64: dts: qcom: kaanapali: Add iris video node Jingyi Wang
@ 2025-09-25 14:12 ` Rob Herring (Arm)
2025-09-25 16:51 ` Dmitry Baryshkov
2025-09-30 17:48 ` Alexey Klimov
2025-12-02 18:21 ` Pavel Machek
22 siblings, 1 reply; 135+ messages in thread
From: Rob Herring (Arm) @ 2025-09-25 14:12 UTC (permalink / raw)
To: Jingyi Wang
Cc: Tengfei Fan, Bjorn Andersson, Qiang Yu, linux-kernel, trilok.soni,
Jyothi Kumar Seerapu, aiqun.yu, devicetree, tingwei.zhang,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, Manish Pandey,
Kamal Wadhwa, yijie.yang, Jishnu Prakash, Vikash Garodia,
Konrad Dybcio, Prasad Kumpatla, Ronak Raheja, Hangxiang Ma
On Wed, 24 Sep 2025 17:17:17 -0700, Jingyi Wang wrote:
> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
>
> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
> and QRD (Qualcommm Reference Device) are splited in three:
>
> - 1-3: MTP board boot-to-shell with basic function.
> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
> - 17-20: Multimedia features including audio, video and camss.
>
> Features added and enabled:
> - CPUs with PSCI idle states and cpufreq
> - Interrupt-controller with PDC wakeup support
> - Timers, TCSR Clock Controllers
> - Reserved Shared memory
> - GCC and RPMHCC
> - TLMM
> - Interconnect with CPU BWMONs
> - QuP with uart
> - SMMU
> - RPMHPD and regulator
> - UFS with inline crypto engine (ICE)
> - LLCC
> - Watchdog
> - cDSP, aDSP with SMP2P and fastrpc
> - BUS with I2C and SPI
> - USB2/USB3
> - Modem(see crash after bring up)
> - SoCCP
> - SDHCI
> - random number generator (RNG) and Qcrypto
> - tsens
> - PCIE
> - coresight
> - Bluetooth
> - WLAN
> - Audio
> - CAMSS
> - Video
>
> For part1(patch 1-3)
> build dependency:
> - tlmm: https://lore.kernel.org/all/20250924-knp-tlmm-v1-0-acabb59ae48c@oss.qualcomm.com/
> - gcc: https://lore.kernel.org/all/20250924-knp-clk-v1-0-29b02b818782@oss.qualcomm.com/
> - interconnect: https://lore.kernel.org/all/20250924-knp-interconnect-v1-0-4c822a72141c@oss.qualcomm.com/
> - rpmhpd: https://lore.kernel.org/all/20250924-knp-pd-v1-0-b78444125c91@oss.qualcomm.com/
> - config: https://lore.kernel.org/all/20250924-knp-config-v1-1-e2cf83b1932e@oss.qualcomm.com/
> binding dependency:
> - ipcc: https://lore.kernel.org/all/20250924-knp-ipcc-v1-1-5d9e9cb59ad4@oss.qualcomm.com/
> - smmu: https://lore.kernel.org/all/20250924-knp-smmu-v1-1-c93c998dd04c@oss.qualcomm.com/
> - pdc: https://lore.kernel.org/all/20250924-knp-pdc-v1-1-1aec7ecd2027@oss.qualcomm.com/
> - cpufreq: https://lore.kernel.org/all/20250924-knp-cpufreq-v1-1-1bda16702bb1@oss.qualcomm.com/
> - mfd: https://lore.kernel.org/all/20250924-knp-mfd-v1-1-6c8a98760e95@oss.qualcomm.com/
> - watchdog: https://lore.kernel.org/all/20250924-knp-watchdog-v1-1-fd8f3fa0ae7e@oss.qualcomm.com/
> - llcc: https://lore.kernel.org/all/20250924-knp-llcc-v1-0-ae6a016e5138@oss.qualcomm.com/
> - bwmon: https://lore.kernel.org/all/20250924-knp-bwmon-v1-1-56a9cdda7d72@oss.qualcomm.com/
> - ufs: https://lore.kernel.org/all/20250924-knp-ufs-v1-0-42e0955a1f7c@oss.qualcomm.com/
> - ice: https://lore.kernel.org/all/20250924-knp-ice-v1-1-1adfc2d9e83c@oss.qualcomm.com/
> - regulator: https://lore.kernel.org/all/20250924-knp-regulator-v1-0-d9cde9a98a44@oss.qualcomm.com/
> - misc soc related: https://lore.kernel.org/all/20250924-knp-soc-binding-v1-0-93a072e174f9@oss.qualcomm.com/
> others:
> - socinfo: https://lore.kernel.org/all/20250924-knp-socid-v1-0-fad059c60e71@oss.qualcomm.com/
>
> For part2(patch 4-16)
> build dependency:
> - ipcc header: https://lore.kernel.org/all/20250922-ipcc-header-v1-1-f0b12715e118@oss.qualcomm.com/
> binding dependency:
> - pcie: https://lore.kernel.org/all/20250924-knp-pcie-v1-0-5fb59e398b83@oss.qualcomm.com/
> - sdcard: https://lore.kernel.org/all/20250924-knp-sdcard-v1-1-fc54940066f1@oss.qualcomm.com/
> - usb: https://lore.kernel.org/all/20250924-knp-usb-v1-0-48bf9fbcc546@oss.qualcomm.com/
> - remoteproc: https://lore.kernel.org/all/20250924-knp-remoteproc-v1-0-611bf7be8329@oss.qualcomm.com/
> - tsense: https://lore.kernel.org/all/20250924-knp-tsens-v1-1-ad0cde4bd455@oss.qualcomm.com/
> - crypto: https://lore.kernel.org/all/20250924-knp-crypto-v1-0-49af17a231b7@oss.qualcomm.com/
> - bam: https://lore.kernel.org/all/20250924-knp-bam-v1-0-c991273ddf63@oss.qualcomm.com/
> - spmi: https://lore.kernel.org/all/20250924-knp-spmi-binding-v1-1-b4ace3f7a838@oss.qualcomm.com/
> - pmic: https://lore.kernel.org/all/20250924-knp-pmic-binding-v1-1-b9cce48b8460@oss.qualcomm.com/
> - pmic-peripherals: https://lore.kernel.org/all/20250924-knp-pmic-peri-v1-0-47413f8ddbf2@oss.qualcomm.com/
> - bus: https://lore.kernel.org/all/20250924-knp-bus-v1-1-f2f2c6e6a797@oss.qualcomm.com/
> others:
> - fastrpc: https://lore.kernel.org/all/20250924-knp-fastrpc-v1-0-4b40f8bfce1d@oss.qualcomm.com/
> - spmi-gpio: https://lore.kernel.org/all/20250920-glymur-spmi-v8-gpio-driver-v1-1-23df93b7818a@oss.qualcomm.com/
>
> For part3(patch 17-20)
> dependency:
> - multimedia clk: https://lore.kernel.org/all/20250924-knp-mmclk-v1-0-d7ea96b4784a@oss.qualcomm.com/
> - config: https://lore.kernel.org/all/20250924-knp-config-v1-2-e2cf83b1932e@oss.qualcomm.com/
> - pd-mapper: https://lore.kernel.org/all/20250924-knp-pdmapper-v1-1-fcf44bae377a@oss.qualcomm.com/
> - audio: https://lore.kernel.org/all/20250924-knp-audio-v1-0-5afa926b567c@oss.qualcomm.com/
> - camss: https://lore.kernel.org/all/20250924-knp-cam-v1-0-b72d6deea054@oss.qualcomm.com/
> - video: https://lore.kernel.org/all/20250925-knp_video-v1-0-e323c0b3c0cd@oss.qualcomm.com/
>
> For convenience, a regularly refreshed linux-next based git tree containing all the Kaanapali related work is available at:
> https://git.codelinaro.org/clo/linux-kernel/kernel-qcom/-/tree/kaanapali?ref_type=heads
>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> Hangxiang Ma (1):
> arm64: dts: qcom: kaanapali: Add support for camss
>
> Jingyi Wang (9):
> dt-bindings: arm: qcom: Document Kaanapali SoC and its reference boards
> arm64: dts: qcom: Introduce Kaanapali SoC
> arm64: dts: qcom: kaanapali: Add base MTP board
> arm64: dts: qcom: kaanapali: Add remoteprocs for Kaanapali SoC
> arm64: dts: qcom: kaanapali: Add misc features
> arm64: dts: qcom: kaanapali-mtp: Enable more features
> arm64: dts: qcom: kaanapali-mtp: Enable modem
> arm64: dts: qcom: kaanapali: Add QRD board
> arm64: dts: qcom: kaanapali: Add iris video node
>
> Jishnu Prakash (4):
> arm64: dts: qcom: Add PMK8850 pmic dtsi
> arm64: dts: qcom: Add PMH0101 pmic dtsi
> arm64: dts: qcom: Add PMH0104 pmic dtsi
> arm64: dts: qcom: Add PMH0110 pmic dtsi
>
> Jyothi Kumar Seerapu (1):
> arm64: dts: qcom: kaanapali: Add QUPv3 configuration for serial engines
>
> Manish Pandey (1):
> arm64: dts: qcom: kaanapali: Add SDC2 nodes for Kaanapali soc
>
> Prasad Kumpatla (2):
> arm64: dts: qcom: kaanapali: Add support for audio
> arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC)
>
> Qiang Yu (1):
> arm64: dts: qcom: kaanapali: Add support for PCIe0 on Kaanapali
>
> Ronak Raheja (1):
> arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC
>
> Documentation/devicetree/bindings/arm/qcom.yaml | 6 +
> arch/arm64/boot/dts/qcom/Makefile | 2 +
> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 1601 ++++++
> arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 1212 +++++
> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 6315 +++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/pmh0101.dtsi | 45 +
> arch/arm64/boot/dts/qcom/pmh0104.dtsi | 33 +
> arch/arm64/boot/dts/qcom/pmh0110.dtsi | 109 +
> arch/arm64/boot/dts/qcom/pmk8850.dtsi | 66 +
> 9 files changed, 9389 insertions(+)
> ---
> base-commit: ae2d20002576d2893ecaff25db3d7ef9190ac0b6
> change-id: 20250918-knp-dts-0e8da3f76e85
>
> Best regards,
> --
> Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base:
Base: using specified base-commit ae2d20002576d2893ecaff25db3d7ef9190ac0b6
If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20250924-knp-dts-v1-0-3fdbc4b9e1b1@oss.qualcomm.com:
In file included from arch/arm64/boot/dts/qcom/kaanapali-qrd.dts:12:
arch/arm64/boot/dts/qcom/kaanapali.dtsi:6:10: fatal error: dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h: No such file or directory
6 | #include <dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[3]: *** [scripts/Makefile.dtbs:132: arch/arm64/boot/dts/qcom/kaanapali-qrd.dtb] Error 1
make[2]: *** [scripts/Makefile.build:556: arch/arm64/boot/dts/qcom] Error 2
make[2]: Target 'arch/arm64/boot/dts/qcom/kaanapali-qrd.dtb' not remade because of errors.
make[1]: *** [/home/rob/proj/linux-dt-testing/Makefile:1478: qcom/kaanapali-qrd.dtb] Error 2
In file included from arch/arm64/boot/dts/qcom/kaanapali-mtp.dts:12:
arch/arm64/boot/dts/qcom/kaanapali.dtsi:6:10: fatal error: dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h: No such file or directory
6 | #include <dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[3]: *** [scripts/Makefile.dtbs:132: arch/arm64/boot/dts/qcom/kaanapali-mtp.dtb] Error 1
make[2]: *** [scripts/Makefile.build:556: arch/arm64/boot/dts/qcom] Error 2
make[2]: Target 'arch/arm64/boot/dts/qcom/kaanapali-mtp.dtb' not remade because of errors.
make[1]: *** [/home/rob/proj/linux-dt-testing/Makefile:1478: qcom/kaanapali-mtp.dtb] Error 2
make: *** [Makefile:248: __sub-make] Error 2
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^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-09-25 14:12 ` [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Rob Herring (Arm)
@ 2025-09-25 16:51 ` Dmitry Baryshkov
0 siblings, 0 replies; 135+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 16:51 UTC (permalink / raw)
To: Rob Herring (Arm)
Cc: Jingyi Wang, Tengfei Fan, Bjorn Andersson, Qiang Yu, linux-kernel,
trilok.soni, Jyothi Kumar Seerapu, aiqun.yu, devicetree,
tingwei.zhang, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
Manish Pandey, Kamal Wadhwa, yijie.yang, Jishnu Prakash,
Vikash Garodia, Konrad Dybcio, Prasad Kumpatla, Ronak Raheja,
Hangxiang Ma
On Thu, Sep 25, 2025 at 09:12:30AM -0500, Rob Herring (Arm) wrote:
>
> On Wed, 24 Sep 2025 17:17:17 -0700, Jingyi Wang wrote:
> > Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
> > https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
> >
> > Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
> > and QRD (Qualcommm Reference Device) are splited in three:
> >
> > - 1-3: MTP board boot-to-shell with basic function.
> > - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
> > - 17-20: Multimedia features including audio, video and camss.
> >
> > Features added and enabled:
> > - CPUs with PSCI idle states and cpufreq
> > - Interrupt-controller with PDC wakeup support
> > - Timers, TCSR Clock Controllers
> > - Reserved Shared memory
> > - GCC and RPMHCC
> > - TLMM
> > - Interconnect with CPU BWMONs
> > - QuP with uart
> > - SMMU
> > - RPMHPD and regulator
> > - UFS with inline crypto engine (ICE)
> > - LLCC
> > - Watchdog
> > - cDSP, aDSP with SMP2P and fastrpc
> > - BUS with I2C and SPI
> > - USB2/USB3
> > - Modem(see crash after bring up)
> > - SoCCP
> > - SDHCI
> > - random number generator (RNG) and Qcrypto
> > - tsens
> > - PCIE
> > - coresight
> > - Bluetooth
> > - WLAN
> > - Audio
> > - CAMSS
> > - Video
> >
> > For part1(patch 1-3)
> > build dependency:
> > - tlmm: https://lore.kernel.org/all/20250924-knp-tlmm-v1-0-acabb59ae48c@oss.qualcomm.com/
> > - gcc: https://lore.kernel.org/all/20250924-knp-clk-v1-0-29b02b818782@oss.qualcomm.com/
> > - interconnect: https://lore.kernel.org/all/20250924-knp-interconnect-v1-0-4c822a72141c@oss.qualcomm.com/
> > - rpmhpd: https://lore.kernel.org/all/20250924-knp-pd-v1-0-b78444125c91@oss.qualcomm.com/
> > - config: https://lore.kernel.org/all/20250924-knp-config-v1-1-e2cf83b1932e@oss.qualcomm.com/
> > binding dependency:
> > - ipcc: https://lore.kernel.org/all/20250924-knp-ipcc-v1-1-5d9e9cb59ad4@oss.qualcomm.com/
> > - smmu: https://lore.kernel.org/all/20250924-knp-smmu-v1-1-c93c998dd04c@oss.qualcomm.com/
> > - pdc: https://lore.kernel.org/all/20250924-knp-pdc-v1-1-1aec7ecd2027@oss.qualcomm.com/
> > - cpufreq: https://lore.kernel.org/all/20250924-knp-cpufreq-v1-1-1bda16702bb1@oss.qualcomm.com/
> > - mfd: https://lore.kernel.org/all/20250924-knp-mfd-v1-1-6c8a98760e95@oss.qualcomm.com/
> > - watchdog: https://lore.kernel.org/all/20250924-knp-watchdog-v1-1-fd8f3fa0ae7e@oss.qualcomm.com/
> > - llcc: https://lore.kernel.org/all/20250924-knp-llcc-v1-0-ae6a016e5138@oss.qualcomm.com/
> > - bwmon: https://lore.kernel.org/all/20250924-knp-bwmon-v1-1-56a9cdda7d72@oss.qualcomm.com/
> > - ufs: https://lore.kernel.org/all/20250924-knp-ufs-v1-0-42e0955a1f7c@oss.qualcomm.com/
> > - ice: https://lore.kernel.org/all/20250924-knp-ice-v1-1-1adfc2d9e83c@oss.qualcomm.com/
> > - regulator: https://lore.kernel.org/all/20250924-knp-regulator-v1-0-d9cde9a98a44@oss.qualcomm.com/
> > - misc soc related: https://lore.kernel.org/all/20250924-knp-soc-binding-v1-0-93a072e174f9@oss.qualcomm.com/
> > others:
> > - socinfo: https://lore.kernel.org/all/20250924-knp-socid-v1-0-fad059c60e71@oss.qualcomm.com/
> >
> > For part2(patch 4-16)
> > build dependency:
> > - ipcc header: https://lore.kernel.org/all/20250922-ipcc-header-v1-1-f0b12715e118@oss.qualcomm.com/
> > binding dependency:
> > - pcie: https://lore.kernel.org/all/20250924-knp-pcie-v1-0-5fb59e398b83@oss.qualcomm.com/
> > - sdcard: https://lore.kernel.org/all/20250924-knp-sdcard-v1-1-fc54940066f1@oss.qualcomm.com/
> > - usb: https://lore.kernel.org/all/20250924-knp-usb-v1-0-48bf9fbcc546@oss.qualcomm.com/
> > - remoteproc: https://lore.kernel.org/all/20250924-knp-remoteproc-v1-0-611bf7be8329@oss.qualcomm.com/
> > - tsense: https://lore.kernel.org/all/20250924-knp-tsens-v1-1-ad0cde4bd455@oss.qualcomm.com/
> > - crypto: https://lore.kernel.org/all/20250924-knp-crypto-v1-0-49af17a231b7@oss.qualcomm.com/
> > - bam: https://lore.kernel.org/all/20250924-knp-bam-v1-0-c991273ddf63@oss.qualcomm.com/
> > - spmi: https://lore.kernel.org/all/20250924-knp-spmi-binding-v1-1-b4ace3f7a838@oss.qualcomm.com/
> > - pmic: https://lore.kernel.org/all/20250924-knp-pmic-binding-v1-1-b9cce48b8460@oss.qualcomm.com/
> > - pmic-peripherals: https://lore.kernel.org/all/20250924-knp-pmic-peri-v1-0-47413f8ddbf2@oss.qualcomm.com/
> > - bus: https://lore.kernel.org/all/20250924-knp-bus-v1-1-f2f2c6e6a797@oss.qualcomm.com/
> > others:
> > - fastrpc: https://lore.kernel.org/all/20250924-knp-fastrpc-v1-0-4b40f8bfce1d@oss.qualcomm.com/
> > - spmi-gpio: https://lore.kernel.org/all/20250920-glymur-spmi-v8-gpio-driver-v1-1-23df93b7818a@oss.qualcomm.com/
> >
> > For part3(patch 17-20)
> > dependency:
> > - multimedia clk: https://lore.kernel.org/all/20250924-knp-mmclk-v1-0-d7ea96b4784a@oss.qualcomm.com/
> > - config: https://lore.kernel.org/all/20250924-knp-config-v1-2-e2cf83b1932e@oss.qualcomm.com/
> > - pd-mapper: https://lore.kernel.org/all/20250924-knp-pdmapper-v1-1-fcf44bae377a@oss.qualcomm.com/
> > - audio: https://lore.kernel.org/all/20250924-knp-audio-v1-0-5afa926b567c@oss.qualcomm.com/
> > - camss: https://lore.kernel.org/all/20250924-knp-cam-v1-0-b72d6deea054@oss.qualcomm.com/
> > - video: https://lore.kernel.org/all/20250925-knp_video-v1-0-e323c0b3c0cd@oss.qualcomm.com/
Please separate the actual dependencies (the patches which are required
to build the DT) and all other patches which are not a real
dependencies. Just adding a binding is not a dependency.
> >
> > For convenience, a regularly refreshed linux-next based git tree containing all the Kaanapali related work is available at:
> > https://git.codelinaro.org/clo/linux-kernel/kernel-qcom/-/tree/kaanapali?ref_type=heads
> >
> > Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> > ---
> > base-commit: ae2d20002576d2893ecaff25db3d7ef9190ac0b6
> > change-id: 20250918-knp-dts-0e8da3f76e85
Oh, you are using b4, but you don't use b4 prep --edit-deps. That's sad.
> >
> > Best regards,
> > --
> > Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> >
> >
> >
>
>
> My bot found new DTB warnings on the .dts files added or changed in this
> series.
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (20 preceding siblings ...)
2025-09-25 14:12 ` [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Rob Herring (Arm)
@ 2025-09-30 17:48 ` Alexey Klimov
2025-10-03 9:09 ` Prasad Kumpatla
2025-12-02 18:21 ` Pavel Machek
22 siblings, 1 reply; 135+ messages in thread
From: Alexey Klimov @ 2025-09-30 17:48 UTC (permalink / raw)
To: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Tengfei Fan, Qiang Yu, Manish Pandey,
Ronak Raheja, Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Prasad Kumpatla, Hangxiang Ma, Vikash Garodia
On Thu Sep 25, 2025 at 1:17 AM BST, Jingyi Wang wrote:
> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
>
> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
> and QRD (Qualcommm Reference Device) are splited in three:
>
> - 1-3: MTP board boot-to-shell with basic function.
> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
> - 17-20: Multimedia features including audio, video and camss.
>
> Features added and enabled:
> - CPUs with PSCI idle states and cpufreq
> - Interrupt-controller with PDC wakeup support
> - Timers, TCSR Clock Controllers
> - Reserved Shared memory
> - GCC and RPMHCC
> - TLMM
> - Interconnect with CPU BWMONs
> - QuP with uart
> - SMMU
> - RPMHPD and regulator
> - UFS with inline crypto engine (ICE)
> - LLCC
> - Watchdog
> - cDSP, aDSP with SMP2P and fastrpc
> - BUS with I2C and SPI
> - USB2/USB3
> - Modem(see crash after bring up)
> - SoCCP
> - SDHCI
> - random number generator (RNG) and Qcrypto
> - tsens
> - PCIE
> - coresight
> - Bluetooth
> - WLAN
> - Audio
Were everything described as audio enabled and tested? As far as I was aware
some devices required some soundwire rework to support soundwire microphones.
Is it finished? I don't see this linked here, but you state that audio
features "added and enabled".
Do we understand this correctly that, I presume, everthing that is more-or-less compatible
with previous platforms were added and enabled (with renames) but not _all_ ?
Probably some rewording is required.
Best regards,
Alexey
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-09-30 17:48 ` Alexey Klimov
@ 2025-10-03 9:09 ` Prasad Kumpatla
2025-10-03 16:35 ` Alexey Klimov
0 siblings, 1 reply; 135+ messages in thread
From: Prasad Kumpatla @ 2025-10-03 9:09 UTC (permalink / raw)
To: Alexey Klimov, Jingyi Wang, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Tengfei Fan, Qiang Yu, Manish Pandey,
Ronak Raheja, Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Hangxiang Ma, Vikash Garodia
On 9/30/2025 11:18 PM, Alexey Klimov wrote:
> On Thu Sep 25, 2025 at 1:17 AM BST, Jingyi Wang wrote:
>> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
>> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
>>
>> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
>> and QRD (Qualcommm Reference Device) are splited in three:
>>
>> - 1-3: MTP board boot-to-shell with basic function.
>> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
>> - 17-20: Multimedia features including audio, video and camss.
>>
>> Features added and enabled:
>> - CPUs with PSCI idle states and cpufreq
>> - Interrupt-controller with PDC wakeup support
>> - Timers, TCSR Clock Controllers
>> - Reserved Shared memory
>> - GCC and RPMHCC
>> - TLMM
>> - Interconnect with CPU BWMONs
>> - QuP with uart
>> - SMMU
>> - RPMHPD and regulator
>> - UFS with inline crypto engine (ICE)
>> - LLCC
>> - Watchdog
>> - cDSP, aDSP with SMP2P and fastrpc
>> - BUS with I2C and SPI
>> - USB2/USB3
>> - Modem(see crash after bring up)
>> - SoCCP
>> - SDHCI
>> - random number generator (RNG) and Qcrypto
>> - tsens
>> - PCIE
>> - coresight
>> - Bluetooth
>> - WLAN
>> - Audio
> Were everything described as audio enabled and tested? As far as I was aware
> some devices required some soundwire rework to support soundwire microphones.
> Is it finished? I don't see this linked here, but you state that audio
> features "added and enabled".
>
> Do we understand this correctly that, I presume, everthing that is more-or-less compatible
> with previous platforms were added and enabled (with renames) but not _all_ ?
>
> Probably some rewording is required.
No, As outlined in the commit message, validation was performed on the
Kaanapali-MTP platform having
WSA8845 and On board Microphones(Mic Bias supply from WCD939x) , and
there is no SoundWire
microphones support on this MTP platform.
Thanks,
Prasad
>
> Best regards,
> Alexey
>
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-10-03 9:09 ` Prasad Kumpatla
@ 2025-10-03 16:35 ` Alexey Klimov
2025-10-14 6:09 ` Jingyi Wang
0 siblings, 1 reply; 135+ messages in thread
From: Alexey Klimov @ 2025-10-03 16:35 UTC (permalink / raw)
To: Prasad Kumpatla, Jingyi Wang, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Tengfei Fan, Qiang Yu, Manish Pandey,
Ronak Raheja, Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Hangxiang Ma, Vikash Garodia
On Fri Oct 3, 2025 at 10:09 AM BST, Prasad Kumpatla wrote:
>
> On 9/30/2025 11:18 PM, Alexey Klimov wrote:
>> On Thu Sep 25, 2025 at 1:17 AM BST, Jingyi Wang wrote:
>>> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
>>> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
>>>
>>> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
>>> and QRD (Qualcommm Reference Device) are splited in three:
>>>
>>> - 1-3: MTP board boot-to-shell with basic function.
>>> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
>>> - 17-20: Multimedia features including audio, video and camss.
>>>
>>> Features added and enabled:
>>> - CPUs with PSCI idle states and cpufreq
>>> - Interrupt-controller with PDC wakeup support
>>> - Timers, TCSR Clock Controllers
>>> - Reserved Shared memory
>>> - GCC and RPMHCC
>>> - TLMM
>>> - Interconnect with CPU BWMONs
>>> - QuP with uart
>>> - SMMU
>>> - RPMHPD and regulator
>>> - UFS with inline crypto engine (ICE)
>>> - LLCC
>>> - Watchdog
>>> - cDSP, aDSP with SMP2P and fastrpc
>>> - BUS with I2C and SPI
>>> - USB2/USB3
>>> - Modem(see crash after bring up)
>>> - SoCCP
>>> - SDHCI
>>> - random number generator (RNG) and Qcrypto
>>> - tsens
>>> - PCIE
>>> - coresight
>>> - Bluetooth
>>> - WLAN
>>> - Audio
>> Were everything described as audio enabled and tested? As far as I was aware
>> some devices required some soundwire rework to support soundwire microphones.
>> Is it finished? I don't see this linked here, but you state that audio
>> features "added and enabled".
>>
>> Do we understand this correctly that, I presume, everthing that is more-or-less compatible
>> with previous platforms were added and enabled (with renames) but not _all_ ?
>>
>> Probably some rewording is required.
>
> No, As outlined in the commit message, validation was performed on the
> Kaanapali-MTP platform having
> WSA8845 and On board Microphones(Mic Bias supply from WCD939x) , and
> there is no SoundWire
> microphones support on this MTP platform.
No, the email here clearly says both MTP and QRD and then that audio
is enabled. That's why is should be clarified otherwise it misleads
that audio is enabled on all platforms/devices including missing
features.
Best regards,
Alexey
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-10-03 16:35 ` Alexey Klimov
@ 2025-10-14 6:09 ` Jingyi Wang
0 siblings, 0 replies; 135+ messages in thread
From: Jingyi Wang @ 2025-10-14 6:09 UTC (permalink / raw)
To: Alexey Klimov, Prasad Kumpatla, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang, Tengfei Fan, Qiang Yu, Manish Pandey,
Ronak Raheja, Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Hangxiang Ma, Vikash Garodia
On 10/4/2025 12:35 AM, Alexey Klimov wrote:
> On Fri Oct 3, 2025 at 10:09 AM BST, Prasad Kumpatla wrote:
>>
>> On 9/30/2025 11:18 PM, Alexey Klimov wrote:
>>> On Thu Sep 25, 2025 at 1:17 AM BST, Jingyi Wang wrote:
>>>> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
>>>> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
>>>>
>>>> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
>>>> and QRD (Qualcommm Reference Device) are splited in three:
>>>>
>>>> - 1-3: MTP board boot-to-shell with basic function.
>>>> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
>>>> - 17-20: Multimedia features including audio, video and camss.
>>>>
>>>> Features added and enabled:
>>>> - CPUs with PSCI idle states and cpufreq
>>>> - Interrupt-controller with PDC wakeup support
>>>> - Timers, TCSR Clock Controllers
>>>> - Reserved Shared memory
>>>> - GCC and RPMHCC
>>>> - TLMM
>>>> - Interconnect with CPU BWMONs
>>>> - QuP with uart
>>>> - SMMU
>>>> - RPMHPD and regulator
>>>> - UFS with inline crypto engine (ICE)
>>>> - LLCC
>>>> - Watchdog
>>>> - cDSP, aDSP with SMP2P and fastrpc
>>>> - BUS with I2C and SPI
>>>> - USB2/USB3
>>>> - Modem(see crash after bring up)
>>>> - SoCCP
>>>> - SDHCI
>>>> - random number generator (RNG) and Qcrypto
>>>> - tsens
>>>> - PCIE
>>>> - coresight
>>>> - Bluetooth
>>>> - WLAN
>>>> - Audio
>>> Were everything described as audio enabled and tested? As far as I was aware
>>> some devices required some soundwire rework to support soundwire microphones.
>>> Is it finished? I don't see this linked here, but you state that audio
>>> features "added and enabled".
>>>
>>> Do we understand this correctly that, I presume, everthing that is more-or-less compatible
>>> with previous platforms were added and enabled (with renames) but not _all_ ?
>>>
>>> Probably some rewording is required.
>>
>> No, As outlined in the commit message, validation was performed on the
>> Kaanapali-MTP platform having
>> WSA8845 and On board Microphones(Mic Bias supply from WCD939x) , and
>> there is no SoundWire
>> microphones support on this MTP platform.
>
> No, the email here clearly says both MTP and QRD and then that audio
> is enabled. That's why is should be clarified otherwise it misleads
> that audio is enabled on all platforms/devices including missing
> features.
>
> Best regards,
> Alexey
Will make the msg more clear in the cover letter for next version.
Thanks,
Jingyi
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
` (21 preceding siblings ...)
2025-09-30 17:48 ` Alexey Klimov
@ 2025-12-02 18:21 ` Pavel Machek
2025-12-02 18:33 ` Konrad Dybcio
` (2 more replies)
22 siblings, 3 replies; 135+ messages in thread
From: Pavel Machek @ 2025-12-02 18:21 UTC (permalink / raw)
To: Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Tengfei Fan, Qiang Yu,
Manish Pandey, Ronak Raheja, Jishnu Prakash, Kamal Wadhwa,
Jyothi Kumar Seerapu, Prasad Kumpatla, Hangxiang Ma,
Vikash Garodia
[-- Attachment #1: Type: text/plain, Size: 946 bytes --]
Hi!
> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
>
> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
> and QRD (Qualcommm Reference Device) are splited in three:
>
> - 1-3: MTP board boot-to-shell with basic function.
> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
> - 17-20: Multimedia features including audio, video and camss.
Thanks for doing this. I assume there devices available with this are
quite expensive/hard to get at this point?
Please cc phone-devel@vger.kernel.org with phone related patches.
Best regards,
Pavel
--
I don't work for Nazis and criminals, and neither should you.
Boycott Putin, Trump, Netanyahu and Musk!
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-02 18:21 ` Pavel Machek
@ 2025-12-02 18:33 ` Konrad Dybcio
2025-12-02 20:56 ` Pavel Machek
2025-12-03 17:31 ` Krzysztof Kozlowski
2025-12-04 2:41 ` Jingyi Wang
2 siblings, 1 reply; 135+ messages in thread
From: Konrad Dybcio @ 2025-12-02 18:33 UTC (permalink / raw)
To: Pavel Machek, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Tengfei Fan, Qiang Yu,
Manish Pandey, Ronak Raheja, Jishnu Prakash, Kamal Wadhwa,
Jyothi Kumar Seerapu, Prasad Kumpatla, Hangxiang Ma,
Vikash Garodia
On 12/2/25 7:21 PM, Pavel Machek wrote:
> Hi!
>
>> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
>> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
>>
>> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
>> and QRD (Qualcommm Reference Device) are splited in three:
>>
>> - 1-3: MTP board boot-to-shell with basic function.
>> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
>> - 17-20: Multimedia features including audio, video and camss.
>
> Thanks for doing this. I assume there devices available with this are
> quite expensive/hard to get at this point?
A number of them seem available at most shops now, but they just came out
recently and they're all flagship phones so understandably it'll probably
take some time before enthusiasts poke at them
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-02 18:33 ` Konrad Dybcio
@ 2025-12-02 20:56 ` Pavel Machek
2025-12-03 10:34 ` Konrad Dybcio
0 siblings, 1 reply; 135+ messages in thread
From: Pavel Machek @ 2025-12-02 20:56 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Tengfei Fan, Qiang Yu, Manish Pandey, Ronak Raheja,
Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Prasad Kumpatla, Hangxiang Ma, Vikash Garodia
[-- Attachment #1: Type: text/plain, Size: 1606 bytes --]
On Tue 2025-12-02 19:33:03, Konrad Dybcio wrote:
> On 12/2/25 7:21 PM, Pavel Machek wrote:
> > Hi!
> >
> >> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
> >> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
> >>
> >> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
> >> and QRD (Qualcommm Reference Device) are splited in three:
> >>
> >> - 1-3: MTP board boot-to-shell with basic function.
> >> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
> >> - 17-20: Multimedia features including audio, video and camss.
> >
> > Thanks for doing this. I assume there devices available with this are
> > quite expensive/hard to get at this point?
>
> A number of them seem available at most shops now, but they just came out
> recently and they're all flagship phones so understandably it'll probably
> take some time before enthusiasts poke at them
Aha, that's actually good news, I was assuming only dev boards are
available (MTP, QRD). So OnePlus 15, for example, would be suitable?
(But I'd assume OnePlus 15 would still need separate dts, perhaps
similar to MTP?).
https://www.kimovil.com/en/list-smartphones-by-processor-group/snapd-8-elite-g5
Its still more than EUR1000, but better than I expected :-).
Thanks and best regards,
Pavel
--
I don't work for Nazis and criminals, and neither should you.
Boycott Putin, Trump, Netanyahu and Musk!
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-02 20:56 ` Pavel Machek
@ 2025-12-03 10:34 ` Konrad Dybcio
2025-12-03 16:17 ` Pavel Machek
0 siblings, 1 reply; 135+ messages in thread
From: Konrad Dybcio @ 2025-12-03 10:34 UTC (permalink / raw)
To: Pavel Machek
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Tengfei Fan, Qiang Yu, Manish Pandey, Ronak Raheja,
Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Prasad Kumpatla, Hangxiang Ma, Vikash Garodia
On 12/2/25 9:56 PM, Pavel Machek wrote:
> On Tue 2025-12-02 19:33:03, Konrad Dybcio wrote:
>> On 12/2/25 7:21 PM, Pavel Machek wrote:
>>> Hi!
>>>
>>>> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
>>>> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
>>>>
>>>> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
>>>> and QRD (Qualcommm Reference Device) are splited in three:
>>>>
>>>> - 1-3: MTP board boot-to-shell with basic function.
>>>> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
>>>> - 17-20: Multimedia features including audio, video and camss.
>>>
>>> Thanks for doing this. I assume there devices available with this are
>>> quite expensive/hard to get at this point?
>>
>> A number of them seem available at most shops now, but they just came out
>> recently and they're all flagship phones so understandably it'll probably
>> take some time before enthusiasts poke at them
>
> Aha, that's actually good news, I was assuming only dev boards are
> available (MTP, QRD). So OnePlus 15, for example, would be suitable?
> (But I'd assume OnePlus 15 would still need separate dts, perhaps
> similar to MTP?).
There are always *some* bits that are common with the dev boards,
but it really varies. Depends on a specific device and how it was
designed.
Each device needs its own DTS, particularly since it encodes things
like voltage regulator settings, so the consequences may be dire if
there's a mismatch.
Konrad
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-03 10:34 ` Konrad Dybcio
@ 2025-12-03 16:17 ` Pavel Machek
0 siblings, 0 replies; 135+ messages in thread
From: Pavel Machek @ 2025-12-03 16:17 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Tengfei Fan, Qiang Yu, Manish Pandey, Ronak Raheja,
Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Prasad Kumpatla, Hangxiang Ma, Vikash Garodia
[-- Attachment #1: Type: text/plain, Size: 2079 bytes --]
Hi!
> >>>> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
> >>>> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
> >>>>
> >>>> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
> >>>> and QRD (Qualcommm Reference Device) are splited in three:
> >>>>
> >>>> - 1-3: MTP board boot-to-shell with basic function.
> >>>> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
> >>>> - 17-20: Multimedia features including audio, video and camss.
> >>>
> >>> Thanks for doing this. I assume there devices available with this are
> >>> quite expensive/hard to get at this point?
> >>
> >> A number of them seem available at most shops now, but they just came out
> >> recently and they're all flagship phones so understandably it'll probably
> >> take some time before enthusiasts poke at them
> >
> > Aha, that's actually good news, I was assuming only dev boards are
> > available (MTP, QRD). So OnePlus 15, for example, would be suitable?
> > (But I'd assume OnePlus 15 would still need separate dts, perhaps
> > similar to MTP?).
>
> There are always *some* bits that are common with the dev boards,
> but it really varies. Depends on a specific device and how it was
> designed.
>
> Each device needs its own DTS, particularly since it encodes things
> like voltage regulator settings, so the consequences may be dire if
> there's a mismatch.
So if I would like to directly use this patches, I'd need either MTP
or QRD device, and those are not available in shops. Something close
to this should work on hardware such as OnePlus 15, but DTS will need
to be different (and perhaps drivers for hardware that differs) and it
is not clear if OnePlus will not sabotage custom kernels somehow.
Best regards,
Pavel
--
I don't work for Nazis and criminals, and neither should you.
Boycott Putin, Trump, Netanyahu and Musk!
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-02 18:21 ` Pavel Machek
2025-12-02 18:33 ` Konrad Dybcio
@ 2025-12-03 17:31 ` Krzysztof Kozlowski
2025-12-03 18:10 ` Pavel Machek
2025-12-04 2:41 ` Jingyi Wang
2 siblings, 1 reply; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-12-03 17:31 UTC (permalink / raw)
To: Pavel Machek, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Tengfei Fan, Qiang Yu,
Manish Pandey, Ronak Raheja, Jishnu Prakash, Kamal Wadhwa,
Jyothi Kumar Seerapu, Prasad Kumpatla, Hangxiang Ma,
Vikash Garodia
On 02/12/2025 19:21, Pavel Machek wrote:
> Hi!
>
>> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
>> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
>>
>> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
>> and QRD (Qualcommm Reference Device) are splited in three:
>>
>> - 1-3: MTP board boot-to-shell with basic function.
>> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
>> - 17-20: Multimedia features including audio, video and camss.
>
> Thanks for doing this. I assume there devices available with this are
> quite expensive/hard to get at this point?
>
> Please cc phone-devel@vger.kernel.org with phone related patches.
That's not even a phone, anyway contributors should not cc lists which
are not relevant to the posting and not pointed out by maintainers. You
cannot just ask people to keep posting before you wish to look at it.
Please use lei for own filters or adjust maintainers file.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-03 17:31 ` Krzysztof Kozlowski
@ 2025-12-03 18:10 ` Pavel Machek
2025-12-03 18:40 ` Krzysztof Kozlowski
0 siblings, 1 reply; 135+ messages in thread
From: Pavel Machek @ 2025-12-03 18:10 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Tengfei Fan, Qiang Yu, Manish Pandey, Ronak Raheja,
Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Prasad Kumpatla, Hangxiang Ma, Vikash Garodia
[-- Attachment #1: Type: text/plain, Size: 1360 bytes --]
On Wed 2025-12-03 18:31:11, Krzysztof Kozlowski wrote:
> On 02/12/2025 19:21, Pavel Machek wrote:
> > Hi!
> >
> >> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
> >> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
> >>
> >> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
> >> and QRD (Qualcommm Reference Device) are splited in three:
> >>
> >> - 1-3: MTP board boot-to-shell with basic function.
> >> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
> >> - 17-20: Multimedia features including audio, video and camss.
> >
> > Thanks for doing this. I assume there devices available with this are
> > quite expensive/hard to get at this point?
> >
> > Please cc phone-devel@vger.kernel.org with phone related patches.
>
> That's not even a phone, anyway contributors should not cc lists which
> are not relevant to the posting and not pointed out by maintainers. You
People should Cc relevant lists, and yes, if it is called "Mobile Test
Platform", it is relevant to phone development.
Pavel
--
I don't work for Nazis and criminals, and neither should you.
Boycott Putin, Trump, Netanyahu and Musk!
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-03 18:10 ` Pavel Machek
@ 2025-12-03 18:40 ` Krzysztof Kozlowski
2025-12-03 18:41 ` Krzysztof Kozlowski
2025-12-04 9:14 ` Pavel Machek
0 siblings, 2 replies; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-12-03 18:40 UTC (permalink / raw)
To: Pavel Machek
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Tengfei Fan, Qiang Yu, Manish Pandey, Ronak Raheja,
Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Prasad Kumpatla, Hangxiang Ma, Vikash Garodia
On 03/12/2025 19:10, Pavel Machek wrote:
> On Wed 2025-12-03 18:31:11, Krzysztof Kozlowski wrote:
>> On 02/12/2025 19:21, Pavel Machek wrote:
>>> Hi!
>>>
>>>> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
>>>> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
>>>>
>>>> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
>>>> and QRD (Qualcommm Reference Device) are splited in three:
>>>>
>>>> - 1-3: MTP board boot-to-shell with basic function.
>>>> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
>>>> - 17-20: Multimedia features including audio, video and camss.
>>>
>>> Thanks for doing this. I assume there devices available with this are
>>> quite expensive/hard to get at this point?
>>>
>>> Please cc phone-devel@vger.kernel.org with phone related patches.
>>
>> That's not even a phone, anyway contributors should not cc lists which
>> are not relevant to the posting and not pointed out by maintainers. You
>
> People should Cc relevant lists, and yes, if it is called "Mobile Test
> Platform", it is relevant to phone development.
Almost everything in ARM64 is then relevant for "phone development".
People should use tools, not invent or try to guess whom to Cc. It's
impossible to btw keep guessing them - you will request phone-devel,
someone else will request desktop-devel, laptop-devel or
new-hardware-devel or whatever. No. People should use tools, not guess
the cc lists. Fix the tools if you miss any Cc.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-03 18:40 ` Krzysztof Kozlowski
@ 2025-12-03 18:41 ` Krzysztof Kozlowski
2025-12-04 9:09 ` Pavel Machek
2025-12-04 9:14 ` Pavel Machek
1 sibling, 1 reply; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-12-03 18:41 UTC (permalink / raw)
To: Pavel Machek
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Tengfei Fan, Qiang Yu, Manish Pandey, Ronak Raheja,
Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Prasad Kumpatla, Hangxiang Ma, Vikash Garodia
On 03/12/2025 19:40, Krzysztof Kozlowski wrote:
> On 03/12/2025 19:10, Pavel Machek wrote:
>> On Wed 2025-12-03 18:31:11, Krzysztof Kozlowski wrote:
>>> On 02/12/2025 19:21, Pavel Machek wrote:
>>>> Hi!
>>>>
>>>>> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
>>>>> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
>>>>>
>>>>> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
>>>>> and QRD (Qualcommm Reference Device) are splited in three:
>>>>>
>>>>> - 1-3: MTP board boot-to-shell with basic function.
>>>>> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
>>>>> - 17-20: Multimedia features including audio, video and camss.
>>>>
>>>> Thanks for doing this. I assume there devices available with this are
>>>> quite expensive/hard to get at this point?
>>>>
>>>> Please cc phone-devel@vger.kernel.org with phone related patches.
>>>
>>> That's not even a phone, anyway contributors should not cc lists which
>>> are not relevant to the posting and not pointed out by maintainers. You
>>
>> People should Cc relevant lists, and yes, if it is called "Mobile Test
>> Platform", it is relevant to phone development.
... and btw, I know what MTP and QRD is and MTP IS NOT A PHONE. I work
on this, I upstream this and it is not a phone, regardless how you call
it. Just because we call our evalkit like that, does not make it a phone.
>
>
> Almost everything in ARM64 is then relevant for "phone development".
> People should use tools, not invent or try to guess whom to Cc. It's
> impossible to btw keep guessing them - you will request phone-devel,
> someone else will request desktop-devel, laptop-devel or
> new-hardware-devel or whatever. No. People should use tools, not guess
> the cc lists. Fix the tools if you miss any Cc.
>
> Best regards,
> Krzysztof
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-03 18:41 ` Krzysztof Kozlowski
@ 2025-12-04 9:09 ` Pavel Machek
2025-12-04 10:41 ` Krzysztof Kozlowski
0 siblings, 1 reply; 135+ messages in thread
From: Pavel Machek @ 2025-12-04 9:09 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Tengfei Fan, Qiang Yu, Manish Pandey, Ronak Raheja,
Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Prasad Kumpatla, Hangxiang Ma, Vikash Garodia
[-- Attachment #1: Type: text/plain, Size: 1980 bytes --]
On Wed 2025-12-03 19:41:59, Krzysztof Kozlowski wrote:
> On 03/12/2025 19:40, Krzysztof Kozlowski wrote:
> > On 03/12/2025 19:10, Pavel Machek wrote:
> >> On Wed 2025-12-03 18:31:11, Krzysztof Kozlowski wrote:
> >>> On 02/12/2025 19:21, Pavel Machek wrote:
> >>>> Hi!
> >>>>
> >>>>> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
> >>>>> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
> >>>>>
> >>>>> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
> >>>>> and QRD (Qualcommm Reference Device) are splited in three:
> >>>>>
> >>>>> - 1-3: MTP board boot-to-shell with basic function.
> >>>>> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
> >>>>> - 17-20: Multimedia features including audio, video and camss.
> >>>>
> >>>> Thanks for doing this. I assume there devices available with this are
> >>>> quite expensive/hard to get at this point?
> >>>>
> >>>> Please cc phone-devel@vger.kernel.org with phone related patches.
> >>>
> >>> That's not even a phone, anyway contributors should not cc lists which
> >>> are not relevant to the posting and not pointed out by maintainers. You
> >>
> >> People should Cc relevant lists, and yes, if it is called "Mobile Test
> >> Platform", it is relevant to phone development.
>
> ... and btw, I know what MTP and QRD is and MTP IS NOT A PHONE. I work
> on this, I upstream this and it is not a phone, regardless how you call
> it. Just because we call our evalkit like that, does not make it a
phone.
So what is it?
> > new-hardware-devel or whatever. No. People should use tools, not guess
> > the cc lists. Fix the tools if you miss any Cc.
No.
Pavel
--
I don't work for Nazis and criminals, and neither should you.
Boycott Putin, Trump, Netanyahu and Musk!
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-04 9:09 ` Pavel Machek
@ 2025-12-04 10:41 ` Krzysztof Kozlowski
2025-12-04 11:42 ` Pavel Machek
0 siblings, 1 reply; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-12-04 10:41 UTC (permalink / raw)
To: Pavel Machek
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Tengfei Fan, Qiang Yu, Manish Pandey, Ronak Raheja,
Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Prasad Kumpatla, Hangxiang Ma, Vikash Garodia
On 04/12/2025 10:09, Pavel Machek wrote:
> On Wed 2025-12-03 19:41:59, Krzysztof Kozlowski wrote:
>> On 03/12/2025 19:40, Krzysztof Kozlowski wrote:
>>> On 03/12/2025 19:10, Pavel Machek wrote:
>>>> On Wed 2025-12-03 18:31:11, Krzysztof Kozlowski wrote:
>>>>> On 02/12/2025 19:21, Pavel Machek wrote:
>>>>>> Hi!
>>>>>>
>>>>>>> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
>>>>>>> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
>>>>>>>
>>>>>>> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
>>>>>>> and QRD (Qualcommm Reference Device) are splited in three:
>>>>>>>
>>>>>>> - 1-3: MTP board boot-to-shell with basic function.
>>>>>>> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
>>>>>>> - 17-20: Multimedia features including audio, video and camss.
>>>>>>
>>>>>> Thanks for doing this. I assume there devices available with this are
>>>>>> quite expensive/hard to get at this point?
>>>>>>
>>>>>> Please cc phone-devel@vger.kernel.org with phone related patches.
>>>>>
>>>>> That's not even a phone, anyway contributors should not cc lists which
>>>>> are not relevant to the posting and not pointed out by maintainers. You
>>>>
>>>> People should Cc relevant lists, and yes, if it is called "Mobile Test
>>>> Platform", it is relevant to phone development.
>>
>> ... and btw, I know what MTP and QRD is and MTP IS NOT A PHONE. I work
>> on this, I upstream this and it is not a phone, regardless how you call
>> it. Just because we call our evalkit like that, does not make it a
> phone.
>
> So what is it?
evalkit for SoC. Just like every other NXP evalkit board is.
>
>>> new-hardware-devel or whatever. No. People should use tools, not guess
>>> the cc lists. Fix the tools if you miss any Cc.
>
> No.
Then do not impose additional rules to cc foo-devel just because you
want the patches.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-04 10:41 ` Krzysztof Kozlowski
@ 2025-12-04 11:42 ` Pavel Machek
2025-12-04 12:10 ` Krzysztof Kozlowski
0 siblings, 1 reply; 135+ messages in thread
From: Pavel Machek @ 2025-12-04 11:42 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Tengfei Fan, Qiang Yu, Manish Pandey, Ronak Raheja,
Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Prasad Kumpatla, Hangxiang Ma, Vikash Garodia
[-- Attachment #1: Type: text/plain, Size: 2341 bytes --]
> >>>>>>> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
> >>>>>>> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
> >>>>>>> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
> >>>>>>> and QRD (Qualcommm Reference Device) are splited in three:
> >> ... and btw, I know what MTP and QRD is and MTP IS NOT A PHONE. I work
> >> on this, I upstream this and it is not a phone, regardless how you call
> >> it. Just because we call our evalkit like that, does not make it a
> > phone.
> >
> > So what is it?
>
> evalkit for SoC. Just like every other NXP evalkit board is.
...products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms...
...Mobile Test Platform...
Clearly not phone related.
> >>> new-hardware-devel or whatever. No. People should use tools, not guess
> >>> the cc lists. Fix the tools if you miss any Cc.
Where did you get that "people should completely rely on tools" thing from?
"You should always copy the appropriate subsystem maintainer(s) on any patch
to code that they maintain; look through the MAINTAINERS file and the
source code revision history to see who those maintainers are. The
script scripts/get_maintainer.pl can be very useful at this step (pass paths to
your patches as arguments to scripts/get_maintainer.pl). If you cannot find a
maintainer for the subsystem you are working on, Andrew Morton
(akpm@linux-foundation.org) serves as a maintainer of last resort.
You should also normally choose at least one mailing list to receive a copy
of your patch set. linux-kernel@vger.kernel.org should be used by default
for all patches, but the volume on that list has caused a number of
developers to tune it out. Look in the MAINTAINERS file for a
subsystem-specific list; your patch will probably get more attention there.
Please do not spam unrelated lists, though.
Many kernel-related lists are hosted on vger.kernel.org; you can find a
list of them at http://vger.kernel.org/vger-lists.html. There are
kernel-related lists hosted elsewhere as well, though."
Pavel
--
I don't work for Nazis and criminals, and neither should you.
Boycott Putin, Trump, Netanyahu and Musk!
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-04 11:42 ` Pavel Machek
@ 2025-12-04 12:10 ` Krzysztof Kozlowski
2025-12-04 12:26 ` Pavel Machek
0 siblings, 1 reply; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-12-04 12:10 UTC (permalink / raw)
To: Pavel Machek
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Tengfei Fan, Qiang Yu, Manish Pandey, Ronak Raheja,
Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Prasad Kumpatla, Hangxiang Ma, Vikash Garodia
On 04/12/2025 12:42, Pavel Machek wrote:
>
>>>>>>>>> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
>>>>>>>>> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
>
>>>>>>>>> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
>>>>>>>>> and QRD (Qualcommm Reference Device) are splited in three:
>
>>>> ... and btw, I know what MTP and QRD is and MTP IS NOT A PHONE. I work
>>>> on this, I upstream this and it is not a phone, regardless how you call
>>>> it. Just because we call our evalkit like that, does not make it a
>>> phone.
>>>
>>> So what is it?
>>
>> evalkit for SoC. Just like every other NXP evalkit board is.
>
> ...products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms...
> ...Mobile Test Platform...
>
> Clearly not phone related.
so you never had it in your hands, never heard about it before, know
nothing about it, but you correct people and you claim it is "phone
related" thus some fake new rule should be followed on cc-ing
non-documented address (just git grep for it...).
I think this concludes the discussion.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-04 12:10 ` Krzysztof Kozlowski
@ 2025-12-04 12:26 ` Pavel Machek
0 siblings, 0 replies; 135+ messages in thread
From: Pavel Machek @ 2025-12-04 12:26 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Tengfei Fan, Qiang Yu, Manish Pandey, Ronak Raheja,
Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Prasad Kumpatla, Hangxiang Ma, Vikash Garodia
[-- Attachment #1: Type: text/plain, Size: 2089 bytes --]
On Thu 2025-12-04 13:10:12, Krzysztof Kozlowski wrote:
> On 04/12/2025 12:42, Pavel Machek wrote:
> >
> >>>>>>>>> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
> >>>>>>>>> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
> >
> >>>>>>>>> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
> >>>>>>>>> and QRD (Qualcommm Reference Device) are splited in three:
> >
> >>>> ... and btw, I know what MTP and QRD is and MTP IS NOT A PHONE. I work
> >>>> on this, I upstream this and it is not a phone, regardless how you call
> >>>> it. Just because we call our evalkit like that, does not make it a
> >>> phone.
> >>>
> >>> So what is it?
> >>
> >> evalkit for SoC. Just like every other NXP evalkit board is.
> >
> > ...products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms...
> > ...Mobile Test Platform...
> >
> > Clearly not phone related.
>
> so you never had it in your hands, never heard about it before, know
> nothing about it, but you correct people and you claim it is "phone
> related" thus some fake new rule should be followed on cc-ing
> non-documented address (just git grep for it...).
I have not heard of it, and that's why I want people to cc the list,
so I don't have to pick it up from lkml. There are other people on the
list, maybe not following lkml, and likely interested in chipset
OnePlus 15 is based on.
We do have guidance about cc-ing the lists, and somehow I don't see "git
grep" in those rules, nor it says "if get_maintainers does not know
about it, it does not exist". In fact, it says:
"Many kernel-related lists are hosted on vger.kernel.org; you can find a
list of them at http://vger.kernel.org/vger-lists.html. There are
kernel-related lists hosted elsewhere as well, though."
Why don't you click on the link?
Pavel
--
I don't work for Nazis and criminals, and neither should you.
Boycott Putin, Trump, Netanyahu and Musk!
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-03 18:40 ` Krzysztof Kozlowski
2025-12-03 18:41 ` Krzysztof Kozlowski
@ 2025-12-04 9:14 ` Pavel Machek
2025-12-04 10:42 ` Krzysztof Kozlowski
1 sibling, 1 reply; 135+ messages in thread
From: Pavel Machek @ 2025-12-04 9:14 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Tengfei Fan, Qiang Yu, Manish Pandey, Ronak Raheja,
Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Prasad Kumpatla, Hangxiang Ma, Vikash Garodia
[-- Attachment #1: Type: text/plain, Size: 2287 bytes --]
On Wed 2025-12-03 19:40:20, Krzysztof Kozlowski wrote:
> On 03/12/2025 19:10, Pavel Machek wrote:
> > On Wed 2025-12-03 18:31:11, Krzysztof Kozlowski wrote:
> >> On 02/12/2025 19:21, Pavel Machek wrote:
> >>> Hi!
> >>>
> >>>> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
> >>>> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
> >>>>
> >>>> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
> >>>> and QRD (Qualcommm Reference Device) are splited in three:
> >>>>
> >>>> - 1-3: MTP board boot-to-shell with basic function.
> >>>> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
> >>>> - 17-20: Multimedia features including audio, video and camss.
> >>>
> >>> Thanks for doing this. I assume there devices available with this are
> >>> quite expensive/hard to get at this point?
> >>>
> >>> Please cc phone-devel@vger.kernel.org with phone related patches.
> >>
> >> That's not even a phone, anyway contributors should not cc lists which
> >> are not relevant to the posting and not pointed out by maintainers. You
> >
> > People should Cc relevant lists, and yes, if it is called "Mobile Test
> > Platform", it is relevant to phone development.
>
>
> Almost everything in ARM64 is then relevant for "phone development".
No.
> People should use tools, not invent or try to guess whom to Cc. It's
No. People should cc relevant people / lists. Tools are tools,
submitter is responsible for getting the cc right. I believe you
should be capable of reading our patch submission guidelines yourself,
but I can find it for you if you are not.
> impossible to btw keep guessing them - you will request phone-devel,
> someone else will request desktop-devel, laptop-devel or
Desktop-devel is not kernel-related list. But yes, if
cat-picture-devel was somehow relevant because now interface to
cat-pictures changeed, it would be your responsibility to cc it.
Pavel
--
I don't work for Nazis and criminals, and neither should you.
Boycott Putin, Trump, Netanyahu and Musk!
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^ permalink raw reply [flat|nested] 135+ messages in thread* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-04 9:14 ` Pavel Machek
@ 2025-12-04 10:42 ` Krzysztof Kozlowski
2025-12-04 11:44 ` Pavel Machek
0 siblings, 1 reply; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-12-04 10:42 UTC (permalink / raw)
To: Pavel Machek
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Tengfei Fan, Qiang Yu, Manish Pandey, Ronak Raheja,
Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Prasad Kumpatla, Hangxiang Ma, Vikash Garodia
On 04/12/2025 10:14, Pavel Machek wrote:
> On Wed 2025-12-03 19:40:20, Krzysztof Kozlowski wrote:
>> On 03/12/2025 19:10, Pavel Machek wrote:
>>> On Wed 2025-12-03 18:31:11, Krzysztof Kozlowski wrote:
>>>> On 02/12/2025 19:21, Pavel Machek wrote:
>>>>> Hi!
>>>>>
>>>>>> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
>>>>>> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
>>>>>>
>>>>>> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
>>>>>> and QRD (Qualcommm Reference Device) are splited in three:
>>>>>>
>>>>>> - 1-3: MTP board boot-to-shell with basic function.
>>>>>> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
>>>>>> - 17-20: Multimedia features including audio, video and camss.
>>>>>
>>>>> Thanks for doing this. I assume there devices available with this are
>>>>> quite expensive/hard to get at this point?
>>>>>
>>>>> Please cc phone-devel@vger.kernel.org with phone related patches.
>>>>
>>>> That's not even a phone, anyway contributors should not cc lists which
>>>> are not relevant to the posting and not pointed out by maintainers. You
>>>
>>> People should Cc relevant lists, and yes, if it is called "Mobile Test
>>> Platform", it is relevant to phone development.
>>
>>
>> Almost everything in ARM64 is then relevant for "phone development".
>
> No.
>
>> People should use tools, not invent or try to guess whom to Cc. It's
>
> No. People should cc relevant people / lists. Tools are tools,
> submitter is responsible for getting the cc right. I believe you
> should be capable of reading our patch submission guidelines yourself,
> but I can find it for you if you are not.
>
>> impossible to btw keep guessing them - you will request phone-devel,
>> someone else will request desktop-devel, laptop-devel or
>
> Desktop-devel is not kernel-related list. But yes, if
> cat-picture-devel was somehow relevant because now interface to
> cat-pictures changeed, it would be your responsibility to cc it.
Maintainers decide what is relevant, not you. Just because you wanted
phone-devel list does not grant you ability to impose such rule and
claim it is relevant and people should Cc it.
No, there is no rule of Cc-ing phone-devel. No one has to do it and you
need to stop coming with the impression that it is sanctioned rule by
any platform or architecture maintainer.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-04 10:42 ` Krzysztof Kozlowski
@ 2025-12-04 11:44 ` Pavel Machek
2025-12-04 12:07 ` Krzysztof Kozlowski
0 siblings, 1 reply; 135+ messages in thread
From: Pavel Machek @ 2025-12-04 11:44 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Tengfei Fan, Qiang Yu, Manish Pandey, Ronak Raheja,
Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Prasad Kumpatla, Hangxiang Ma, Vikash Garodia
[-- Attachment #1: Type: text/plain, Size: 758 bytes --]
Hi!
> No, there is no rule of Cc-ing phone-devel. No one has to do it and you
> need to stop coming with the impression that it is sanctioned rule by
> any platform or architecture maintainer.
Yes, people need to cc relevant mailing lists, that's why we have the
lists, and that's how kernel development works. You want relevant
developers, well, to review the patch.
"You should also normally choose at least one mailing list to receive a copy
of your patch set. linux-kernel@vger.kernel.org should be used by default
for all patches, but the volume on that list has caused a number of
developers to tune it out."
Pavel
--
I don't work for Nazis and criminals, and neither should you.
Boycott Putin, Trump, Netanyahu and Musk!
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-04 11:44 ` Pavel Machek
@ 2025-12-04 12:07 ` Krzysztof Kozlowski
0 siblings, 0 replies; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-12-04 12:07 UTC (permalink / raw)
To: Pavel Machek
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Tengfei Fan, Qiang Yu, Manish Pandey, Ronak Raheja,
Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Prasad Kumpatla, Hangxiang Ma, Vikash Garodia
On 04/12/2025 12:44, Pavel Machek wrote:
> Hi!
>
>> No, there is no rule of Cc-ing phone-devel. No one has to do it and you
>> need to stop coming with the impression that it is sanctioned rule by
>> any platform or architecture maintainer.
>
> Yes, people need to cc relevant mailing lists, that's why we have the
And it was done here.
> lists, and that's how kernel development works. You want relevant
> developers, well, to review the patch.
They can review the patch because all the necessary lists were Cc-ed here.
>
> "You should also normally choose at least one mailing list to receive a copy
> of your patch set. linux-kernel@vger.kernel.org should be used by default
> for all patches, but the volume on that list has caused a number of
> developers to tune it out."
And above was fulfilled. Nothing, no single rule says some
"foo-devel-whatever" should be cc-ed. This patchset touches specific
subsystems and concept, and all these were cc-ed.
You really need to stop inventing own rules about undisclosed and hidden
phone-devel (just git grep for phone-devel).
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-02 18:21 ` Pavel Machek
2025-12-02 18:33 ` Konrad Dybcio
2025-12-03 17:31 ` Krzysztof Kozlowski
@ 2025-12-04 2:41 ` Jingyi Wang
2025-12-04 8:56 ` Pavel Machek
2 siblings, 1 reply; 135+ messages in thread
From: Jingyi Wang @ 2025-12-04 2:41 UTC (permalink / raw)
To: Pavel Machek
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Tengfei Fan, Qiang Yu,
Manish Pandey, Ronak Raheja, Jishnu Prakash, Kamal Wadhwa,
Jyothi Kumar Seerapu, Prasad Kumpatla, Hangxiang Ma,
Vikash Garodia
On 12/3/2025 2:21 AM, Pavel Machek wrote:
> Hi!
>
>> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
>> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
>>
>> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
>> and QRD (Qualcommm Reference Device) are splited in three:
>>
>> - 1-3: MTP board boot-to-shell with basic function.
>> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
>> - 17-20: Multimedia features including audio, video and camss.
>
> Thanks for doing this. I assume there devices available with this are
> quite expensive/hard to get at this point?
>
> Please cc phone-devel@vger.kernel.org with phone related patches.
>
> Best regards,
> Pavel
Hi Pavel,
The cc list is generated by tools following the list in MAINTAINERS, you can get
this series from devicetree@vger.kernel.org or linux-arm-msm@vger.kernel.org
Thanks，
Jingyi
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-04 2:41 ` Jingyi Wang
@ 2025-12-04 8:56 ` Pavel Machek
2025-12-04 9:01 ` Krzysztof Kozlowski
0 siblings, 1 reply; 135+ messages in thread
From: Pavel Machek @ 2025-12-04 8:56 UTC (permalink / raw)
To: Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Tengfei Fan, Qiang Yu,
Manish Pandey, Ronak Raheja, Jishnu Prakash, Kamal Wadhwa,
Jyothi Kumar Seerapu, Prasad Kumpatla, Hangxiang Ma,
Vikash Garodia
[-- Attachment #1: Type: text/plain, Size: 1486 bytes --]
On Thu 2025-12-04 10:41:53, Jingyi Wang wrote:
>
>
> On 12/3/2025 2:21 AM, Pavel Machek wrote:
> > Hi!
> >
> >> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
> >> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
> >>
> >> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
> >> and QRD (Qualcommm Reference Device) are splited in three:
> >>
> >> - 1-3: MTP board boot-to-shell with basic function.
> >> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
> >> - 17-20: Multimedia features including audio, video and camss.
> >
> > Thanks for doing this. I assume there devices available with this are
> > quite expensive/hard to get at this point?
> >
> > Please cc phone-devel@vger.kernel.org with phone related patches.
>
> The cc list is generated by tools following the list in MAINTAINERS, you can get
> this series from devicetree@vger.kernel.org or linux-arm-msm@vger.kernel.org
Well, tools are not smart enough to generate good Cc list in this
case, so please do the cc manually. (I don't think they can be
improved easily, as it is not clear when code is phone-related from
the filename).
Best regards,
Pavel
--
I don't work for Nazis and criminals, and neither should you.
Boycott Putin, Trump, Netanyahu and Musk!
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-04 8:56 ` Pavel Machek
@ 2025-12-04 9:01 ` Krzysztof Kozlowski
2025-12-04 9:06 ` Pavel Machek
0 siblings, 1 reply; 135+ messages in thread
From: Krzysztof Kozlowski @ 2025-12-04 9:01 UTC (permalink / raw)
To: Pavel Machek, Jingyi Wang
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Tengfei Fan, Qiang Yu,
Manish Pandey, Ronak Raheja, Jishnu Prakash, Kamal Wadhwa,
Jyothi Kumar Seerapu, Prasad Kumpatla, Hangxiang Ma,
Vikash Garodia
On 04/12/2025 09:56, Pavel Machek wrote:
> On Thu 2025-12-04 10:41:53, Jingyi Wang wrote:
>>
>>
>> On 12/3/2025 2:21 AM, Pavel Machek wrote:
>>> Hi!
>>>
>>>> Introduce the Device Tree for the recently announced Snapdragon SoC from Qualcomm:
>>>> https://www.qualcomm.com/products/mobile/snapdragon/smartphones/snapdragon-8-series-mobile-platforms/snapdragon-8-elite-gen-5
>>>>
>>>> Bindings and base Device Tree for the Kaanapali SoC, MTP (Mobile Test Platform)
>>>> and QRD (Qualcommm Reference Device) are splited in three:
>>>>
>>>> - 1-3: MTP board boot-to-shell with basic function.
>>>> - 4-16: More feature including PCIE, sdcard, usb, DSPs, PMIC related, tsense, bus, crypto etc. Add QRD board support.
>>>> - 17-20: Multimedia features including audio, video and camss.
>>>
>>> Thanks for doing this. I assume there devices available with this are
>>> quite expensive/hard to get at this point?
>>>
>>> Please cc phone-devel@vger.kernel.org with phone related patches.
>>
>> The cc list is generated by tools following the list in MAINTAINERS, you can get
>> this series from devicetree@vger.kernel.org or linux-arm-msm@vger.kernel.org
>
> Well, tools are not smart enough to generate good Cc list in this
> case, so please do the cc manually. (I don't think they can be
> improved easily, as it is not clear when code is phone-related from
> the filename).
>
You cannot impose additional manual rules, just because you want your
list to be cc-ed. If you want that list to be cc-ed, you need to improve
the tools, not use excuse they are not good enough and push this task to
contributors.
Contributors for every standard patchset (there are only known 2
exceptions for arm soc development and foo-devel is not one of them)
must only use the tools and not cc phone-devel manually.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 135+ messages in thread
* Re: [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree
2025-12-04 9:01 ` Krzysztof Kozlowski
@ 2025-12-04 9:06 ` Pavel Machek
0 siblings, 0 replies; 135+ messages in thread
From: Pavel Machek @ 2025-12-04 9:06 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Jingyi Wang, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Tengfei Fan, Qiang Yu, Manish Pandey, Ronak Raheja,
Jishnu Prakash, Kamal Wadhwa, Jyothi Kumar Seerapu,
Prasad Kumpatla, Hangxiang Ma, Vikash Garodia
[-- Attachment #1: Type: text/plain, Size: 1067 bytes --]
Hi!
> >>> Please cc phone-devel@vger.kernel.org with phone related patches.
> >>
> >> The cc list is generated by tools following the list in MAINTAINERS, you can get
> >> this series from devicetree@vger.kernel.org or linux-arm-msm@vger.kernel.org
> >
> > Well, tools are not smart enough to generate good Cc list in this
> > case, so please do the cc manually. (I don't think they can be
> > improved easily, as it is not clear when code is phone-related from
> > the filename).
>
> You cannot impose additional manual rules, just because you want
"You have to cc relevant list" is the rule that predates
automation. Just because automation does not work well in this case
does not mean you are exempt.
> Contributors for every standard patchset (there are only known 2
> exceptions for arm soc development and foo-devel is not one of them)
> must only use the tools and not cc phone-devel manually.
Untrue.
Pavel
--
I don't work for Nazis and criminals, and neither should you.
Boycott Putin, Trump, Netanyahu and Musk!
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^ permalink raw reply [flat|nested] 135+ messages in thread