From mboxrd@z Thu Jan 1 00:00:00 1970 From: Krzysztof Kozlowski Subject: Re: [PATCH v1 37/50] ARM: dts: exynos: change parent and rate of bus_fsys in Exynos5422 Date: Wed, 17 Jul 2019 12:45:12 +0200 Message-ID: References: <20190715124417.4787-1-l.luba@partner.samsung.com> <20190715124417.4787-38-l.luba@partner.samsung.com> <2fe2e840-f4b2-773b-7d92-4ffb8502d4e6@partner.samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: <2fe2e840-f4b2-773b-7d92-4ffb8502d4e6@partner.samsung.com> Sender: linux-kernel-owner@vger.kernel.org To: Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "linux-samsung-soc@vger.kernel.org" , linux-clk@vger.kernel.org, mturquette@baylibre.com, sboyd@kernel.org, =?UTF-8?B?QmFydMWCb21pZWogxbtvxYJuaWVya2lld2ljeg==?= , kgene@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, Chanwoo Choi , kyungmin.park@samsung.com, Andrzej Hajda , Marek Szyprowski , s.nawrocki@samsung.com, myungjoo.ham@samsung.com List-Id: devicetree@vger.kernel.org On Wed, 17 Jul 2019 at 12:39, Lukasz Luba wrote: > >> > >> &bus_fsys { > >> devfreq = <&bus_wcore>; > >> + assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS>, > >> + <&clock CLK_DOUT_ACLK200_FSYS>, > >> + <&clock CLK_FOUT_DPLL>; > >> + assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>; > >> + assigned-clock-rates = <0>, <240000000>,<1200000000>; > > > > Here and in all other patches: > > I am not entirely sure that this should be here. It looks like > > property of the SoC. Do we expect that buses will be configured to > > different clock rates between different boards? Since the OPP tables > > are shared (they are property of the SoC, not board) then I would > > assume that default frequency is shared as well. > These clocks they all relay on some bootloader configuration. It depends > which version of the bootloader you have, then you might get different > default configuration in the clocks. I do not agree here. This configuration is not dependent on bootloader. Although one bootloader might set the clocks to X and other to Y, but still you provide here valid configuration setting them, e.g. to Y (or to Z). What bootloader set before does not matter because you always override it. > The pattern of changing the parent > or even rate is known in the DT files (or I am missing something). > When you grep for it, you get 168 hits (38 for exynos*): > git grep -n "assigned-clock-rates" ./arch/arm/boot/dts/ | wc -l Yeah, and if you grep per type you got: DTSI: 114 DTS: 54 so what do you want to say? My thinking is that all the boards have buses configured to the same initial frequency. I am not questioning the use of assigned-clock-rates at all. Just the place... BR, Krzysztof