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AJvYcCW82iyL6B5Xg3ayQylCRGu6kICc/79C8q1kviEcJNzhstcrKnjDNTLSzrHNr19Jmr8XGmCVrl8E9Cl5@vger.kernel.org X-Gm-Message-State: AOJu0Yy9vyovygSNR7FEvz/Izsb2TJuIwDtkYpDj4rQx1xjiLbDNKsGX o8gGC6lvi0AiJY77MBy/4Fwvk8rzolQ7Xfsyb0fzxyl1xsBZta+NDTS0CFdgHoy7GvFafFA7X3v qk7+U3ctfQqY6jfVq8K6MTYFNdufKKsWDG35lY1fsbBMYCh+yIPl1tnH4vRAONZ8k6L3Nv9WKI1 O7V6pRnTbVaK6Nn4TkoAzbMYIgD2tq1n4xoSJ9XtHe14vWIBPMFQ== X-Received: by 2002:a05:6871:1c7:b0:277:fd73:8f82 with SMTP id 586e51a60fabf-28710c28d08mr1801229fac.45.1727427998420; Fri, 27 Sep 2024 02:06:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGv+HoVG+UamQzP9HYGm4dvtX0uDQArn9ex/l2o6/iZbKaH7H7PMWWqDndToxE25AX6dEyIqQ8K4thbHVn/x+E= X-Received: by 2002:a05:6871:1c7:b0:277:fd73:8f82 with SMTP id 586e51a60fabf-28710c28d08mr1801204fac.45.1727427998028; Fri, 27 Sep 2024 02:06:38 -0700 (PDT) Received: from 348282803490 named unknown by gmailapi.google.com with HTTPREST; Fri, 27 Sep 2024 02:06:37 -0700 From: Emil Renner Berthing In-Reply-To: References: <20240926-th1520-dwmac-v2-0-f34f28ad1dc9@tenstorrent.com> <20240926-th1520-dwmac-v2-3-f34f28ad1dc9@tenstorrent.com> <3e26f580-bc5d-448e-b5bd-9b607c33702b@lunn.ch> <0b49b681-2289-412a-8969-d134ffcfb7fc@lunn.ch> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Date: Fri, 27 Sep 2024 02:06:37 -0700 Message-ID: Subject: Re: [PATCH v2 3/3] riscv: dts: thead: Add TH1520 ethernet nodes To: Drew Fustini , Andrew Lunn Cc: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Jisheng Zhang , Maxime Coquelin , Emil Renner Berthing , Drew Fustini , Guo Ren , Fu Wei , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Drew Fustini wrote: > On Thu, Sep 26, 2024 at 09:30:32PM +0200, Andrew Lunn wrote: > > On Thu, Sep 26, 2024 at 12:13:06PM -0700, Drew Fustini wrote: > > > On Thu, Sep 26, 2024 at 08:39:29PM +0200, Andrew Lunn wrote: > > > > > +&mdio0 { > > > > > + phy0: ethernet-phy@1 { > > > > > + reg = <1>; > > > > > + }; > > > > > + > > > > > + phy1: ethernet-phy@2 { > > > > > + reg = <2>; > > > > > + }; > > > > > +}; > > > > > > > > Two PHYs on one bus... > > > > > > Thanks for pointing this out. I will move phy1 to mdio1. > > > > ??? > > > > Are you saying the two PHYs are not on the same bus? > > Sorry, this is my first time working on an Ethernet driver and I > misunderstood. > > Sipeed only shares the schematic of the baseboard for the LPi4a [1]. > There are pages for GMAC Ethernet0 and GMAC Ethernet1. Each shows 4 MDIO > differential pairs going into a SG4301G transformer. > > I believe that RTL8211F-CG phy chips are on the LM4A SoM board which > contains the TH1520 SoC. Unfortunately, Sipeed does not provide a > schematic of the SoM so its hard for me to inspect how the phy chips are > wired up. > > Vendor kernel [2] that Sipeed uses has: > > mdio0 { > #address-cells = <1>; > #size-cells = <0>; > compatible = "snps,dwmac-mdio"; > > phy_88E1111_0: ethernet-phy@0 { > reg = <0x1>; > }; > > phy_88E1111_1: ethernet-phy@1 { > reg = <0x2>; > }; > }; > > so I think that does mean they are on the same MDIO bus. It depends how you look at it. The SoC has two MACs and they can both control their own MDIO bus. However MDIO of both MACs are pinmux'ed to the same pins on the SoC. So the solution above just mux the pins to GMAC0 and let that control both PHYs. Alternatively I guess one could let each GMAC control their own phy on their own MDIO bus and then switch pinmux settings everytime you need to need to talk to one or the other. /Emil