From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
To: "Minda Chen" <minda.chen@starfivetech.com>,
"Daire McNamara" <daire.mcnamara@microchip.com>,
"Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Emil Renner Berthing" <emil.renner.berthing@canonical.com>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-pci@vger.kernel.org,
"Pali Rohár" <pali@kernel.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Mason Huo" <mason.huo@starfivetech.com>,
"Leyfoon Tan" <leyfoon.tan@starfivetech.com>,
"Kevin Xie" <kevin.xie@starfivetech.com>
Subject: Re: [PATCH v6 19/19] riscv: dts: starfive: add PCIe dts configuration for JH7110
Date: Sun, 17 Sep 2023 15:20:23 -0700 [thread overview]
Message-ID: <CAJM55Z8ES9ip53R14OoKVphEr14BFOwk88DCZEp13oGrnPkdvg@mail.gmail.com> (raw)
In-Reply-To: <20230915102243.59775-20-minda.chen@starfivetech.com>
Minda Chen wrote:
> Add PCIe dts configuraion for JH7110 SoC platform.
>
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> ---
> .../jh7110-starfive-visionfive-2.dtsi | 63 +++++++++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 88 +++++++++++++++++++
> 2 files changed, 151 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index d79f94432b27..8c84852f1c06 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -402,6 +402,53 @@
> };
> };
>
> + pcie0_pins: pcie0-0 {
> + wake-pins {
> + pinmux = <GPIOMUX(32, GPOUT_LOW,
> + GPOEN_DISABLE,
> + GPI_NONE)>;
> + bias-pull-up;
> + drive-strength = <2>;
> + input-enable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + clkreq-pins {
> + pinmux = <GPIOMUX(27, GPOUT_LOW,
> + GPOEN_DISABLE,
> + GPI_NONE)>;
> + bias-pull-down;
> + drive-strength = <2>;
> + input-enable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + };
> +
> + pcie1_pins: pcie1-0 {
> + wake-pins {
> + pinmux = <GPIOMUX(21, GPOUT_LOW,
> + GPOEN_DISABLE,
> + GPI_NONE)>;
> + bias-pull-up;
> + drive-strength = <2>;
> + input-enable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> +
> + clkreq-pins {
> + pinmux = <GPIOMUX(29, GPOUT_LOW,
> + GPOEN_DISABLE,
> + GPI_NONE)>;
> + bias-pull-down;
> + drive-strength = <2>;
> + input-enable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + };
> +
> spi0_pins: spi0-0 {
> mosi-pins {
> pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
> @@ -499,6 +546,22 @@
> };
> };
>
> +&pcie0 {
> + pinctrl-names = "default";
> + perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
> + pinctrl-0 = <&pcie0_pins>;
> + phys = <&pciephy0>;
> + status = "okay";
> +};
> +
> +&pcie1 {
> + pinctrl-names = "default";
> + perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
> + pinctrl-0 = <&pcie1_pins>;
> + phys = <&pciephy1>;
> + status = "okay";
> +};
These nodes are out of place. The order is
- root node
- clocks sorted alphabetically
- other node references sorted alphabetically
> &tdm {
> pinctrl-names = "default";
> pinctrl-0 = <&tdm_pins>;
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index e85464c328d0..97fe5a242d60 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -1045,5 +1045,93 @@
> #reset-cells = <1>;
> power-domains = <&pwrc JH7110_PD_VOUT>;
> };
> +
> + pcie0: pcie@940000000 {
> + compatible = "starfive,jh7110-pcie";
> + reg = <0x9 0x40000000 0x0 0x1000000>,
> + <0x0 0x2b000000 0x0 0x100000>;
> + reg-names = "cfg", "apb";
> + linux,pci-domain = <0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
> + <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
> + interrupts = <56>;
> + interrupt-parent = <&plic>;
Is interrupt-parent not inherited from the soc bus like other peripherals?
> + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
> + <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
> + <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
> + <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
> + msi-controller;
> + device_type = "pci";
> + starfive,stg-syscon = <&stg_syscon>;
> + bus-range = <0x0 0xff>;
> + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
> + <&stgcrg JH7110_STGCLK_PCIE0_TL>,
> + <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
> + <&stgcrg JH7110_STGCLK_PCIE0_APB>;
> + clock-names = "noc", "tl", "axi_mst0", "apb";
> + resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
> + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
> + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
> + <&stgcrg JH7110_STGRST_PCIE0_BRG>,
> + <&stgcrg JH7110_STGRST_PCIE0_CORE>,
> + <&stgcrg JH7110_STGRST_PCIE0_APB>;
> + reset-names = "mst0", "slv0", "slv", "brg",
> + "core", "apb";
> + status = "disabled";
> +
> + pcie_intc0: interrupt-controller {
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +
> + pcie1: pcie@9c0000000 {
> + compatible = "starfive,jh7110-pcie";
> + reg = <0x9 0xc0000000 0x0 0x1000000>,
> + <0x0 0x2c000000 0x0 0x100000>;
> + reg-names = "cfg", "apb";
> + linux,pci-domain = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
> + <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
> + interrupts = <57>;
> + interrupt-parent = <&plic>;
ditto.
> + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
> + <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>,
> + <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>,
> + <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>;
> + msi-controller;
> + device_type = "pci";
> + starfive,stg-syscon = <&stg_syscon>;
> + bus-range = <0x0 0xff>;
> + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
> + <&stgcrg JH7110_STGCLK_PCIE1_TL>,
> + <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
> + <&stgcrg JH7110_STGCLK_PCIE1_APB>;
> + clock-names = "noc", "tl", "axi_mst0", "apb";
> + resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
> + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
> + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
> + <&stgcrg JH7110_STGRST_PCIE1_BRG>,
> + <&stgcrg JH7110_STGRST_PCIE1_CORE>,
> + <&stgcrg JH7110_STGRST_PCIE1_APB>;
> + reset-names = "mst0", "slv0", "slv", "brg",
> + "core", "apb";
> + status = "disabled";
> +
> + pcie_intc1: interrupt-controller {
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> };
> };
> --
> 2.17.1
next prev parent reply other threads:[~2023-09-17 22:20 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-15 10:22 [PATCH v6 0/19] Refactoring Microchip PCIe driver and add StarFive PCIe Minda Chen
2023-09-15 10:22 ` [PATCH v6 01/19] dt-bindings: PCI: Add PLDA XpressRICH PCIe host common properties Minda Chen
2023-09-15 10:22 ` [PATCH v6 02/19] PCI: microchip: Move pcie-microchip-host.c to plda directory Minda Chen
2023-09-16 0:09 ` Conor Dooley
2023-09-17 8:49 ` Minda Chen
2023-09-15 10:22 ` [PATCH v6 03/19] PCI: microchip: Move PLDA IP register macros to pcie-plda.h Minda Chen
2023-09-15 10:22 ` [PATCH v6 04/19] PCI: microchip: Rename data structure Minda Chen
2023-09-15 10:22 ` [PATCH v6 05/19] PCI: microchip: Rename two setup functions Minda Chen
2023-09-15 10:22 ` [PATCH v6 06/19] PCI: microchip: Change the argument of plda_pcie_setup_iomems() Minda Chen
2023-09-15 10:22 ` [PATCH v6 07/19] PCI: plda: Move the setup functions to pcie-plda-host.c Minda Chen
2023-09-17 22:45 ` Emil Renner Berthing
2023-09-22 10:42 ` Minda Chen
2023-09-15 10:22 ` [PATCH v6 08/19] PCI: plda: Add event interrupt codes and IRQ domain ops Minda Chen
2023-09-16 0:11 ` Conor Dooley
2023-09-21 15:08 ` Bjorn Helgaas
2023-09-22 1:23 ` Minda Chen
2023-09-15 10:22 ` [PATCH v6 09/19] PCI: microchip: Rename interrupt related functions Minda Chen
2023-09-15 10:22 ` [PATCH v6 10/19] PCI: microchip: Add num_events field to struct plda_pcie_rp Minda Chen
2023-09-15 10:22 ` [PATCH v6 11/19] PCI: microchip: Add request_event_irq() callback function Minda Chen
2023-09-15 10:22 ` [PATCH v6 12/19] PCI: microchip: Add INTx and MSI event num to struct plda_event Minda Chen
2023-09-15 10:22 ` [PATCH v6 13/19] PCI: microchip: Add get_events() callback function Minda Chen
2023-09-15 10:22 ` [PATCH v6 14/19] PCI: microchip: Add event IRQ domain ops to plda_event struct Minda Chen
2023-09-15 10:22 ` [PATCH v6 15/19] PCI: microchip: Move IRQ functions to pcie-plda-host.c Minda Chen
2023-09-15 10:22 ` [PATCH v6 16/19] PCI: plda: Set plda_event_handler() to static Minda Chen
2023-09-15 10:22 ` [PATCH v6 17/19] dt-bindings: PCI: Add StarFive JH7110 PCIe controller Minda Chen
2023-09-15 10:22 ` [PATCH v6 18/19] PCI: starfive: Add " Minda Chen
2023-09-17 22:13 ` Emil Renner Berthing
2023-09-18 10:52 ` Emil Renner Berthing
2023-09-19 11:17 ` Minda Chen
2023-09-19 11:34 ` Emil Renner Berthing
2023-09-21 10:50 ` Minda Chen
2023-09-21 11:05 ` Emil Renner Berthing
2023-09-15 10:22 ` [PATCH v6 19/19] riscv: dts: starfive: add PCIe dts configuration for JH7110 Minda Chen
2023-09-16 0:07 ` Conor Dooley
2023-09-17 8:49 ` Minda Chen
2023-09-17 22:20 ` Emil Renner Berthing [this message]
2023-09-15 10:33 ` [PATCH v6 0/19] Refactoring Microchip PCIe driver and add StarFive PCIe Minda Chen
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