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AJvYcCVoEQ77V/IrAPIm0OkyigQgDdNvEvGubDCe8ZIsuEmz3XAnCldeF5amV51kyblPe7tU0ACZyXQuitKg@vger.kernel.org X-Gm-Message-State: AOJu0YzECXyEukLznh6PQX9RC7xGh+ItWzXiZb+KHFfA1faiWNbgCs6d 0rVTBCnIZ5ga68BHts1pcEPQ9uafwmUeFmEgHIVuhfiFCL1jReLj5fag7A1/UIq0rtgZD/iUbB4 pZFmLCruj6xHLMKrye8UIX41WkzHXfahEcGB+0sccM7C/4225kec9r0aaKU8v9L5DK+l289o5XU M3WYf7ZVgfAzz/gnN+Gmim1LXVCEIW03v7OUb5vdTYWbqnBXQrbg== X-Received: by 2002:a05:6871:a6aa:b0:287:541:c60 with SMTP id 586e51a60fabf-287889aa2b0mr2470203fac.1.1727888372575; Wed, 02 Oct 2024 09:59:32 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGqcxKIhFuRh+HBH4VGMynHVutdUUyzDUM77wrN93IMmYcomKUkacOGnkCdDFPa2rdTrgDyhXCZk9+ZWOlwbms= X-Received: by 2002:a05:6871:a6aa:b0:287:541:c60 with SMTP id 586e51a60fabf-287889aa2b0mr2470156fac.1.1727888372149; Wed, 02 Oct 2024 09:59:32 -0700 (PDT) Received: from 348282803490 named unknown by gmailapi.google.com with HTTPREST; Wed, 2 Oct 2024 09:59:31 -0700 From: Emil Renner Berthing In-Reply-To: <20240911-xtheadvector-v10-10-8d3930091246@rivosinc.com> References: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> <20240911-xtheadvector-v10-10-8d3930091246@rivosinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Date: Wed, 2 Oct 2024 09:59:31 -0700 Message-ID: Subject: Re: [PATCH v10 10/14] riscv: hwprobe: Add thead vendor extension probing To: Charlie Jenkins , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Charlie Jenkins wrote: > Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which > allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR > vendor extension. > > This new key will allow userspace code to probe for which thead vendor > extensions are supported. This API is modeled to be consistent with > RISCV_HWPROBE_KEY_IMA_EXT_0. The bitmask returned will have each bit > corresponding to a supported thead vendor extension of the cpumask set. > Just like RISCV_HWPROBE_KEY_IMA_EXT_0, this allows a userspace program > to determine all of the supported thead vendor extensions in one call. > > Signed-off-by: Charlie Jenkins > Reviewed-by: Evan Green > --- > arch/riscv/include/asm/hwprobe.h | 3 +- > .../include/asm/vendor_extensions/thead_hwprobe.h | 19 +++++++++++ > .../include/asm/vendor_extensions/vendor_hwprobe.h | 37 ++++++++++++++++++++++ > arch/riscv/include/uapi/asm/hwprobe.h | 3 +- > arch/riscv/include/uapi/asm/vendor/thead.h | 3 ++ > arch/riscv/kernel/sys_hwprobe.c | 5 +++ > arch/riscv/kernel/vendor_extensions/Makefile | 1 + > .../riscv/kernel/vendor_extensions/thead_hwprobe.c | 19 +++++++++++ > 8 files changed, 88 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h > index ef01c182af2b..6148e1eab64c 100644 > --- a/arch/riscv/include/asm/hwprobe.h > +++ b/arch/riscv/include/asm/hwprobe.h > @@ -1,6 +1,6 @@ > /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > /* > - * Copyright 2023 Rivos, Inc > + * Copyright 2023-2024 Rivos, Inc > */ > > #ifndef _ASM_HWPROBE_H > @@ -21,6 +21,7 @@ static inline bool hwprobe_key_is_bitmask(__s64 key) > case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: > case RISCV_HWPROBE_KEY_IMA_EXT_0: > case RISCV_HWPROBE_KEY_CPUPERF_0: > + case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: > return true; > } > > diff --git a/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h b/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h > new file mode 100644 > index 000000000000..65a9c5612466 > --- /dev/null > +++ b/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h > @@ -0,0 +1,19 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H > +#define _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H > + > +#include > + > +#include > + > +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD > +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpumask *cpus); > +#else > +static inline void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, > + const struct cpumask *cpus) > +{ > + pair->value = 0; > +} > +#endif > + > +#endif > diff --git a/arch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h b/arch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h > new file mode 100644 > index 000000000000..6b9293e984a9 > --- /dev/null > +++ b/arch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h > @@ -0,0 +1,37 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright 2024 Rivos, Inc > + */ > + > +#ifndef _ASM_RISCV_SYS_HWPROBE_H > +#define _ASM_RISCV_SYS_HWPROBE_H > + > +#include > + > +#define VENDOR_EXT_KEY(ext) \ > + do { \ > + if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_VENDOR_EXT_##ext)) \ > + pair->value |= RISCV_HWPROBE_VENDOR_EXT_##ext; \ > + else \ > + missing |= RISCV_HWPROBE_VENDOR_EXT_##ext; \ > + } while (false) > + > +/* > + * Loop through and record extensions that 1) anyone has, and 2) anyone > + * doesn't have. > + * > + * _extension_checks is an arbitrary C block to set the values of pair->value > + * and missing. It should be filled with VENDOR_EXT_KEY expressions. > + */ > +#define VENDOR_EXTENSION_SUPPORTED(pair, cpus, per_hart_vendor_bitmap, _extension_checks) \ > + do { \ > + int cpu; \ > + u64 missing = 0; \ > + for_each_cpu(cpu, (cpus)) { \ > + struct riscv_isavendorinfo *isainfo = &(per_hart_vendor_bitmap)[cpu]; \ > + _extension_checks \ > + } \ > + (pair)->value &= ~missing; \ > + } while (false) \ > + > +#endif /* _ASM_RISCV_SYS_HWPROBE_H */ > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > index b706c8e47b02..452d0b84f17f 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -1,6 +1,6 @@ > /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > /* > - * Copyright 2023 Rivos, Inc > + * Copyright 2023-2024 Rivos, Inc > */ > > #ifndef _UAPI_ASM_HWPROBE_H > @@ -82,6 +82,7 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 > #define RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS 7 > #define RISCV_HWPROBE_KEY_TIME_CSR_FREQ 8 > +#define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 9 > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ I wanted to try this patchset on my Nezha board, but rebasing on v6.11 this conflicts with c42e2f076769 ("RISC-V: hwprobe: Add MISALIGNED_PERF key") While fixing it up I bumped the RISCV_HWPROBE_MAX_KEY as the comment above told me to do, but now I notice you don't do that in this patch. Is that a bug or am I misunderstanding something? /Emil > > /* Flags */ > diff --git a/arch/riscv/include/uapi/asm/vendor/thead.h b/arch/riscv/include/uapi/asm/vendor/thead.h > new file mode 100644 > index 000000000000..43790ebe5faf > --- /dev/null > +++ b/arch/riscv/include/uapi/asm/vendor/thead.h > @@ -0,0 +1,3 @@ > +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > + > +#define RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR (1 << 0) > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c > index 8d1b5c35d2a7..5a3dc8e66c85 100644 > --- a/arch/riscv/kernel/sys_hwprobe.c > +++ b/arch/riscv/kernel/sys_hwprobe.c > @@ -15,6 +15,7 @@ > #include > #include > #include > +#include > #include > > > @@ -241,6 +242,10 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, > pair->value = riscv_timebase; > break; > > + case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: > + hwprobe_isa_vendor_ext_thead_0(pair, cpus); > + break; > + > /* > * For forward compatibility, unknown keys don't fail the whole > * call, but get their element key set to -1 and value set to 0 > diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kernel/vendor_extensions/Makefile > index 353522cb3bf0..866414c81a9f 100644 > --- a/arch/riscv/kernel/vendor_extensions/Makefile > +++ b/arch/riscv/kernel/vendor_extensions/Makefile > @@ -2,3 +2,4 @@ > > obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) += andes.o > obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead.o > +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead_hwprobe.o > diff --git a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c > new file mode 100644 > index 000000000000..2eba34011786 > --- /dev/null > +++ b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c > @@ -0,0 +1,19 @@ > +// SPDX-License-Identifier: GPL-2.0-only > + > +#include > +#include > +#include > + > +#include > +#include > + > +#include > +#include > + > +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpumask *cpus) > +{ > + VENDOR_EXTENSION_SUPPORTED(pair, cpus, > + riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap, { > + VENDOR_EXT_KEY(XTHEADVECTOR); > + }); > +} > > -- > 2.45.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv