From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
To: Hal Feng <hal.feng@starfivetech.com>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
Conor Dooley <conor@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Ben Dooks <ben.dooks@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Linus Walleij <linus.walleij@linaro.org>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 6/8] riscv: dts: starfive: Add initial StarFive JH7110 device tree
Date: Fri, 18 Nov 2022 18:41:41 +0100 [thread overview]
Message-ID: <CAJM55Z9PXVLfFTPuyELR4ov22ENfEXZfJAJdLgURA+R4mcH_eg@mail.gmail.com> (raw)
In-Reply-To: <20221118011714.70877-7-hal.feng@starfivetech.com>
On Fri, 18 Nov 2022 at 02:17, Hal Feng <hal.feng@starfivetech.com> wrote:
>
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add initial device tree for the JH7110 RISC-V SoC by StarFive
> Technology Ltd.
>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 437 +++++++++++++++++++++++
> 1 file changed, 437 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> new file mode 100644
> index 000000000000..c22e8f1d2640
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -0,0 +1,437 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include <dt-bindings/clock/starfive-jh7110.h>
> +#include <dt-bindings/reset/starfive-jh7110.h>
> +
> +/ {
> + compatible = "starfive,jh7110";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + S76_0: cpu@0 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <0>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <8192>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <16384>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imac";
> + tlb-split;
> + status = "disabled";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + U74_1: cpu@1 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <1>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> +
> + cpu1_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + U74_2: cpu@2 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <2>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> +
> + cpu2_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + U74_3: cpu@3 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <3>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> +
> + cpu3_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + U74_4: cpu@4 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <4>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> +
> + cpu4_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&S76_0>;
> + };
> +
> + core1 {
> + cpu = <&U74_1>;
> + };
> +
> + core2 {
> + cpu = <&U74_2>;
> + };
> +
> + core3 {
> + cpu = <&U74_3>;
> + };
> +
> + core4 {
> + cpu = <&U74_4>;
> + };
> + };
> + };
> + };
> +
> + osc: osc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + clk_rtc: clk_rtc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + gmac0_rmii_refin: gmac0_rmii_refin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + gmac0_rgmii_rxin: gmac0_rgmii_rxin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + gmac1_rmii_refin: gmac1_rmii_refin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + gmac1_rgmii_rxin: gmac1_rgmii_rxin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + i2stx_bclk_ext: i2stx_bclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + i2stx_lrck_ext: i2stx_lrck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + i2srx_bclk_ext: i2srx_bclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + i2srx_lrck_ext: i2srx_lrck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + tdm_ext: tdm_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + mclk_ext: mclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + soc {
Please sort these nodes after their address like the jh7100.dtsi.
That is sort the nodes after @<number>.
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clint: clint@2000000 {
> + compatible = "starfive,jh7110-clint", "sifive,clint0";
> + reg = <0x0 0x2000000 0x0 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> + <&cpu1_intc 3>, <&cpu1_intc 7>,
> + <&cpu2_intc 3>, <&cpu2_intc 7>,
> + <&cpu3_intc 3>, <&cpu3_intc 7>,
> + <&cpu4_intc 3>, <&cpu4_intc 7>;
> + };
> +
> + plic: plic@c000000 {
> + compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
> + reg = <0x0 0xc000000 0x0 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>,
> + <&cpu1_intc 11>, <&cpu1_intc 9>,
> + <&cpu2_intc 11>, <&cpu2_intc 9>,
> + <&cpu3_intc 11>, <&cpu3_intc 9>,
> + <&cpu4_intc 11>, <&cpu4_intc 9>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + #address-cells = <0>;
> + riscv,ndev = <136>;
> + };
> +
> + ccache: cache-controller@2010000 {
> + compatible = "starfive,jh7110-ccache", "cache";
> + reg = <0x0 0x2010000 0x0 0x4000>;
> + interrupts = <1>, <3>, <4>, <2>;
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-sets = <2048>;
> + cache-size = <2097152>;
> + cache-unified;
> + };
> +
> + syscrg: clock-controller@13020000 {
> + compatible = "starfive,jh7110-syscrg";
> + reg = <0x0 0x13020000 0x0 0x10000>;
> + clocks = <&osc>, <&gmac1_rmii_refin>,
> + <&gmac1_rgmii_rxin>,
> + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
> + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
> + <&tdm_ext>, <&mclk_ext>;
> + clock-names = "osc", "gmac1_rmii_refin",
> + "gmac1_rgmii_rxin",
> + "i2stx_bclk_ext", "i2stx_lrck_ext",
> + "i2srx_bclk_ext", "i2srx_lrck_ext",
> + "tdm_ext", "mclk_ext";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + aoncrg: clock-controller@17000000 {
> + compatible = "starfive,jh7110-aoncrg";
> + reg = <0x0 0x17000000 0x0 0x10000>;
> + clocks = <&osc>, <&clk_rtc>,
> + <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
> + <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
> + <&syscrg JH7110_SYSCLK_APB_BUS_FUNC>,
> + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>;
> + clock-names = "osc", "clk_rtc", "gmac0_rmii_refin",
> + "gmac0_rgmii_rxin", "stg_axiahb",
> + "apb_bus_func", "gmac0_gtxclk";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + gpio: gpio@13040000 {
> + compatible = "starfive,jh7110-sys-pinctrl";
> + reg = <0x0 0x13040000 0x0 0x10000>;
> + reg-names = "control";
> + clocks = <&syscrg JH7110_SYSCLK_IOMUX>;
> + resets = <&syscrg JH7110_SYSRST_IOMUX>;
> + interrupts = <86>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + gpioa: gpio@17020000 {
> + compatible = "starfive,jh7110-aon-pinctrl";
> + reg = <0x0 0x17020000 0x0 0x10000>;
> + reg-names = "control";
> + resets = <&aoncrg JH7110_AONRST_AON_IOMUX>;
> + interrupts = <85>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + uart0: serial@10000000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x10000000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
> + <&syscrg JH7110_SYSCLK_UART0_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg JH7110_SYSRST_UART0_APB>;
> + interrupts = <32>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart1: serial@10010000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x10010000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
> + <&syscrg JH7110_SYSCLK_UART1_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg JH7110_SYSRST_UART1_APB>;
> + interrupts = <33>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart2: serial@10020000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x10020000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
> + <&syscrg JH7110_SYSCLK_UART2_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg JH7110_SYSRST_UART2_APB>;
> + interrupts = <34>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart3: serial@12000000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x12000000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
> + <&syscrg JH7110_SYSCLK_UART3_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg JH7110_SYSRST_UART3_APB>;
> + interrupts = <45>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart4: serial@12010000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x12010000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
> + <&syscrg JH7110_SYSCLK_UART4_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg JH7110_SYSRST_UART4_APB>;
> + interrupts = <46>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart5: serial@12020000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x12020000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
> + <&syscrg JH7110_SYSCLK_UART5_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg JH7110_SYSRST_UART5_APB>;
> + interrupts = <47>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> + };
> +};
> --
> 2.38.1
>
next prev parent reply other threads:[~2022-11-18 17:42 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-18 1:17 [PATCH v2 0/8] Basic device tree support for StarFive JH7110 RISC-V SoC Hal Feng
2022-11-18 1:17 ` [PATCH v2 1/8] dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive2 board Hal Feng
2022-11-18 11:31 ` Conor Dooley
2022-11-18 13:13 ` Krzysztof Kozlowski
2022-11-18 17:28 ` Emil Renner Berthing
[not found] ` <202211190418.2AJ4ImtE072425@SH1-CSMTP-DB111.sundns.com>
2022-11-24 1:57 ` Hal Feng
[not found] ` <202211190418.2AJ4IQjc072382@SH1-CSMTP-DB111.sundns.com>
2022-11-24 5:56 ` Hal Feng
2022-11-24 9:20 ` Emil Renner Berthing
2022-11-24 9:50 ` Hal Feng
2022-11-18 1:17 ` [PATCH v2 2/8] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng
2022-11-18 11:32 ` Conor Dooley
2022-11-18 1:17 ` [PATCH v2 3/8] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng
2022-11-18 11:32 ` Conor Dooley
2022-11-18 1:17 ` [PATCH v2 4/8] dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC Hal Feng
2022-11-18 11:37 ` Conor Dooley
2022-11-18 11:39 ` Conor Dooley
2022-11-22 8:40 ` Hal Feng
2022-11-22 9:07 ` Conor Dooley
2022-11-22 9:09 ` Ben Dooks
2022-11-22 9:55 ` Hal Feng
2022-11-22 10:01 ` Conor Dooley
2022-11-22 10:16 ` Hal Feng
2022-11-22 10:35 ` Emil Renner Berthing
2022-11-22 12:51 ` Hal Feng
2022-11-23 22:26 ` Rob Herring
2022-11-18 1:17 ` [PATCH v2 5/8] soc: sifive: ccache: Add StarFive JH7110 support Hal Feng
2022-11-18 11:45 ` Conor Dooley
2022-11-22 9:02 ` Hal Feng
2022-11-22 9:54 ` Emil Renner Berthing
2022-11-22 10:12 ` Conor Dooley
2022-11-18 17:32 ` Emil Renner Berthing
2022-11-22 9:17 ` Hal Feng
2022-11-18 1:17 ` [PATCH v2 6/8] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng
2022-11-18 12:01 ` Conor Dooley
2022-11-18 17:39 ` Emil Renner Berthing
2022-11-23 7:11 ` Hal Feng
2022-11-18 17:41 ` Emil Renner Berthing [this message]
2022-11-23 7:20 ` Hal Feng
2022-11-18 1:17 ` [PATCH v2 7/8] riscv: dts: starfive: Add StarFive JH7110 VisionFive2 board " Hal Feng
2022-11-18 17:55 ` Emil Renner Berthing
2022-11-24 6:17 ` Hal Feng
2022-11-18 1:17 ` [PATCH v2 8/8] RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW Hal Feng
2022-11-18 12:04 ` Conor Dooley
2022-12-02 18:00 ` Palmer Dabbelt
2022-12-02 18:07 ` Conor Dooley
2022-12-02 18:13 ` Palmer Dabbelt
2022-12-02 18:18 ` Conor Dooley
2022-12-02 18:24 ` Palmer Dabbelt
2022-12-02 18:43 ` Palmer Dabbelt
2022-12-04 7:20 ` Hal Feng
2022-11-18 7:28 ` [PATCH v2 0/8] Basic device tree support for StarFive JH7110 RISC-V SoC Hal Feng
2022-12-02 19:00 ` patchwork-bot+linux-riscv
2022-12-02 19:04 ` Palmer Dabbelt
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAJM55Z9PXVLfFTPuyELR4ov22ENfEXZfJAJdLgURA+R4mcH_eg@mail.gmail.com \
--to=emil.renner.berthing@canonical.com \
--cc=aou@eecs.berkeley.edu \
--cc=ben.dooks@sifive.com \
--cc=conor@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=hal.feng@starfivetech.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linus.walleij@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=maz@kernel.org \
--cc=mturquette@baylibre.com \
--cc=p.zabel@pengutronix.de \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).