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Wed, 19 Jul 2023 08:45:31 -0700 (PDT) MIME-Version: 1.0 References: <20230717023040.78860-1-xingyu.wu@starfivetech.com> <20230717023040.78860-2-xingyu.wu@starfivetech.com> In-Reply-To: <20230717023040.78860-2-xingyu.wu@starfivetech.com> From: Emil Renner Berthing Date: Wed, 19 Jul 2023 17:45:14 +0200 Message-ID: Subject: Re: [PATCH v7 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator To: Xingyu Wu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , William Qiu , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, 17 Jul 2023 at 04:30, Xingyu Wu wrote: > > Add bindings for the PLL clock generator on the JH7110 RISC-V SoC. > > Reviewed-by: Conor Dooley > Reviewed-by: Krzysztof Kozlowski Reviewed-by: Emil Renner Berthing > Signed-off-by: Xingyu Wu > --- > .../bindings/clock/starfive,jh7110-pll.yaml | 46 +++++++++++++++++++ > .../dt-bindings/clock/starfive,jh7110-crg.h | 6 +++ > 2 files changed, 52 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml > > diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml > new file mode 100644 > index 000000000000..be8300ce86d0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml > @@ -0,0 +1,46 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive JH7110 PLL Clock Generator > + > +description: > + These PLLs are high speed, low jitter frequency synthesizers in the JH7110. > + Each PLL works in integer mode or fraction mode, with configuration > + registers in the sys syscon. So the PLLs node should be a child of > + SYS-SYSCON node. > + The formula for calculating frequency is > + Fvco = Fref * (NI + NF) / M / Q1 > + > +maintainers: > + - Xingyu Wu > + > +properties: > + compatible: > + const: starfive,jh7110-pll > + > + clocks: > + maxItems: 1 > + description: Main Oscillator (24 MHz) > + > + '#clock-cells': > + const: 1 > + description: > + See for valid indices. > + > +required: > + - compatible > + - clocks > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + clock-controller { > + compatible = "starfive,jh7110-pll"; > + clocks = <&osc>; > + #clock-cells = <1>; > + }; > diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h > index 06257bfd9ac1..3fb5e31c3be4 100644 > --- a/include/dt-bindings/clock/starfive,jh7110-crg.h > +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h > @@ -6,6 +6,12 @@ > #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ > #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ > > +/* PLL clocks */ > +#define JH7110_PLLCLK_PLL0_OUT 0 > +#define JH7110_PLLCLK_PLL1_OUT 1 > +#define JH7110_PLLCLK_PLL2_OUT 2 > +#define JH7110_PLLCLK_END 3 > + > /* SYSCRG clocks */ > #define JH7110_SYSCLK_CPU_ROOT 0 > #define JH7110_SYSCLK_CPU_CORE 1 > -- > 2.25.1 >