Re: [PATCH v2 3/7] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table

["Clément Péron" <peron.clem@gmail.com>]

Hi,

On Mon, 6 Apr 2020 at 10:14, Maxime Ripard <maxime@cerno.tech> wrote:
>
> On Sun, Apr 05, 2020 at 07:35:57PM +0200, Clément Péron wrote:
> > From: Ondrej Jirman <megous@megous.com>
> >
> > Add an Operating Performance Points table for the CPU cores to
> > enable Dynamic Voltage & Frequency Scaling on the H6.
> >
> > Signed-off-by: Ondrej Jirman <megous@megous.com>
> > Signed-off-by: Clément Péron <peron.clem@gmail.com>
> > ---
> >  .../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 121 ++++++++++++++++++
> >  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  |   4 +
> >  2 files changed, 125 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
> > new file mode 100644
> > index 000000000000..8c1e413c6af9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
> > @@ -0,0 +1,121 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
> > +// Copyright (C) 2020 Clément Péron <peron.clem@gmail.com>
> > +
> > +/ {
> > +     cpu0_opp_table: opp_table0 {
>
> Node names shouldn't have an underscore, this will trigger a DTC
> warning.
>
> > +             compatible = "allwinner,sun50i-h6-operating-points";
> > +             nvmem-cells = <&speedbin_efuse>;
> > +             opp-shared;
> > +
> > +             opp@480000000 {
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +                     opp-hz = /bits/ 64 <480000000>;
> > +
> > +                     opp-microvolt-speed0 = <880000>;
> > +                     opp-microvolt-speed1 = <820000>;
> > +                     opp-microvolt-speed2 = <820000>;
> > +             };
>
> And similarly, if you have a unit-address (the part after @), you
> should have a matching reg property. You should use a dash instead.
>
> > +             opp@720000000 {
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +                     opp-hz = /bits/ 64 <720000000>;
> > +
> > +                     opp-microvolt-speed0 = <880000>;
> > +                     opp-microvolt-speed1 = <820000>;
> > +                     opp-microvolt-speed2 = <820000>;
> > +             };
> > +
> > +             opp@816000000 {
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +                     opp-hz = /bits/ 64 <816000000>;
> > +
> > +                     opp-microvolt-speed0 = <880000>;
> > +                     opp-microvolt-speed1 = <820000>;
> > +                     opp-microvolt-speed2 = <820000>;
> > +             };
> > +
> > +             opp@888000000 {
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +                     opp-hz = /bits/ 64 <888000000>;
> > +
> > +                     opp-microvolt-speed0 = <880000>;
> > +                     opp-microvolt-speed1 = <820000>;
> > +                     opp-microvolt-speed2 = <820000>;
> > +             };
> > +
> > +             opp@1080000000 {
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +                     opp-hz = /bits/ 64 <1080000000>;
> > +
> > +                     opp-microvolt-speed0 = <940000>;
> > +                     opp-microvolt-speed1 = <880000>;
> > +                     opp-microvolt-speed2 = <880000>;
> > +             };
> > +
> > +             opp@1320000000 {
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +                     opp-hz = /bits/ 64 <1320000000>;
> > +
> > +                     opp-microvolt-speed0 = <1000000>;
> > +                     opp-microvolt-speed1 = <940000>;
> > +                     opp-microvolt-speed2 = <940000>;
> > +             };
> > +
> > +             opp@1488000000 {
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +                     opp-hz = /bits/ 64 <1488000000>;
> > +
> > +                     opp-microvolt-speed0 = <1060000>;
> > +                     opp-microvolt-speed1 = <1000000>;
> > +                     opp-microvolt-speed2 = <1000000>;
> > +             };
> > +
> > +             opp@1608000000 {
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +                     opp-hz = /bits/ 64 <1608000000>;
> > +
> > +                     opp-microvolt-speed0 = <1090000>;
> > +                     opp-microvolt-speed1 = <1030000>;
> > +                     opp-microvolt-speed2 = <1030000>;
> > +             };
> > +
> > +             opp@1704000000 {
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +                     opp-hz = /bits/ 64 <1704000000>;
> > +
> > +                     opp-microvolt-speed0 = <1120000>;
> > +                     opp-microvolt-speed1 = <1060000>;
> > +                     opp-microvolt-speed2 = <1060000>;
> > +             };
> > +
> > +             opp@1800000000 {
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +                     opp-hz = /bits/ 64 <1800000000>;
> > +
> > +                     opp-microvolt-speed0 = <1160000>;
> > +                     opp-microvolt-speed1 = <1100000>;
> > +                     opp-microvolt-speed2 = <1100000>;
> > +             };
> > +     };
> > +};
> > +
> > +&cpu0 {
> > +     operating-points-v2 = <&cpu0_opp_table>;
> > +     #cooling-cells = <2>;
> > +};
> > +
> > +&cpu1 {
> > +     operating-points-v2 = <&cpu0_opp_table>;
> > +     #cooling-cells = <2>;
> > +};
> > +
> > +&cpu2 {
> > +     operating-points-v2 = <&cpu0_opp_table>;
> > +     #cooling-cells = <2>;
> > +};
> > +
> > +&cpu3 {
> > +     operating-points-v2 = <&cpu0_opp_table>;
> > +     #cooling-cells = <2>;
> > +};
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > index e0dd0757be0b..6b7af858614a 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > @@ -253,6 +253,10 @@
> >                       #address-cells = <1>;
> >                       #size-cells = <1>;
> >
> > +                     speedbin_efuse: speed@1c {
> > +                             reg = <0x1c 0x4>;
> > +                     };
> > +
>
> You should order this by address, so after the THS calibration. Also,
> using a less generic node name than "speed" would be great. What about
> soc-bin ?

Indeed it's too generic.
I will keep coherency with i.MX8 and use "cpu_speed_grade"

Thanks for the review,
Clement

>
> Maxime