From: Masahiro Yamada <yamada.masahiro@socionext.com>
To: Boris Brezillon <boris.brezillon@bootlin.com>
Cc: linux-mtd <linux-mtd@lists.infradead.org>,
Miquel Raynal <miquel.raynal@bootlin.com>,
David Woodhouse <dwmw2@infradead.org>,
Mark Rutland <mark.rutland@arm.com>,
DTML <devicetree@vger.kernel.org>,
Linux Kbuild mailing list <linux-kbuild@vger.kernel.org>,
Richard Weinberger <richard@nod.at>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
"linux-stable #4 . 14+" <stable@vger.kernel.org>,
Marek Vasut <marek.vasut@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Brian Norris <computersforpeace@gmail.com>
Subject: Re: [PATCH v3 1/3] mtd: rawnand: denali_dt: add more clocks based on IP datasheet
Date: Fri, 22 Jun 2018 22:24:56 +0900 [thread overview]
Message-ID: <CAK7LNAQdfEF3j69DnmpwTMnuBQJ+f4x-1Di9TZ1f5hvVmPDwmw@mail.gmail.com> (raw)
In-Reply-To: <20180622134235.5ab76325@bbrezillon>
2018-06-22 20:42 GMT+09:00 Boris Brezillon <boris.brezillon@bootlin.com>:
> Hi Masahiro,
>
> On Tue, 19 Jun 2018 13:28:11 +0200
> Boris Brezillon <boris.brezillon@bootlin.com> wrote:
>
>> Hi Masahiro,
>>
>> On Fri, 15 Jun 2018 10:18:50 +0900
>> Masahiro Yamada <yamada.masahiro@socionext.com> wrote:
>>
>> > According to the Denali User's Guide, this IP needs three clocks:
>> >
>> > - clk: controller core clock
>> >
>> > - clk_x: bus interface clock
>> >
>> > - ecc_clk: clock at which ECC circuitry is run
>> >
>> > Currently, denali_dt.c requires a single anonymous clock and its
>> > frequency. However, the driver needs to get the frequency of "clk_x"
>> > not "clk". This is confusing because people tend to assume the
>> > anonymous clock means the core clock. In fact, I got a report of
>> > SOCFPGA breakage because the timing parameters are calculated based
>> > on a wrong frequency.
>> >
>> > Instead of the cheesy implementation, the clocks in the real hardware
>> > should be represented in the driver and the DT-binding.
>> >
>> > However, adding new clocks would break the existing platforms. For the
>> > backward compatibility, the driver still accepts a single clock just as
>> > before. If clk_x is missing, clk_x_rate is set to a hardcoded value.
>> > This is fine for existing DT of Socionext UniPhier, and also fixes the
>> > issue of Altera (Intel) SOCFPGA because both platforms use 200 MHz for
>> > the bus interface clock.
>> >
>> > Fixes: 1bb88666775e ("mtd: nand: denali: handle timing parameters by setup_data_interface()")
>>
>> Sorry for changing my mind, but I think this patch is doing more than
>> just fixing a bug. The bugfix should IMO be limited to unconditionally
>> setting ->clk_x_rate to 200000000 since this is what was done before
>> commit 1bb88666775e. And the remaining changes should go in nand/next.
>
> Do you want me to write this patch? Note that I can't really take this
> patch since Rob asked for a new version with DT bindings changes placed
> in a separate patch.
Sorry for the delay. I was traveling.
Now I am back home, and started to flush my TODO queue.
V4 will be soon.
--
Best Regards
Masahiro Yamada
next prev parent reply other threads:[~2018-06-22 13:24 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-15 1:18 [PATCH v3 0/3] mtd: rawnand: denali: add new clocks and improve setup_data_interface Masahiro Yamada
2018-06-15 1:18 ` [PATCH v3 1/3] mtd: rawnand: denali_dt: add more clocks based on IP datasheet Masahiro Yamada
2018-06-18 7:09 ` Richard Weinberger
2018-06-18 7:46 ` Boris Brezillon
2018-06-18 12:18 ` Miquel Raynal
2018-06-19 8:07 ` Masahiro Yamada
2018-06-19 10:46 ` Richard Weinberger
2018-06-19 9:14 ` Miquel Raynal
2018-06-19 11:28 ` Boris Brezillon
2018-06-22 11:42 ` Boris Brezillon
2018-06-22 13:24 ` Masahiro Yamada [this message]
2018-06-20 18:12 ` Rob Herring
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