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AJvYcCWnPeqiEOkN0aswUB9KBSfk2odnOO889rq5/85YV2xt9Gd4RHmHmbSxz/mNzKMEps163EsvZnvSJ7Dc9t0ZhXoSlG56Vg7qEVwGDw== X-Gm-Message-State: AOJu0Yw0AkoVtrJ8QEUEB1gZu8NOWDq7VIlJOTG3OWXsH2Y4wxR4iSJi RFr6Xjb56jGF+1lx2XQoWb45ohzX3ml9dlfYDN3NWR1SwGY4zc1zw4xZaRXLIFsk58Os9pS4PzF HwxVkyQVlPHEqyEFRu5b20LgrIsxzDqgkORdblA== X-Google-Smtp-Source: AGHT+IFxn/XbcJ1LB10krZNF1aRmNeyYmzh22jCeeFItu7QL0ccN+D39sO7s3W7/K3hok3NiVql/DfBXEhGDD51v9UM= X-Received: by 2002:a05:651c:1047:b0:2d2:3f05:d137 with SMTP id x7-20020a05651c104700b002d23f05d137mr3610001ljm.1.1708447932770; Tue, 20 Feb 2024 08:52:12 -0800 (PST) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240220060718.823229-1-apatel@ventanamicro.com> <20240220060718.823229-8-apatel@ventanamicro.com> <875xyji7mc.ffs@tglx> In-Reply-To: <875xyji7mc.ffs@tglx> From: Anup Patel Date: Tue, 20 Feb 2024 22:22:01 +0530 Message-ID: Subject: Re: [PATCH v13 07/13] irqchip/riscv-imsic: Add device MSI domain support for platform devices To: Thomas Gleixner Cc: Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley , Marc Zyngier , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Feb 20, 2024 at 7:02=E2=80=AFPM Thomas Gleixner wrote: > > On Tue, Feb 20 2024 at 11:37, Anup Patel wrote: > > +#ifdef CONFIG_SMP > > +static void imsic_msi_update_msg(struct irq_data *d, struct imsic_vect= or *vec) > > +{ > > + struct msi_msg msg[2] =3D { [1] =3D { }, }; > > That's a weird initializer and why do you need an array here? > > struct msi_msg msg =3D { }; > > Should be sufficient, no? I had taken reference from irq_msi_update_msg() in arch/x86/kernel/apic/msi.c I tried "struct msi_msg msg =3D { };" and it works fine so I will update. > > > + > > + imsic_irq_compose_vector_msg(vec, msg); > > + irq_data_get_irq_chip(d)->irq_write_msi_msg(d, msg); > > +} > > > +static int imsic_irq_domain_alloc(struct irq_domain *domain, unsigned = int virq, > > + unsigned int nr_irqs, void *args) > > +{ > > + struct imsic_vector *vec; > > + > > + /* Legacy-MSI or multi-MSI not supported yet. */ > > Coming back to my earlier question: > > >> What's legacy MSI in that context? > > > > The legacy-MSI is the MSI support in PCI v2.2 where > > number of MSIs allocated by device were either 1, 2, 4, > > 8, 16, or 32 and the data written is + . > > You talk about PCI/MSI, where more than one vector is named > multi-MSI. Contrary to the modern v3.0 variant which is PCI/MSI-X. > > So this should be "Multi-MSI is not supported yet", no? Yes, I agree. We should just call it "Multi-MSI is not supported yet" to avoid confusion. I will update. > > > + if (nr_irqs > 1) > > + return -ENOTSUPP; > > + > > + vec =3D imsic_vector_alloc(virq, cpu_online_mask); > > + if (!vec) > > + return -ENOSPC; > > + > > + irq_domain_set_info(domain, virq, virq, > > + &imsic_irq_base_chip, vec, > > + handle_simple_irq, NULL, NULL); > > Please utilize the 100 characters. Okay, I will update. > > > + irq_set_noprobe(virq); > > + irq_set_affinity(virq, cpu_online_mask); > > + > > + return 0; > > +} > > Thanks, > > tglx Thanks, Anup