Re: Two different interrupt-parents

["jonsmirl-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org" <jonsmirl-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]

On Mon, Apr 16, 2012 at 12:53 AM, David Gibson
<david-xT8FGy+AXnRB3Ne2BGzF6laj5H9X9Tb+@public.gmane.org> wrote:
> On Mon, Apr 16, 2012 at 04:14:25AM +0000, Sethi Varun-B16395 wrote:
>> You can use a 4 cell interrupt specifier (we use that in case of embedded power architecture platforms)
>> - First cell corresponds to one of the four cascade lines (coming from the cascaded pic)
>> - Second cell provides the interrupt sense information
>> - Third one tells the interrupt subtype (in your case should be the cascade power interrupt type)
>> - Fourth cell communicates the interrupt number corresponding to the cascaded pic.
>>
>> There would be a single interrupt parent, which is the system interrupt controller. You would have
>> to translate the four cell interrupt specifier and also add cascaded interrupt handling
>> for the shared interrupt line.
>
> No, don't do that.
>
> Use the interrupt-map technique described in the thread that got
> linked earlier.

If interrupts had syntax like GPIOs this problem wouldn't exist.


>
> --
> David Gibson                    | I'll have my music baroque, and my code
> david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
>                                | _way_ _around_!
> http://www.ozlabs.org/~dgibson



-- 
Jon Smirl
jonsmirl-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org