From: Vincent Guittot <vincent.guittot@linaro.org>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: chester62515@gmail.com, mbrugger@suse.com,
ghennadi.procopciuc@oss.nxp.com, s32@nxp.com,
bhelgaas@google.com, jingoohan1@gmail.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, Ionut.Vicovan@nxp.com,
larisa.grigore@nxp.com, Ghennadi.Procopciuc@nxp.com,
ciprianmarian.costea@nxp.com, bogdan.hamciuc@nxp.com,
Frank.li@nxp.com, linux-arm-kernel@lists.infradead.org,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev,
cassel@kernel.org
Subject: Re: [PATCH 2/3 v2] PCI: s32g: Add initial PCIe support (RC)
Date: Tue, 30 Sep 2025 18:11:05 +0200 [thread overview]
Message-ID: <CAKfTPtDva4fUQty8b5b=tLEHcd+OGFSS9i0DJqnn3vFvgG9wrA@mail.gmail.com> (raw)
In-Reply-To: <xmjgs5ssolugcq2ogjc5j3ccwalcc4q3whl64fcra2aiebhtci@qwobbjtb2wcl>
On Mon, 29 Sept 2025 at 18:32, Manivannan Sadhasivam <mani@kernel.org> wrote:
>
> On Mon, Sep 29, 2025 at 06:23:05PM +0200, Vincent Guittot wrote:
>
> [...]
>
> > > > > > +static int s32g_pcie_resume(struct device *dev)
> > > > > > +{
> > > > > > + struct s32g_pcie *s32g_pp = dev_get_drvdata(dev);
> > > > > > + struct dw_pcie *pci = &s32g_pp->pci;
> > > > > > + struct dw_pcie_rp *pp = &pci->pp;
> > > > > > + int ret = 0;
> > > > > > +
> > > > > > + ret = s32g_pcie_init(dev, s32g_pp);
> > > > > > + if (ret < 0)
> > > > > > + return ret;
> > > > > > +
> > > > > > + ret = dw_pcie_setup_rc(pp);
> > > > > > + if (ret) {
> > > > > > + dev_err(dev, "Failed to resume DW RC: %d\n", ret);
> > > > > > + goto fail_host_init;
> > > > > > + }
> > > > > > +
> > > > > > + ret = dw_pcie_start_link(pci);
> > > > > > + if (ret) {
> > > > > > + /*
> > > > > > + * We do not exit with error if link up was unsuccessful
> > > > > > + * Endpoint may not be connected.
> > > > > > + */
> > > > > > + if (dw_pcie_wait_for_link(pci))
> > > > > > + dev_warn(pci->dev,
> > > > > > + "Link Up failed, Endpoint may not be connected\n");
> > > > > > +
> > > > > > + if (!phy_validate(s32g_pp->phy, PHY_MODE_PCIE, 0, NULL)) {
> > > > > > + dev_err(dev, "Failed to get link up with EP connected\n");
> > > > > > + goto fail_host_init;
> > > > > > + }
> > > > > > + }
> > > > > > +
> > > > > > + ret = pci_host_probe(pp->bridge);
> > > > >
> > > > > Oh no... Do not call pci_host_probe() directly from glue drivers. Use
> > > > > dw_pcie_host_init() to do so. This should simplify suspend and resume functions.
> > > >
> > > > dw_pcie_host_init() is doing much more than just init the controller
> > > > as it gets resources which we haven't released during suspend.
> > > >
> > >
> > > Any specific reason to keep resources enabled, even though you were removing the
> > > Root bus? This doesn't make sense to me.
> >
> > By ressources I mean everything before dw_pcie_setup_rc() in
> > dw_pcie_host_init() which are still there after dw_pcie_host_deinit()
> > in addition to being a waste of time. Also we don't need to remove
> > edma and free msi
> >
>
> Let me take a step back and ask, why do you need to remove Root bus during
> suspend() and not just disable LTSSM with dw_pcie_stop_link()?
That's something that I'm trying to clarify but it's so far the only
way to get suspend/resume working. I have some hypotheses that I need
to get confirmed but it doesn't have full control of clocks and power
domain
Vincent
>
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2025-09-30 16:11 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-19 15:58 [PATCH 0/4 v2] PCI: s32g: Add support for PCIe controller Vincent Guittot
2025-09-19 15:58 ` [PATCH 1/3 v2] dt-bindings: PCI: s32g: Add NXP " Vincent Guittot
2025-09-19 16:39 ` Frank Li
2025-09-23 14:49 ` Vincent Guittot
2025-09-23 16:28 ` Frank Li
2025-09-22 6:21 ` Manivannan Sadhasivam
2025-09-23 17:40 ` Vincent Guittot
2025-10-07 15:41 ` Lorenzo Pieralisi
2025-10-07 22:28 ` Manivannan Sadhasivam
2025-10-08 8:26 ` Arnd Bergmann
2025-10-08 8:35 ` Arnd Bergmann
2025-10-08 15:19 ` Manivannan Sadhasivam
2025-10-08 17:56 ` Arnd Bergmann
2025-10-09 18:47 ` Manivannan Sadhasivam
2025-10-09 21:16 ` Arnd Bergmann
2025-10-17 15:12 ` Manivannan Sadhasivam
2025-10-08 15:14 ` Manivannan Sadhasivam
2025-09-19 15:58 ` [PATCH 2/3 v2] PCI: s32g: Add initial PCIe support (RC) Vincent Guittot
2025-09-19 17:03 ` [External] : " ALOK TIWARI
2025-09-19 18:37 ` Frank Li
2025-09-25 17:09 ` Vincent Guittot
2025-09-22 4:07 ` kernel test robot
2025-09-22 7:56 ` Manivannan Sadhasivam
2025-09-25 16:52 ` Vincent Guittot
2025-09-29 13:57 ` Manivannan Sadhasivam
2025-09-29 16:23 ` Vincent Guittot
2025-09-29 16:32 ` Manivannan Sadhasivam
2025-09-30 16:11 ` Vincent Guittot [this message]
2025-09-22 14:52 ` Rob Herring
2025-09-25 16:56 ` Vincent Guittot
2025-09-25 19:15 ` Bjorn Helgaas
2025-09-26 14:18 ` Rob Herring
2025-09-19 15:58 ` [PATCH 3/3 v2] MAINTAINERS: Add MAINTAINER for NXP S32G PCIe driver Vincent Guittot
2025-09-19 16:58 ` Frank Li
2025-09-25 17:16 ` Vincent Guittot
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