Re: [PATCH v2 01/16] MIPS: Provide a generic plat_irq_dispatch

[Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>]

On Fri, Sep 5, 2014 at 11:51 AM, Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org> wrote:
> On Fri, 5 Sep 2014, Andrew Bresticker wrote:
>> For platforms which boot with device-tree and use the MIPS CPU interrupt
>> controller binding, a generic plat_irq_dispatch() can be used since all
>> CPU interrupts should be mapped through the CPU IRQ domain.  Implement a
>> plat_irq_dispatch() which simply handles the highest pending interrupt.
>>
>> Signed-off-by: Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
>> Tested-by: Jonas Gorski <jogo-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
>> ---
>> No changes from v1.
>> ---
>>  arch/mips/kernel/irq_cpu.c | 28 +++++++++++++++++++++++-----
>>  1 file changed, 23 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
>> index e498f2b..9cf8459 100644
>> --- a/arch/mips/kernel/irq_cpu.c
>> +++ b/arch/mips/kernel/irq_cpu.c
>> @@ -116,6 +116,24 @@ void __init mips_cpu_irq_init(void)
>>  }
>>
>>  #ifdef CONFIG_IRQ_DOMAIN
>> +static struct irq_domain *mips_intc_domain;
>> +
>> +asmlinkage void __weak plat_irq_dispatch(void)
>> +{
>> +     unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
>> +     unsigned int hw;
>> +     int irq;
>> +
>> +     if (!pending) {
>> +             spurious_interrupt();
>> +             return;
>> +     }
>> +
>> +     hw = fls(pending) - CAUSEB_IP - 1;
>> +     irq = irq_linear_revmap(mips_intc_domain, hw);
>> +     do_IRQ(irq);
>
> Why are you not handling all pending interrupts in a loop?

Nearly all of the existing plat_irq_dispatch()es handle only a single
pending interrupt.  I suppose it doesn't hurt to handle all pending
interrupts though.
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