[PATCH V2 0/3] Pistachio USB2.0 PHY

[PATCH V2 0/3] Pistachio USB2.0 PHY

[Andrew Bresticker]

This series adds support for the USB2.0 PHY present on the IMG Pistachio SoC.

Based on mips-for-linux-next and tested on the IMG Pistachio BuB.  If possible,
I'd like this to go through the MIPS tree with Kishon's ACK.

Cc: James Hartley <james.hartley@imgtec.com>
Cc: Damien Horsley <Damien.Horsley@imgtec.com>

Changes from v1:
 - Added patch to enable PHY driver in pistachio_defconfig
 - Fixed a couple of spelling errors

Andrew Bresticker (3):
  phy: Add binding document for Pistachio USB2.0 PHY
  phy: Add driver for Pistachio USB2.0 PHY
  MIPS: pistachio: Enable USB PHY driver in defconfig

 .../devicetree/bindings/phy/pistachio-usb-phy.txt  |  29 +++
 arch/mips/configs/pistachio_defconfig              |   1 +
 drivers/phy/Kconfig                                |   7 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-pistachio-usb.c                    | 206 +++++++++++++++++++++
 include/dt-bindings/phy/phy-pistachio-usb.h        |  16 ++
 6 files changed, 260 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
 create mode 100644 drivers/phy/phy-pistachio-usb.c
 create mode 100644 include/dt-bindings/phy/phy-pistachio-usb.h

-- 
2.2.0.rc0.207.ga3a616c

[PATCH V2 1/3] phy: Add binding document for Pistachio USB2.0 PHY

[Andrew Bresticker]

Add a binding document for the USB2.0 PHY found on the IMG Pistachio SoC.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
---
No changes from v1.
---
 .../devicetree/bindings/phy/pistachio-usb-phy.txt  | 29 ++++++++++++++++++++++
 include/dt-bindings/phy/phy-pistachio-usb.h        | 16 ++++++++++++
 2 files changed, 45 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
 create mode 100644 include/dt-bindings/phy/phy-pistachio-usb.h

diff --git a/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
new file mode 100644
index 0000000..afbc7e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
@@ -0,0 +1,29 @@
+IMG Pistachio USB PHY
+=====================
+
+Required properties:
+--------------------
+ - compatible: Must be "img,pistachio-usb-phy".
+ - #phy-cells: Must be 0.  See ./phy-bindings.txt for details.
+ - clocks: Must contain an entry for each entry in clock-names.
+   See ../clock/clock-bindings.txt for details.
+ - clock-names: Must include "usb_phy".
+ - img,cr-top: Must constain a phandle to the CR_TOP syscon node.
+ - img,refclk: Indicates the reference clock source for the USB PHY.
+   See <dt-bindings/phy/phy-pistachio-usb.h> for a list of valid values.
+
+Optional properties:
+--------------------
+ - phy-supply: USB VBUS supply.  Must supply 5.0V.
+
+Example:
+--------
+usb_phy: usb-phy {
+	compatible = "img,pistachio-usb-phy";
+	clocks = <&clk_core CLK_USB_PHY>;
+	clock-names = "usb_phy";
+	phy-supply = <&usb_vbus>;
+	img,refclk = <REFCLK_CLK_CORE>;
+	img,cr-top = <&cr_top>;
+	#phy-cells = <0>;
+};
diff --git a/include/dt-bindings/phy/phy-pistachio-usb.h b/include/dt-bindings/phy/phy-pistachio-usb.h
new file mode 100644
index 0000000..d1877aa
--- /dev/null
+++ b/include/dt-bindings/phy/phy-pistachio-usb.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_PHY_PISTACHIO
+#define _DT_BINDINGS_PHY_PISTACHIO
+
+#define REFCLK_XO_CRYSTAL	0x0
+#define REFCLK_X0_EXT_CLK	0x1
+#define REFCLK_CLK_CORE		0x2
+
+#endif /* _DT_BINDINGS_PHY_PISTACHIO */
-- 
2.2.0.rc0.207.ga3a616c

Re: [PATCH V2 1/3] phy: Add binding document for Pistachio USB2.0 PHY

[James Hogan]

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Hi Andrew,

On Tue, Apr 07, 2015 at 03:04:16PM -0700, Andrew Bresticker wrote:
> Add a binding document for the USB2.0 PHY found on the IMG Pistachio SoC.
> 
> Signed-off-by: Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
> Cc: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
> No changes from v1.
> ---
>  .../devicetree/bindings/phy/pistachio-usb-phy.txt  | 29 ++++++++++++++++++++++
>  include/dt-bindings/phy/phy-pistachio-usb.h        | 16 ++++++++++++
>  2 files changed, 45 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
>  create mode 100644 include/dt-bindings/phy/phy-pistachio-usb.h
> 
> diff --git a/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
> new file mode 100644
> index 0000000..afbc7e2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
> @@ -0,0 +1,29 @@
> +IMG Pistachio USB PHY
> +=====================
> +
> +Required properties:
> +--------------------
> + - compatible: Must be "img,pistachio-usb-phy".
> + - #phy-cells: Must be 0.  See ./phy-bindings.txt for details.
> + - clocks: Must contain an entry for each entry in clock-names.
> +   See ../clock/clock-bindings.txt for details.
> + - clock-names: Must include "usb_phy".
> + - img,cr-top: Must constain a phandle to the CR_TOP syscon node.
> + - img,refclk: Indicates the reference clock source for the USB PHY.
> +   See <dt-bindings/phy/phy-pistachio-usb.h> for a list of valid values.

Possibly dumb question: why isn't the reference clock source specified
in the normal ways like the "usb_phy" clock is?

Does the value required here depend on what usb_phy clock gets muxed
from or something?

Cheers
James

> +
> +Optional properties:
> +--------------------
> + - phy-supply: USB VBUS supply.  Must supply 5.0V.
> +
> +Example:
> +--------
> +usb_phy: usb-phy {
> +	compatible = "img,pistachio-usb-phy";
> +	clocks = <&clk_core CLK_USB_PHY>;
> +	clock-names = "usb_phy";
> +	phy-supply = <&usb_vbus>;
> +	img,refclk = <REFCLK_CLK_CORE>;
> +	img,cr-top = <&cr_top>;
> +	#phy-cells = <0>;
> +};
> diff --git a/include/dt-bindings/phy/phy-pistachio-usb.h b/include/dt-bindings/phy/phy-pistachio-usb.h
> new file mode 100644
> index 0000000..d1877aa
> --- /dev/null
> +++ b/include/dt-bindings/phy/phy-pistachio-usb.h
> @@ -0,0 +1,16 @@
> +/*
> + * Copyright (C) 2015 Google, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + */
> +
> +#ifndef _DT_BINDINGS_PHY_PISTACHIO
> +#define _DT_BINDINGS_PHY_PISTACHIO
> +
> +#define REFCLK_XO_CRYSTAL	0x0
> +#define REFCLK_X0_EXT_CLK	0x1
> +#define REFCLK_CLK_CORE		0x2
> +
> +#endif /* _DT_BINDINGS_PHY_PISTACHIO */
> -- 
> 2.2.0.rc0.207.ga3a616c
> 
> 

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Re: [PATCH V2 1/3] phy: Add binding document for Pistachio USB2.0 PHY

[Andrew Bresticker]

Hi James,

On Tue, May 5, 2015 at 3:01 PM, James Hogan <james.hogan@imgtec.com> wrote:
> Hi Andrew,
>
> On Tue, Apr 07, 2015 at 03:04:16PM -0700, Andrew Bresticker wrote:
>> Add a binding document for the USB2.0 PHY found on the IMG Pistachio SoC.
>>
>> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: Pawel Moll <pawel.moll@arm.com>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
>> Cc: Kumar Gala <galak@codeaurora.org>
>> ---
>> No changes from v1.
>> ---
>>  .../devicetree/bindings/phy/pistachio-usb-phy.txt  | 29 ++++++++++++++++++++++
>>  include/dt-bindings/phy/phy-pistachio-usb.h        | 16 ++++++++++++
>>  2 files changed, 45 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
>>  create mode 100644 include/dt-bindings/phy/phy-pistachio-usb.h
>>
>> diff --git a/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
>> new file mode 100644
>> index 0000000..afbc7e2
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
>> @@ -0,0 +1,29 @@
>> +IMG Pistachio USB PHY
>> +=====================
>> +
>> +Required properties:
>> +--------------------
>> + - compatible: Must be "img,pistachio-usb-phy".
>> + - #phy-cells: Must be 0.  See ./phy-bindings.txt for details.
>> + - clocks: Must contain an entry for each entry in clock-names.
>> +   See ../clock/clock-bindings.txt for details.
>> + - clock-names: Must include "usb_phy".
>> + - img,cr-top: Must constain a phandle to the CR_TOP syscon node.
>> + - img,refclk: Indicates the reference clock source for the USB PHY.
>> +   See <dt-bindings/phy/phy-pistachio-usb.h> for a list of valid values.
>
> Possibly dumb question: why isn't the reference clock source specified
> in the normal ways like the "usb_phy" clock is?
>
> Does the value required here depend on what usb_phy clock gets muxed
> from or something?

Right, the value indicates what clock "usb_phy" is: whether it comes
from the core clock controller, the XO crystal, or is some external
clock.  It's a mux internal to the PHY.

Thanks,
Andrew

Re: [PATCH V2 1/3] phy: Add binding document for Pistachio USB2.0 PHY

[James Hogan]

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On Tue, May 05, 2015 at 03:16:23PM -0700, Andrew Bresticker wrote:
> Hi James,
> 
> On Tue, May 5, 2015 at 3:01 PM, James Hogan <james.hogan-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org> wrote:
> > Hi Andrew,
> >
> > On Tue, Apr 07, 2015 at 03:04:16PM -0700, Andrew Bresticker wrote:
> >> Add a binding document for the USB2.0 PHY found on the IMG Pistachio SoC.
> >>
> >> Signed-off-by: Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> >> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> >> Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> >> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> >> Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
> >> Cc: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> >> ---
> >> No changes from v1.
> >> ---
> >>  .../devicetree/bindings/phy/pistachio-usb-phy.txt  | 29 ++++++++++++++++++++++
> >>  include/dt-bindings/phy/phy-pistachio-usb.h        | 16 ++++++++++++
> >>  2 files changed, 45 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
> >>  create mode 100644 include/dt-bindings/phy/phy-pistachio-usb.h
> >>
> >> diff --git a/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
> >> new file mode 100644
> >> index 0000000..afbc7e2
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
> >> @@ -0,0 +1,29 @@
> >> +IMG Pistachio USB PHY
> >> +=====================
> >> +
> >> +Required properties:
> >> +--------------------
> >> + - compatible: Must be "img,pistachio-usb-phy".
> >> + - #phy-cells: Must be 0.  See ./phy-bindings.txt for details.
> >> + - clocks: Must contain an entry for each entry in clock-names.
> >> +   See ../clock/clock-bindings.txt for details.
> >> + - clock-names: Must include "usb_phy".
> >> + - img,cr-top: Must constain a phandle to the CR_TOP syscon node.
> >> + - img,refclk: Indicates the reference clock source for the USB PHY.
> >> +   See <dt-bindings/phy/phy-pistachio-usb.h> for a list of valid values.
> >
> > Possibly dumb question: why isn't the reference clock source specified
> > in the normal ways like the "usb_phy" clock is?
> >
> > Does the value required here depend on what usb_phy clock gets muxed
> > from or something?
> 
> Right, the value indicates what clock "usb_phy" is: whether it comes
> from the core clock controller, the XO crystal, or is some external
> clock.  It's a mux internal to the PHY.

Okay. If its a software controllable mux, is there a particular reason
the DT doesn't describe it as such, i.e. have all 3 clock inputs, and
the driver somehow work out which to use?

Cheers
James

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Re: [PATCH V2 1/3] phy: Add binding document for Pistachio USB2.0 PHY

[Andrew Bresticker]

On Tue, May 5, 2015 at 3:43 PM, James Hogan <james.hogan-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org> wrote:
> On Tue, May 05, 2015 at 03:16:23PM -0700, Andrew Bresticker wrote:
>> Hi James,
>>
>> On Tue, May 5, 2015 at 3:01 PM, James Hogan <james.hogan-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org> wrote:
>> > Hi Andrew,
>> >
>> > On Tue, Apr 07, 2015 at 03:04:16PM -0700, Andrew Bresticker wrote:
>> >> Add a binding document for the USB2.0 PHY found on the IMG Pistachio SoC.
>> >>
>> >> Signed-off-by: Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
>> >> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> >> Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
>> >> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
>> >> Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
>> >> Cc: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>> >> ---
>> >> No changes from v1.
>> >> ---
>> >>  .../devicetree/bindings/phy/pistachio-usb-phy.txt  | 29 ++++++++++++++++++++++
>> >>  include/dt-bindings/phy/phy-pistachio-usb.h        | 16 ++++++++++++
>> >>  2 files changed, 45 insertions(+)
>> >>  create mode 100644 Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
>> >>  create mode 100644 include/dt-bindings/phy/phy-pistachio-usb.h
>> >>
>> >> diff --git a/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
>> >> new file mode 100644
>> >> index 0000000..afbc7e2
>> >> --- /dev/null
>> >> +++ b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
>> >> @@ -0,0 +1,29 @@
>> >> +IMG Pistachio USB PHY
>> >> +=====================
>> >> +
>> >> +Required properties:
>> >> +--------------------
>> >> + - compatible: Must be "img,pistachio-usb-phy".
>> >> + - #phy-cells: Must be 0.  See ./phy-bindings.txt for details.
>> >> + - clocks: Must contain an entry for each entry in clock-names.
>> >> +   See ../clock/clock-bindings.txt for details.
>> >> + - clock-names: Must include "usb_phy".
>> >> + - img,cr-top: Must constain a phandle to the CR_TOP syscon node.
>> >> + - img,refclk: Indicates the reference clock source for the USB PHY.
>> >> +   See <dt-bindings/phy/phy-pistachio-usb.h> for a list of valid values.
>> >
>> > Possibly dumb question: why isn't the reference clock source specified
>> > in the normal ways like the "usb_phy" clock is?
>> >
>> > Does the value required here depend on what usb_phy clock gets muxed
>> > from or something?
>>
>> Right, the value indicates what clock "usb_phy" is: whether it comes
>> from the core clock controller, the XO crystal, or is some external
>> clock.  It's a mux internal to the PHY.
>
> Okay. If its a software controllable mux, is there a particular reason
> the DT doesn't describe it as such, i.e. have all 3 clock inputs, and
> the driver somehow work out which to use?

Well, I'm not sure how the driver would determine which clock to use
without a device-tree property like the one I've got here :).  Also,
all three clock need not be present.

-Andrew
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Re: [PATCH V2 1/3] phy: Add binding document for Pistachio USB2.0 PHY

[James Hogan]

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On Tue, May 05, 2015 at 04:09:31PM -0700, Andrew Bresticker wrote:
> On Tue, May 5, 2015 at 3:43 PM, James Hogan <james.hogan@imgtec.com> wrote:
> > On Tue, May 05, 2015 at 03:16:23PM -0700, Andrew Bresticker wrote:
> >> Hi James,
> >>
> >> On Tue, May 5, 2015 at 3:01 PM, James Hogan <james.hogan@imgtec.com> wrote:
> >> > Hi Andrew,
> >> >
> >> > On Tue, Apr 07, 2015 at 03:04:16PM -0700, Andrew Bresticker wrote:
> >> >> Add a binding document for the USB2.0 PHY found on the IMG Pistachio SoC.
> >> >>
> >> >> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> >> >> Cc: Rob Herring <robh+dt@kernel.org>
> >> >> Cc: Pawel Moll <pawel.moll@arm.com>
> >> >> Cc: Mark Rutland <mark.rutland@arm.com>
> >> >> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
> >> >> Cc: Kumar Gala <galak@codeaurora.org>
> >> >> ---
> >> >> No changes from v1.
> >> >> ---
> >> >>  .../devicetree/bindings/phy/pistachio-usb-phy.txt  | 29 ++++++++++++++++++++++
> >> >>  include/dt-bindings/phy/phy-pistachio-usb.h        | 16 ++++++++++++
> >> >>  2 files changed, 45 insertions(+)
> >> >>  create mode 100644 Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
> >> >>  create mode 100644 include/dt-bindings/phy/phy-pistachio-usb.h
> >> >>
> >> >> diff --git a/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
> >> >> new file mode 100644
> >> >> index 0000000..afbc7e2
> >> >> --- /dev/null
> >> >> +++ b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
> >> >> @@ -0,0 +1,29 @@
> >> >> +IMG Pistachio USB PHY
> >> >> +=====================
> >> >> +
> >> >> +Required properties:
> >> >> +--------------------
> >> >> + - compatible: Must be "img,pistachio-usb-phy".
> >> >> + - #phy-cells: Must be 0.  See ./phy-bindings.txt for details.
> >> >> + - clocks: Must contain an entry for each entry in clock-names.
> >> >> +   See ../clock/clock-bindings.txt for details.
> >> >> + - clock-names: Must include "usb_phy".
> >> >> + - img,cr-top: Must constain a phandle to the CR_TOP syscon node.
> >> >> + - img,refclk: Indicates the reference clock source for the USB PHY.
> >> >> +   See <dt-bindings/phy/phy-pistachio-usb.h> for a list of valid values.
> >> >
> >> > Possibly dumb question: why isn't the reference clock source specified
> >> > in the normal ways like the "usb_phy" clock is?
> >> >
> >> > Does the value required here depend on what usb_phy clock gets muxed
> >> > from or something?
> >>
> >> Right, the value indicates what clock "usb_phy" is: whether it comes
> >> from the core clock controller, the XO crystal, or is some external
> >> clock.  It's a mux internal to the PHY.
> >
> > Okay. If its a software controllable mux, is there a particular reason
> > the DT doesn't describe it as such, i.e. have all 3 clock inputs, and
> > the driver somehow work out which to use?
> 
> Well, I'm not sure how the driver would determine which clock to use
> without a device-tree property like the one I've got here :).  Also,

Does it make sense to just look for the "best" usable source clock based
on the supported rates listed in fsel_rate_map[] (for some definition of
"best" such as "fastest" / "slowest" / "first usable"), or are things
just not that simple?

I'm just wondering how the DT writer would decide, since it seems to
come down to a policy decision rather than a description of the
hardware, which should probably be avoided in DT bindings if possible.

If it really can't be avoided, then fair enough.

Cheers
James

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Re: [PATCH V2 1/3] phy: Add binding document for Pistachio USB2.0 PHY

[Andrew Bresticker]

On Tue, May 5, 2015 at 4:35 PM, James Hogan <james.hogan-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org> wrote:
> On Tue, May 05, 2015 at 04:09:31PM -0700, Andrew Bresticker wrote:
>> On Tue, May 5, 2015 at 3:43 PM, James Hogan <james.hogan-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org> wrote:
>> > On Tue, May 05, 2015 at 03:16:23PM -0700, Andrew Bresticker wrote:
>> >> Hi James,
>> >>
>> >> On Tue, May 5, 2015 at 3:01 PM, James Hogan <james.hogan-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org> wrote:
>> >> > Hi Andrew,
>> >> >
>> >> > On Tue, Apr 07, 2015 at 03:04:16PM -0700, Andrew Bresticker wrote:
>> >> >> Add a binding document for the USB2.0 PHY found on the IMG Pistachio SoC.
>> >> >>
>> >> >> Signed-off-by: Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
>> >> >> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> >> >> Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
>> >> >> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
>> >> >> Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
>> >> >> Cc: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>> >> >> ---
>> >> >> No changes from v1.
>> >> >> ---
>> >> >>  .../devicetree/bindings/phy/pistachio-usb-phy.txt  | 29 ++++++++++++++++++++++
>> >> >>  include/dt-bindings/phy/phy-pistachio-usb.h        | 16 ++++++++++++
>> >> >>  2 files changed, 45 insertions(+)
>> >> >>  create mode 100644 Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
>> >> >>  create mode 100644 include/dt-bindings/phy/phy-pistachio-usb.h
>> >> >>
>> >> >> diff --git a/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
>> >> >> new file mode 100644
>> >> >> index 0000000..afbc7e2
>> >> >> --- /dev/null
>> >> >> +++ b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
>> >> >> @@ -0,0 +1,29 @@
>> >> >> +IMG Pistachio USB PHY
>> >> >> +=====================
>> >> >> +
>> >> >> +Required properties:
>> >> >> +--------------------
>> >> >> + - compatible: Must be "img,pistachio-usb-phy".
>> >> >> + - #phy-cells: Must be 0.  See ./phy-bindings.txt for details.
>> >> >> + - clocks: Must contain an entry for each entry in clock-names.
>> >> >> +   See ../clock/clock-bindings.txt for details.
>> >> >> + - clock-names: Must include "usb_phy".
>> >> >> + - img,cr-top: Must constain a phandle to the CR_TOP syscon node.
>> >> >> + - img,refclk: Indicates the reference clock source for the USB PHY.
>> >> >> +   See <dt-bindings/phy/phy-pistachio-usb.h> for a list of valid values.
>> >> >
>> >> > Possibly dumb question: why isn't the reference clock source specified
>> >> > in the normal ways like the "usb_phy" clock is?
>> >> >
>> >> > Does the value required here depend on what usb_phy clock gets muxed
>> >> > from or something?
>> >>
>> >> Right, the value indicates what clock "usb_phy" is: whether it comes
>> >> from the core clock controller, the XO crystal, or is some external
>> >> clock.  It's a mux internal to the PHY.
>> >
>> > Okay. If its a software controllable mux, is there a particular reason
>> > the DT doesn't describe it as such, i.e. have all 3 clock inputs, and
>> > the driver somehow work out which to use?
>>
>> Well, I'm not sure how the driver would determine which clock to use
>> without a device-tree property like the one I've got here :).  Also,
>
> Does it make sense to just look for the "best" usable source clock based
> on the supported rates listed in fsel_rate_map[] (for some definition of
> "best" such as "fastest" / "slowest" / "first usable"), or are things
> just not that simple?
>
> I'm just wondering how the DT writer would decide, since it seems to
> come down to a policy decision rather than a description of the
> hardware, which should probably be avoided in DT bindings if possible.

Ah, sorry if that was unclear - this *is* describing a hardware
property.  The DT author would pick a value by looking at which clock
is connected to the PHY in the schematic.

-Andrew
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Re: [PATCH V2 1/3] phy: Add binding document for Pistachio USB2.0 PHY

[James Hogan]

[-- Attachment #1: Type: text/plain, Size: 4387 bytes --]

On Tue, May 05, 2015 at 06:06:08PM -0700, Andrew Bresticker wrote:
> On Tue, May 5, 2015 at 4:35 PM, James Hogan <james.hogan-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org> wrote:
> > On Tue, May 05, 2015 at 04:09:31PM -0700, Andrew Bresticker wrote:
> >> On Tue, May 5, 2015 at 3:43 PM, James Hogan <james.hogan-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org> wrote:
> >> > On Tue, May 05, 2015 at 03:16:23PM -0700, Andrew Bresticker wrote:
> >> >> Hi James,
> >> >>
> >> >> On Tue, May 5, 2015 at 3:01 PM, James Hogan <james.hogan-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org> wrote:
> >> >> > Hi Andrew,
> >> >> >
> >> >> > On Tue, Apr 07, 2015 at 03:04:16PM -0700, Andrew Bresticker wrote:
> >> >> >> Add a binding document for the USB2.0 PHY found on the IMG Pistachio SoC.
> >> >> >>
> >> >> >> Signed-off-by: Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> >> >> >> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> >> >> >> Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> >> >> >> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> >> >> >> Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
> >> >> >> Cc: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> >> >> >> ---
> >> >> >> No changes from v1.
> >> >> >> ---
> >> >> >>  .../devicetree/bindings/phy/pistachio-usb-phy.txt  | 29 ++++++++++++++++++++++
> >> >> >>  include/dt-bindings/phy/phy-pistachio-usb.h        | 16 ++++++++++++
> >> >> >>  2 files changed, 45 insertions(+)
> >> >> >>  create mode 100644 Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
> >> >> >>  create mode 100644 include/dt-bindings/phy/phy-pistachio-usb.h
> >> >> >>
> >> >> >> diff --git a/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
> >> >> >> new file mode 100644
> >> >> >> index 0000000..afbc7e2
> >> >> >> --- /dev/null
> >> >> >> +++ b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
> >> >> >> @@ -0,0 +1,29 @@
> >> >> >> +IMG Pistachio USB PHY
> >> >> >> +=====================
> >> >> >> +
> >> >> >> +Required properties:
> >> >> >> +--------------------
> >> >> >> + - compatible: Must be "img,pistachio-usb-phy".
> >> >> >> + - #phy-cells: Must be 0.  See ./phy-bindings.txt for details.
> >> >> >> + - clocks: Must contain an entry for each entry in clock-names.
> >> >> >> +   See ../clock/clock-bindings.txt for details.
> >> >> >> + - clock-names: Must include "usb_phy".
> >> >> >> + - img,cr-top: Must constain a phandle to the CR_TOP syscon node.
> >> >> >> + - img,refclk: Indicates the reference clock source for the USB PHY.
> >> >> >> +   See <dt-bindings/phy/phy-pistachio-usb.h> for a list of valid values.
> >> >> >
> >> >> > Possibly dumb question: why isn't the reference clock source specified
> >> >> > in the normal ways like the "usb_phy" clock is?
> >> >> >
> >> >> > Does the value required here depend on what usb_phy clock gets muxed
> >> >> > from or something?
> >> >>
> >> >> Right, the value indicates what clock "usb_phy" is: whether it comes
> >> >> from the core clock controller, the XO crystal, or is some external
> >> >> clock.  It's a mux internal to the PHY.
> >> >
> >> > Okay. If its a software controllable mux, is there a particular reason
> >> > the DT doesn't describe it as such, i.e. have all 3 clock inputs, and
> >> > the driver somehow work out which to use?
> >>
> >> Well, I'm not sure how the driver would determine which clock to use
> >> without a device-tree property like the one I've got here :).  Also,
> >
> > Does it make sense to just look for the "best" usable source clock based
> > on the supported rates listed in fsel_rate_map[] (for some definition of
> > "best" such as "fastest" / "slowest" / "first usable"), or are things
> > just not that simple?
> >
> > I'm just wondering how the DT writer would decide, since it seems to
> > come down to a policy decision rather than a description of the
> > hardware, which should probably be avoided in DT bindings if possible.
> 
> Ah, sorry if that was unclear - this *is* describing a hardware
> property.  The DT author would pick a value by looking at which clock
> is connected to the PHY in the schematic.

Okay cool. Sorry for the noise.

Thanks
James

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[PATCH V2 2/3] phy: Add driver for Pistachio USB2.0 PHY

[Andrew Bresticker]

Add a driver for the USB2.0 PHY found on the IMG Pistachio SoC.

Signed-off-by: Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
Changes from v1:
 - Fixed a couple of typos
---
 drivers/phy/Kconfig             |   7 ++
 drivers/phy/Makefile            |   1 +
 drivers/phy/phy-pistachio-usb.c | 206 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 214 insertions(+)
 create mode 100644 drivers/phy/phy-pistachio-usb.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 2962de2..717f30d 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -225,6 +225,13 @@ config PHY_EXYNOS5_USBDRD
 	  This driver provides PHY interface for USB 3.0 DRD controller
 	  present on Exynos5 SoC series.
 
+config PHY_PISTACHIO_USB
+	tristate "IMG Pistachio USB2.0 PHY driver"
+	depends on MACH_PISTACHIO
+	select GENERIC_PHY
+	help
+	  Enable this to support the USB2.0 PHY on the IMG Pistachio SoC.
+
 config PHY_QCOM_APQ8064_SATA
 	tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
 	depends on ARCH_QCOM
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f080e1b..e561708 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -38,3 +38,4 @@ obj-$(CONFIG_PHY_STIH41X_USB)		+= phy-stih41x-usb.o
 obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs.o
 obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qmp-20nm.o
 obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qmp-14nm.o
+obj-$(CONFIG_PHY_PISTACHIO_USB)		+= phy-pistachio-usb.o
diff --git a/drivers/phy/phy-pistachio-usb.c b/drivers/phy/phy-pistachio-usb.c
new file mode 100644
index 0000000..c6db35e
--- /dev/null
+++ b/drivers/phy/phy-pistachio-usb.c
@@ -0,0 +1,206 @@
+/*
+ * IMG Pistachio USB PHY driver
+ *
+ * Copyright (C) 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/phy/phy-pistachio-usb.h>
+
+#define USB_PHY_CONTROL1				0x04
+#define USB_PHY_CONTROL1_FSEL_SHIFT			2
+#define USB_PHY_CONTROL1_FSEL_MASK			0x7
+
+#define USB_PHY_STRAP_CONTROL				0x10
+#define USB_PHY_STRAP_CONTROL_REFCLK_SHIFT		4
+#define USB_PHY_STRAP_CONTROL_REFCLK_MASK		0x3
+
+#define USB_PHY_STATUS					0x14
+#define USB_PHY_STATUS_RX_PHY_CLK			BIT(9)
+#define USB_PHY_STATUS_RX_UTMI_CLK			BIT(8)
+#define USB_PHY_STATUS_VBUS_FAULT			BIT(7)
+
+struct pistachio_usb_phy {
+	struct device *dev;
+	struct regmap *cr_top;
+	struct clk *phy_clk;
+	unsigned int refclk;
+};
+
+static const unsigned long fsel_rate_map[] = {
+	9600000,
+	10000000,
+	12000000,
+	19200000,
+	20000000,
+	24000000,
+	0,
+	50000000,
+};
+
+static int pistachio_usb_phy_power_on(struct phy *phy)
+{
+	struct pistachio_usb_phy *p_phy = phy_get_drvdata(phy);
+	unsigned long timeout, rate;
+	unsigned int i;
+	int ret;
+
+	ret = clk_prepare_enable(p_phy->phy_clk);
+	if (ret < 0) {
+		dev_err(p_phy->dev, "Failed to enable PHY clock: %d\n", ret);
+		return ret;
+	}
+
+	regmap_update_bits(p_phy->cr_top, USB_PHY_STRAP_CONTROL,
+			   USB_PHY_STRAP_CONTROL_REFCLK_MASK <<
+			   USB_PHY_STRAP_CONTROL_REFCLK_SHIFT,
+			   p_phy->refclk << USB_PHY_STRAP_CONTROL_REFCLK_SHIFT);
+
+	rate = clk_get_rate(p_phy->phy_clk);
+	if (p_phy->refclk == REFCLK_XO_CRYSTAL && rate != 12000000) {
+		dev_err(p_phy->dev, "Unsupported rate for XO crystal: %ld\n",
+			rate);
+		ret = -EINVAL;
+		goto disable_clk;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(fsel_rate_map); i++) {
+		if (rate == fsel_rate_map[i])
+			break;
+	}
+	if (i == ARRAY_SIZE(fsel_rate_map)) {
+		dev_err(p_phy->dev, "Unsupported clock rate: %lu\n", rate);
+		ret = -EINVAL;
+		goto disable_clk;
+	}
+
+	regmap_update_bits(p_phy->cr_top, USB_PHY_CONTROL1,
+			   USB_PHY_CONTROL1_FSEL_MASK <<
+			   USB_PHY_CONTROL1_FSEL_SHIFT,
+			   i << USB_PHY_CONTROL1_FSEL_SHIFT);
+
+	timeout = jiffies + msecs_to_jiffies(200);
+	while (time_before(jiffies, timeout)) {
+		unsigned int val;
+
+		regmap_read(p_phy->cr_top, USB_PHY_STATUS, &val);
+		if (val & USB_PHY_STATUS_VBUS_FAULT) {
+			dev_err(p_phy->dev, "VBUS fault detected\n");
+			ret = -EIO;
+			goto disable_clk;
+		}
+		if ((val & USB_PHY_STATUS_RX_PHY_CLK) &&
+		    (val & USB_PHY_STATUS_RX_UTMI_CLK))
+			return 0;
+		usleep_range(1000, 1500);
+	}
+
+	dev_err(p_phy->dev, "Timed out waiting for PHY to power on\n");
+	ret = -ETIMEDOUT;
+
+disable_clk:
+	clk_disable_unprepare(p_phy->phy_clk);
+	return ret;
+}
+
+static int pistachio_usb_phy_power_off(struct phy *phy)
+{
+	struct pistachio_usb_phy *p_phy = phy_get_drvdata(phy);
+
+	clk_disable_unprepare(p_phy->phy_clk);
+
+	return 0;
+}
+
+static const struct phy_ops pistachio_usb_phy_ops = {
+	.power_on = pistachio_usb_phy_power_on,
+	.power_off = pistachio_usb_phy_power_off,
+	.owner = THIS_MODULE,
+};
+
+static int pistachio_usb_phy_probe(struct platform_device *pdev)
+{
+	struct pistachio_usb_phy *p_phy;
+	struct phy_provider *provider;
+	struct phy *phy;
+	int ret;
+
+	p_phy = devm_kzalloc(&pdev->dev, sizeof(*p_phy), GFP_KERNEL);
+	if (!p_phy)
+		return -ENOMEM;
+	p_phy->dev = &pdev->dev;
+	platform_set_drvdata(pdev, p_phy);
+
+	p_phy->cr_top = syscon_regmap_lookup_by_phandle(p_phy->dev->of_node,
+							"img,cr-top");
+	if (IS_ERR(p_phy->cr_top)) {
+		dev_err(p_phy->dev, "Failed to get CR_TOP registers: %ld\n",
+			PTR_ERR(p_phy->cr_top));
+		return PTR_ERR(p_phy->cr_top);
+	}
+
+	p_phy->phy_clk = devm_clk_get(p_phy->dev, "usb_phy");
+	if (IS_ERR(p_phy->phy_clk)) {
+		dev_err(p_phy->dev, "Failed to get usb_phy clock: %ld\n",
+			PTR_ERR(p_phy->phy_clk));
+		return PTR_ERR(p_phy->phy_clk);
+	}
+
+	ret = of_property_read_u32(p_phy->dev->of_node, "img,refclk",
+				   &p_phy->refclk);
+	if (ret < 0) {
+		dev_err(p_phy->dev, "No reference clock selector specified\n");
+		return ret;
+	}
+
+	phy = devm_phy_create(p_phy->dev, NULL, &pistachio_usb_phy_ops);
+	if (IS_ERR(phy)) {
+		dev_err(p_phy->dev, "Failed to create PHY: %ld\n",
+			PTR_ERR(phy));
+		return PTR_ERR(phy);
+	}
+	phy_set_drvdata(phy, p_phy);
+
+	provider = devm_of_phy_provider_register(p_phy->dev,
+						 of_phy_simple_xlate);
+	if (IS_ERR(provider)) {
+		dev_err(p_phy->dev, "Failed to register PHY provider: %ld\n",
+			PTR_ERR(provider));
+		return PTR_ERR(provider);
+	}
+
+	return 0;
+}
+
+static const struct of_device_id pistachio_usb_phy_of_match[] = {
+	{ .compatible = "img,pistachio-usb-phy", },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, pistachio_usb_phy_of_match);
+
+static struct platform_driver pistachio_usb_phy_driver = {
+	.probe		= pistachio_usb_phy_probe,
+	.driver		= {
+		.name	= "pistachio-usb-phy",
+		.of_match_table = pistachio_usb_phy_of_match,
+	},
+};
+module_platform_driver(pistachio_usb_phy_driver);
+
+MODULE_AUTHOR("Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>");
+MODULE_DESCRIPTION("IMG Pistachio USB2.0 PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
2.2.0.rc0.207.ga3a616c

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[PATCH V2 3/3] MIPS: pistachio: Enable USB PHY driver in defconfig

[Andrew Bresticker]

Update pistachio_defconfig to enable Pistachio's USB PHY driver.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
---
New for v2.
---
 arch/mips/configs/pistachio_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/configs/pistachio_defconfig b/arch/mips/configs/pistachio_defconfig
index f22e92e..1646cce 100644
--- a/arch/mips/configs/pistachio_defconfig
+++ b/arch/mips/configs/pistachio_defconfig
@@ -272,6 +272,7 @@ CONFIG_IIO=y
 CONFIG_CC10001_ADC=y
 CONFIG_PWM=y
 CONFIG_PWM_IMG=y
+CONFIG_PHY_PISTACHIO_USB=y
 CONFIG_ANDROID=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
-- 
2.2.0.rc0.207.ga3a616c

Re: [PATCH V2 0/3] Pistachio USB2.0 PHY

[Ezequiel Garcia]

Hi Kishon,

> 
> This series adds support for the USB2.0 PHY present on the IMG Pistachio SoC.
> 
> Based on mips-for-linux-next and tested on the IMG Pistachio BuB.  If possible,
> I'd like this to go through the MIPS tree with Kishon's ACK.
> 

Tested-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>

Can we have your Ack for this series so Ralf can pick it?

Thanks!
Ezequiel

> Cc: James Hartley <james.hartley@imgtec.com>
> Cc: Damien Horsley <Damien.Horsley@imgtec.com>
> 
> Changes from v1:
>  - Added patch to enable PHY driver in pistachio_defconfig
>  - Fixed a couple of spelling errors
> 
> Andrew Bresticker (3):
>   phy: Add binding document for Pistachio USB2.0 PHY
>   phy: Add driver for Pistachio USB2.0 PHY
>   MIPS: pistachio: Enable USB PHY driver in defconfig
> 
>  .../devicetree/bindings/phy/pistachio-usb-phy.txt  |  29 +++
>  arch/mips/configs/pistachio_defconfig              |   1 +
>  drivers/phy/Kconfig                                |   7 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-pistachio-usb.c                    | 206 +++++++++++++++++++++
>  include/dt-bindings/phy/phy-pistachio-usb.h        |  16 ++
>  6 files changed, 260 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
>  create mode 100644 drivers/phy/phy-pistachio-usb.c
>  create mode 100644 include/dt-bindings/phy/phy-pistachio-usb.h
> 
> --
> 2.2.0.rc0.207.ga3a616c
> 

-- 
Ezequiel

Re: [PATCH V2 0/3] Pistachio USB2.0 PHY

[Kishon Vijay Abraham I]

On Tuesday 05 May 2015 11:43 PM, Ezequiel Garcia wrote:
> Hi Kishon,
>
>>
>> This series adds support for the USB2.0 PHY present on the IMG Pistachio SoC.
>>
>> Based on mips-for-linux-next and tested on the IMG Pistachio BuB.  If possible,
>> I'd like this to go through the MIPS tree with Kishon's ACK.
>>
>
> Tested-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
>
> Can we have your Ack for this series so Ralf can pick it?

sure..

Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
>
> Thanks!
> Ezequiel
>
>> Cc: James Hartley <james.hartley@imgtec.com>
>> Cc: Damien Horsley <Damien.Horsley@imgtec.com>
>>
>> Changes from v1:
>>   - Added patch to enable PHY driver in pistachio_defconfig
>>   - Fixed a couple of spelling errors
>>
>> Andrew Bresticker (3):
>>    phy: Add binding document for Pistachio USB2.0 PHY
>>    phy: Add driver for Pistachio USB2.0 PHY
>>    MIPS: pistachio: Enable USB PHY driver in defconfig
>>
>>   .../devicetree/bindings/phy/pistachio-usb-phy.txt  |  29 +++
>>   arch/mips/configs/pistachio_defconfig              |   1 +
>>   drivers/phy/Kconfig                                |   7 +
>>   drivers/phy/Makefile                               |   1 +
>>   drivers/phy/phy-pistachio-usb.c                    | 206 +++++++++++++++++++++
>>   include/dt-bindings/phy/phy-pistachio-usb.h        |  16 ++
>>   6 files changed, 260 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
>>   create mode 100644 drivers/phy/phy-pistachio-usb.c
>>   create mode 100644 include/dt-bindings/phy/phy-pistachio-usb.h
>>
>> --
>> 2.2.0.rc0.207.ga3a616c
>>
>

Re: [PATCH V2 0/3] Pistachio USB2.0 PHY

[Andrew Bresticker]

On Mon, May 11, 2015 at 7:45 AM, Kishon Vijay Abraham I <kishon@ti.com> wrote:
>
>
> On Tuesday 05 May 2015 11:43 PM, Ezequiel Garcia wrote:
>>
>> Hi Kishon,
>>
>>>
>>> This series adds support for the USB2.0 PHY present on the IMG Pistachio
>>> SoC.
>>>
>>> Based on mips-for-linux-next and tested on the IMG Pistachio BuB.  If
>>> possible,
>>> I'd like this to go through the MIPS tree with Kishon's ACK.
>>>
>>
>> Tested-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
>>
>> Can we have your Ack for this series so Ralf can pick it?
>
>
> sure..
>
> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>

Ralf, could you pick up this series for 4.2?

Thanks,
Andrew

Re: [PATCH V2 0/3] Pistachio USB2.0 PHY

[Kishon Vijay Abraham I]

On Monday 11 May 2015 08:15 PM, Kishon Vijay Abraham I wrote:
>
>
> On Tuesday 05 May 2015 11:43 PM, Ezequiel Garcia wrote:
>> Hi Kishon,
>>
>>>
>>> This series adds support for the USB2.0 PHY present on the IMG Pistachio SoC.
>>>
>>> Based on mips-for-linux-next and tested on the IMG Pistachio BuB.  If possible,
>>> I'd like this to go through the MIPS tree with Kishon's ACK.
>>>
>>
>> Tested-by: Ezequiel Garcia <ezequiel.garcia-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
>>
>> Can we have your Ack for this series so Ralf can pick it?
>
> sure..
>
> Acked-by: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>

I'm not sure if this has been merged yet. But this will cause conflicts with 
other PHY patches in Makefile and Kconfig when linus merges to his tree. I'd 
prefer the phy patches go in PHY tree itself.

Thanks
Kishon
>>
>> Thanks!
>> Ezequiel
>>
>>> Cc: James Hartley <james.hartley-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
>>> Cc: Damien Horsley <Damien.Horsley-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
>>>
>>> Changes from v1:
>>>    - Added patch to enable PHY driver in pistachio_defconfig
>>>    - Fixed a couple of spelling errors
>>>
>>> Andrew Bresticker (3):
>>>     phy: Add binding document for Pistachio USB2.0 PHY
>>>     phy: Add driver for Pistachio USB2.0 PHY
>>>     MIPS: pistachio: Enable USB PHY driver in defconfig
>>>
>>>    .../devicetree/bindings/phy/pistachio-usb-phy.txt  |  29 +++
>>>    arch/mips/configs/pistachio_defconfig              |   1 +
>>>    drivers/phy/Kconfig                                |   7 +
>>>    drivers/phy/Makefile                               |   1 +
>>>    drivers/phy/phy-pistachio-usb.c                    | 206 +++++++++++++++++++++
>>>    include/dt-bindings/phy/phy-pistachio-usb.h        |  16 ++
>>>    6 files changed, 260 insertions(+)
>>>    create mode 100644 Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
>>>    create mode 100644 drivers/phy/phy-pistachio-usb.c
>>>    create mode 100644 include/dt-bindings/phy/phy-pistachio-usb.h
>>>
>>> --
>>> 2.2.0.rc0.207.ga3a616c
>>>
>>
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Re: [PATCH V2 0/3] Pistachio USB2.0 PHY

[Andrew Bresticker]

On Tue, Jun 2, 2015 at 11:07 PM, Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org> wrote:
>
>
> On Monday 11 May 2015 08:15 PM, Kishon Vijay Abraham I wrote:
>>
>>
>>
>> On Tuesday 05 May 2015 11:43 PM, Ezequiel Garcia wrote:
>>>
>>> Hi Kishon,
>>>
>>>>
>>>> This series adds support for the USB2.0 PHY present on the IMG Pistachio
>>>> SoC.
>>>>
>>>> Based on mips-for-linux-next and tested on the IMG Pistachio BuB.  If
>>>> possible,
>>>> I'd like this to go through the MIPS tree with Kishon's ACK.
>>>>
>>>
>>> Tested-by: Ezequiel Garcia <ezequiel.garcia-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
>>>
>>> Can we have your Ack for this series so Ralf can pick it?
>>
>>
>> sure..
>>
>> Acked-by: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
>
>
> I'm not sure if this has been merged yet. But this will cause conflicts with
> other PHY patches in Makefile and Kconfig when linus merges to his tree. I'd
> prefer the phy patches go in PHY tree itself.

It doesn't look like Ralf has picked these up, so if you want to take
them through your tree, that would be great.

Thanks,
Andrew
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Re: [PATCH V2 0/3] Pistachio USB2.0 PHY

[Andrew Bresticker]

On Wed, Jun 3, 2015 at 8:44 AM, Andrew Bresticker <abrestic@chromium.org> wrote:
> On Tue, Jun 2, 2015 at 11:07 PM, Kishon Vijay Abraham I <kishon@ti.com> wrote:
>>
>>
>> On Monday 11 May 2015 08:15 PM, Kishon Vijay Abraham I wrote:
>>>
>>>
>>>
>>> On Tuesday 05 May 2015 11:43 PM, Ezequiel Garcia wrote:
>>>>
>>>> Hi Kishon,
>>>>
>>>>>
>>>>> This series adds support for the USB2.0 PHY present on the IMG Pistachio
>>>>> SoC.
>>>>>
>>>>> Based on mips-for-linux-next and tested on the IMG Pistachio BuB.  If
>>>>> possible,
>>>>> I'd like this to go through the MIPS tree with Kishon's ACK.
>>>>>
>>>>
>>>> Tested-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
>>>>
>>>> Can we have your Ack for this series so Ralf can pick it?
>>>
>>>
>>> sure..
>>>
>>> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
>>
>>
>> I'm not sure if this has been merged yet. But this will cause conflicts with
>> other PHY patches in Makefile and Kconfig when linus merges to his tree. I'd
>> prefer the phy patches go in PHY tree itself.
>
> It doesn't look like Ralf has picked these up, so if you want to take
> them through your tree, that would be great.

Actually I take that back, looks like Ralf just picked them up.