From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Bresticker Subject: Re: [PATCH 12/13] cpufreq: Add cpufreq driver for Tegra124 Date: Fri, 11 Jul 2014 09:33:47 -0700 Message-ID: References: <1405028569-14253-1-git-send-email-ttynkkynen@nvidia.com> <1405028569-14253-13-git-send-email-ttynkkynen@nvidia.com> <20140711091207.GY23218@tbergstrom-lnx.Nvidia.com> <20140711145735.GB6523@ulmo> <53BFFEAD.7000405@nvidia.com> <20140711151501.GA25810@ulmo> <53C002BE.90805@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: <53C002BE.90805-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Tuomas Tynkkynen Cc: Thierry Reding , Peter De Schrijver , Viresh Kumar , "linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Linux Kernel Mailing List , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Stephen Warren , Prashant Gaikwad , Mike Turquette , "Rafael J. Wysocki" , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" List-Id: devicetree@vger.kernel.org On Fri, Jul 11, 2014 at 8:29 AM, Tuomas Tynkkynen wrote: > > On the hardware level, the two I2C controllers sharing the same pins > have knowledge of each other and won't start transmitting if the bus > is busy (something different from the usual I2C arbitration, that is). > I guess on the kernel side there could be a problem if the voltage register > is marked cached in the PMIC driver's regmap. Yeah, in our tree we have a hack to disable regcache for SD0_VOLTAGE. Other than the value reported to userspace being wrong, leaving it as cacheable shouldn't be an issue if no other drivers try to read/write that register. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html