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Tue, 02 Sep 2025 17:55:47 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250828-t210-actmon-v1-0-aeb19ec1f244@gmail.com> <25477710.6Emhk5qWAg@senjougahara> In-Reply-To: <25477710.6Emhk5qWAg@senjougahara> From: Aaron Kling Date: Tue, 2 Sep 2025 19:55:36 -0500 X-Gm-Features: Ac12FXyiMmcEPBnXVhKhTD563A-aPjl9MtxAaVDXptfjkCQhW65cAeinrQCkxqE Message-ID: Subject: Re: [PATCH RFC 0/7] Support Tegra210 actmon for dynamic EMC scaling To: Mikko Perttunen Cc: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Thierry Reding , Jonathan Hunter , Krzysztof Kozlowski , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Sep 2, 2025 at 6:51=E2=80=AFPM Mikko Perttunen wrote: > > On Friday, August 29, 2025 1:01=E2=80=AFPM Aaron Kling via B4 Relay wrote= : > > This series adds interconnect support to tegra210 MC and EMC, then > > enables actmon. This enables dynamic emc scaling. > > > > This series is marked RFC for two reasons: > > > > 1) Calculating rate from bandwidth usage results in double the expected > > rate. I thought this might be due to the ram being 64-bit, but the > > related CFG5 register reports 32-bit on both p2371-2180 and > > p3450-0000. I'm using the calculation used for Tegra124 and haven't > > seen seen anything obviously different between the ram handling on > > these archs to cause a different result. I have considered that the > > number of channels might affect the reporting, and factoring in that > > variable does result in the correct rate, but I don't want to assume > > that's correct without confirmation. > > My thinking is also that this is due to the channels. L4T says > > /* > * Tegra11 has dual 32-bit memory channels, while > * Tegra12 has single 64-bit memory channel. Tegra21 > * has either dual 32 bit channels (LP4) or a single > * 64 bit channel (LP3). > * > * MC effectively operates as 64-bit bus. > */ > > next to calculating bw_to_freq, and proceeds to use the same divisor for = T114 to T210. Regarding the CFG5_DRAM_WIDTH field, I'm guessing it gives th= e width for one channel, but I'm not sure how it would function for other m= emory types -- I'm not sure if any Tegra210 devices using memory other than= LPDDR4 were ever released. Mmm. "MC effectively operates as 64-bit bus." So I could just hardcode 64-bit dram width and skip reading the CFG5_DRAM_WIDTH field altogether. And regardless of the layout, if I'm reading that correctly, the calculation would remain correct. That should get the numbers I'm expecting on the devkits, but I will verify again before uploading a new revision. Aaron