[PATCH v2 4/5] clk: renesas: Add r8a774a1 CPG Core Clock Definitions

[PATCH v2 4/5] clk: renesas: Add r8a774a1 CPG Core Clock Definitions

[Biju Das]

Add all RZ/G2M Clock Pulse Generator Core Clock Outputs, as listed in
Table 8.2b ("List of Clocks [RZ/G2M]") of the RZ/G2M Hardware User's
Manual.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
V1--> V2
  * Removed internal clock POST2.
---
 include/dt-bindings/clock/r8a774a1-cpg-mssr.h | 58 +++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 include/dt-bindings/clock/r8a774a1-cpg-mssr.h

diff --git a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
new file mode 100644
index 0000000..9bc5d45
--- /dev/null
+++ b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a774a1 CPG Core Clocks */
+#define R8A774A1_CLK_Z			0
+#define R8A774A1_CLK_Z2			1
+#define R8A774A1_CLK_ZG			2
+#define R8A774A1_CLK_ZTR		3
+#define R8A774A1_CLK_ZTRD2		4
+#define R8A774A1_CLK_ZT			5
+#define R8A774A1_CLK_ZX			6
+#define R8A774A1_CLK_S0D1		7
+#define R8A774A1_CLK_S0D2		8
+#define R8A774A1_CLK_S0D3		9
+#define R8A774A1_CLK_S0D4		10
+#define R8A774A1_CLK_S0D6		11
+#define R8A774A1_CLK_S0D8		12
+#define R8A774A1_CLK_S0D12		13
+#define R8A774A1_CLK_S1D2		14
+#define R8A774A1_CLK_S1D4		15
+#define R8A774A1_CLK_S2D1		16
+#define R8A774A1_CLK_S2D2		17
+#define R8A774A1_CLK_S2D4		18
+#define R8A774A1_CLK_S3D1		19
+#define R8A774A1_CLK_S3D2		20
+#define R8A774A1_CLK_S3D4		21
+#define R8A774A1_CLK_LB			22
+#define R8A774A1_CLK_CL			23
+#define R8A774A1_CLK_ZB3		24
+#define R8A774A1_CLK_ZB3D2		25
+#define R8A774A1_CLK_ZB3D4		26
+#define R8A774A1_CLK_CR			27
+#define R8A774A1_CLK_CRD2		28
+#define R8A774A1_CLK_SD0H		29
+#define R8A774A1_CLK_SD0		30
+#define R8A774A1_CLK_SD1H		31
+#define R8A774A1_CLK_SD1		32
+#define R8A774A1_CLK_SD2H		33
+#define R8A774A1_CLK_SD2		34
+#define R8A774A1_CLK_SD3H		35
+#define R8A774A1_CLK_SD3		36
+#define R8A774A1_CLK_RPC		37
+#define R8A774A1_CLK_RPCD2		38
+#define R8A774A1_CLK_MSO		39
+#define R8A774A1_CLK_HDMI		40
+#define R8A774A1_CLK_CSI0		41
+#define R8A774A1_CLK_CP			42
+#define R8A774A1_CLK_CPEX		43
+#define R8A774A1_CLK_R			44
+#define R8A774A1_CLK_OSC		45
+
+#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */
-- 
2.7.4

Re: [PATCH v2 4/5] clk: renesas: Add r8a774a1 CPG Core Clock Definitions

[Geert Uytterhoeven]

Hi Biju,

On Thu, Aug 2, 2018 at 5:02 PM Biju Das <biju.das@bp.renesas.com> wrote:
> Add all RZ/G2M Clock Pulse Generator Core Clock Outputs, as listed in
> Table 8.2b ("List of Clocks [RZ/G2M]") of the RZ/G2M Hardware User's
> Manual.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> V1--> V2
>   * Removed internal clock POST2.

Thanks for the update!

Will queue in clk-renesas-for-v4.20.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v2 4/5] clk: renesas: Add r8a774a1 CPG Core Clock Definitions

[Biju Das]

Hi Rob,


> Subject: Re: [PATCH v2 4/5] clk: renesas: Add r8a774a1 CPG Core Clock
> Definitions
>
> Hi, this is an automated email from Rob's (experimental) review bot. I found
> a couple of common problems with your patch. Please see below.

Do I need to send another patch? The mail says " Rob's (experimental) review bot".
Previously for RZ/G1C upstreaming I have submitted the patches in similar fashion.
Is anything changed?

> On Thu,  2 Aug 2018 15:56:34 +0100, Biju Das wrote:
> > Add all RZ/G2M Clock Pulse Generator Core Clock Outputs, as listed in
> > Table 8.2b ("List of Clocks [RZ/G2M]") of the RZ/G2M Hardware User's
> > Manual.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> The preferred subject prefix is "dt-bindings: <binding dir>: ...".

Regards,
Biju



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

Re: [PATCH v2 4/5] clk: renesas: Add r8a774a1 CPG Core Clock Definitions

[Rob Herring]

On Fri, Aug 10, 2018 at 1:35 AM Biju Das <biju.das@bp.renesas.com> wrote:
>
> Hi Rob,
>
>
> > Subject: Re: [PATCH v2 4/5] clk: renesas: Add r8a774a1 CPG Core Clock
> > Definitions
> >
> > Hi, this is an automated email from Rob's (experimental) review bot. I found
> > a couple of common problems with your patch. Please see below.
>
> Do I need to send another patch? The mail says " Rob's (experimental) review bot".

"experimental" in the sense it may not work right. Such as they all
triggered spam filters. But I checked all these mails before they went
out, so the comments are correct.

> Previously for RZ/G1C upstreaming I have submitted the patches in similar fashion.
> Is anything changed?

Yes, I'm tired of manually providing these comments. If there's no
other comments though, then it is fine to apply as is.

Rob