From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH v2 1/4] dt-bindings: phy: add binding for the Lantiq VRX200 and ARX300 PCIe PHYs Date: Fri, 5 Jul 2019 10:20:43 -0600 Message-ID: References: <20190704122319.8983-1-martin.blumenstingl@googlemail.com> <20190704122319.8983-2-martin.blumenstingl@googlemail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: <20190704122319.8983-2-martin.blumenstingl@googlemail.com> Sender: linux-kernel-owner@vger.kernel.org To: Martin Blumenstingl Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, John Crispin , Kishon Vijay Abraham I , "linux-kernel@vger.kernel.org" , Hauke Mehrtens , Paul Burton , Ralf Baechle , Mark Rutland , Martin Schiller List-Id: devicetree@vger.kernel.org On Thu, Jul 4, 2019 at 6:23 AM Martin Blumenstingl wrote: > > Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs. > The IP block contains settings for the PHY and a PLL. > The PLL mode is configurable through a dedicated #phy-cell in .dts. > > Signed-off-by: Martin Blumenstingl > --- > .../bindings/phy/lantiq,vrx200-pcie-phy.yaml | 95 +++++++++++++++++++ > .../dt-bindings/phy/phy-lantiq-vrx200-pcie.h | 11 +++ > 2 files changed, 106 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml > create mode 100644 include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h Reviewed-by: Rob Herring