From: Rob Herring <robh@kernel.org>
To: Trent Piepho <tpiepho@impinj.com>
Cc: Lucas Stach <l.stach@pengutronix.de>,
Andrey Smirnov <andrew.smirnov@gmail.com>,
Dong Aisheng <aisheng.dong@nxp.com>,
Richard Zhu <hongxing.zhu@nxp.com>,
Chris Healy <cphealy@gmail.com>,
NXP Linux Team <linux-imx@nxp.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
devicetree@vger.kernel.org,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Fabio Estevam <fabio.estevam@nxp.com>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Leonard Crestez <leonard.crestez@nxp.com>,
linux-pci@vger.kernel.org
Subject: Re: [PATCH v3 3/3] PCI: imx6: Add support for i.MX8MQ
Date: Thu, 20 Dec 2018 09:00:01 -0600 [thread overview]
Message-ID: <CAL_JsqJBxZw225qqWfCFa8UqADtGOUCjFogo6Pb2bd8bKwz3nA@mail.gmail.com> (raw)
In-Reply-To: <1545268969.22930.77.camel@impinj.com>
On Wed, Dec 19, 2018 at 7:22 PM Trent Piepho <tpiepho@impinj.com> wrote:
>
> On Wed, 2018-12-19 at 16:47 -0800, Andrey Smirnov wrote:
> >
> > > > This series initially added explicit offsets but I suggested a single
> > > > "controller-id" because:
> > > > * There are multiple bit and byte offsets
> > > > * Other imx8 SOCs also have 2x pcie with other bit/byte offsets
> > > >
> > > > Hiding this behind a compatible string and single "controller-id" seem
> > > > preferable to elaborating register maps in dt bindings. It also makes
> > > > upgrades simpler: if features are added which use other bits there is no
> > > > need to describe them in DT and deal with compatibility headaches.
> > >
> > > You already have an id for the controllers: the address. Use that if
> > > you don't want to put the register offsets in DT.
> > >
> >
> > Lucas, are you on board with this?
>
> Does address here mean the address from the controller's reg property?
Yes.
> How do you map that address to the controller's index? A giant table
> of every soc so the soc type plus controller register address pair than
> can be looked up in the driver?
You only need the 2-Nth instance addresses. A non-matching address can
be instance 0.
> I.e., on iMX8MQ the controller at 0x33800000 is controller 0 and so on
> for every possible SoC address combination?
>
> Not really a fan of that.
Well, this was not my first suggestion.
> The situation here is that some registers for these controllers are
> interleaved, right? I.e., there's one register somewhere where bit 0
> means enable controller 0 and bit 1 means enable controller 1 and so
> on.
So? The only difference here is an additional mapping step.
> Isn't cell-index already the standard device tree property for this
> kind of setup?
>
> I know cell-index was historically also (ab)used in an attempt to
> provide a fixed kernel device enumeration order, something now handled
> better by chosen node aliases.
Don't use cell-index. Consider it a deprecated relic from OF that is
not used on FDT (though there probably are some cases it did get
used).
Rob
next prev parent reply other threads:[~2018-12-20 15:00 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20181218040702.29231-1-andrew.smirnov@gmail.com>
2018-12-18 4:07 ` [PATCH v3 3/3] PCI: imx6: Add support for i.MX8MQ Andrey Smirnov
2018-12-18 9:34 ` Leonard Crestez
2018-12-18 18:14 ` Andrey Smirnov
2018-12-18 15:15 ` Rob Herring
2018-12-18 18:09 ` Leonard Crestez
2018-12-18 21:10 ` Rob Herring
2018-12-20 0:47 ` Andrey Smirnov
2018-12-20 1:22 ` Trent Piepho
2018-12-20 13:49 ` Leonard Crestez
2018-12-20 15:00 ` Rob Herring [this message]
2018-12-20 15:04 ` Rob Herring
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