devicetree.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Rob Herring <robh+dt@kernel.org>
To: Dinh Nguyen <dinguyen@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
	devicetree@vger.kernel.org, thor.thayer@linux.intel.com,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will.deacon@arm.com>, Borislav Petkov <bp@alien8.de>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
	<linux-arm-kernel@lists.infradead.org>,
	linux-edac@vger.kernel.org
Subject: Re: [PATCH 1/3] Documentation: dt: socfpga: Add Stratix10 ECC Manager binding
Date: Thu, 26 Apr 2018 10:06:37 -0500	[thread overview]
Message-ID: <CAL_JsqKSJ35Da9fDx0kzyC5Gi5ks8k_pDpnTF0beh7YV484o4w@mail.gmail.com> (raw)
In-Reply-To: <8f29ed5c-4e21-6200-23dc-4cadf86d2b96@kernel.org>

On Thu, Apr 26, 2018 at 10:01 AM, Dinh Nguyen <dinguyen@kernel.org> wrote:
>
>
> On 04/26/2018 09:58 AM, Thor Thayer wrote:
>> On 04/26/2018 09:43 AM, Thor Thayer wrote:
>>> On 04/25/2018 09:16 PM, Dinh Nguyen wrote:
>>>>
>>>>
>>>> On 04/24/2018 01:35 PM, thor.thayer@linux.intel.com wrote:
>>>>> From: Thor Thayer <thor.thayer@linux.intel.com>
>>>>>
>>>>> Add the device tree bindings needed to support the Stratix10
>>>>> ECC Manager and SDRAM ECC to the existing bindings.
>>>>>
>>>>> Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
>>>>> ---
>>>>>   .../bindings/arm/altera/socfpga-eccmgr.txt         | 47
>>>>> ++++++++++++++++++++++
>>>>>   1 file changed, 47 insertions(+)
>>>>>
>>>>> diff --git
>>>>> a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
>>>>> b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
>>>>> index 4a1714f96bab..fe48ad293a24 100644
>>>>> --- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
>>>>> +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
>>>>> @@ -231,3 +231,50 @@ Example:
>>>>>                        <48 IRQ_TYPE_LEVEL_HIGH>;
>>>>>           };
>>>>>       };
>>>>> +
>>>>> +Stratix10 SoCFPGA ECC Manager
>>>>> +The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
>>>>> +in a shared register similar to the Arria10. However, ECC requires
>>>>> +access to registers that can only be read in EL3 with SMC calls.
>>>>> +Therefore the device tree is slightly different.
>>>>> +
>>>>> +Required Properties:
>>>>> +- compatible : Should be "altr,socfpga-s10-ecc-manager"
>>>>
>>>> Altera technically doesn't exist anymore, should this be
>>>> "intel,stratix10-ecc-manager"?
>>>>
>>> I was trying to be consistent with the older names but I agree with
>>> your argument. I will change this. Thanks
>>>
>> After looking at the Stratix10 device tree, there are only "altr," in
>> there. For instance the top node is:
>>
>> compatible = "altr,socfpga-stratix10";
>>
>> and even the directory that the device tree is in is named "altera"
>>
>> so I'll stick with the existing "altr," designation to be consistent.
>>
>
> That's fine and I don't have any strong inclination for 1 way or
> another. But it's not quite true that there are only "altr" in the dts file.
>
> I did recently switch the clock manager to an intel designation. I
> upstreamed the original stratix10 DTS file back in 2015, before Altera
> was purchased by Intel.
>
> My only argument is that if you're adding new support for devices, it
> should be an intel binding.

I think I would make the switch when you change it at the SoC level
(for a new SoC). IOW, if the top level compatible is using 'intel',
then use that for the device bindings otherwise stick with 'altr' for
that SoC.

Rob

  reply	other threads:[~2018-04-26 15:06 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-24 18:35 [PATCH 0/3] Add SDRAM ECC support for Stratix10 thor.thayer
2018-04-24 18:35 ` [PATCH 1/3] Documentation: dt: socfpga: Add Stratix10 ECC Manager binding thor.thayer
2018-04-26  2:16   ` Dinh Nguyen
2018-04-26 14:43     ` Thor Thayer
2018-04-26 14:58       ` Thor Thayer
2018-04-26 15:01         ` Dinh Nguyen
2018-04-26 15:06           ` Rob Herring [this message]
2018-04-24 18:35 ` [PATCH 2/3] edac: altera: Add support for Stratix10 SDRAM EDAC thor.thayer
2018-04-26  2:14   ` Dinh Nguyen
2018-04-26  6:08     ` Borislav Petkov
2018-04-26 14:42     ` Thor Thayer
2018-04-24 18:35 ` [PATCH 3/3] arm64: dts: stratix10: add sdram ecc thor.thayer

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CAL_JsqKSJ35Da9fDx0kzyC5Gi5ks8k_pDpnTF0beh7YV484o4w@mail.gmail.com \
    --to=robh+dt@kernel.org \
    --cc=bp@alien8.de \
    --cc=catalin.marinas@arm.com \
    --cc=devicetree@vger.kernel.org \
    --cc=dinguyen@kernel.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-edac@vger.kernel.org \
    --cc=mark.rutland@arm.com \
    --cc=mchehab@kernel.org \
    --cc=thor.thayer@linux.intel.com \
    --cc=will.deacon@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).