From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97950C4338F for ; Mon, 16 Aug 2021 18:27:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 68AC360F22 for ; Mon, 16 Aug 2021 18:27:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229987AbhHPS1f (ORCPT ); Mon, 16 Aug 2021 14:27:35 -0400 Received: from mail.kernel.org ([198.145.29.99]:47478 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229966AbhHPS1e (ORCPT ); Mon, 16 Aug 2021 14:27:34 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 5279560F41; Mon, 16 Aug 2021 18:27:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1629138422; bh=J5kTQ9jNl7GtseCHsR5QNLO97/SZNfu88It1yT0aXgE=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=soBU96Am8xpoYrCIDFq34hMvCNLtkV/saokQsws6vR5idXFHlIkTzhfhaFJUeaZTN 7/rz7MbYA+vUxC39AAP//LRFFD+cx58LpziOIaR77NAittHTWUhLl6fGmgP0OsZYPm HNFZMz4UV5GyUK0NwhioXsRLNmZ3v4f1YM35kE9dkgpsohCI97iDQEvZRGpGVHlpem 9ifcfx8E0t4/nXt4+GkWlFQWouvn0jiyEXs0UHSQoCVcquNZrZIww7I97AOZJRXqUX UEEBCsVs5tM172pAD+iUTyUDY1M0txYO0txd6Vlx8aqJSjkPu+sWCPTeRis8SipiK0 EQnA0KFtephVw== Received: by mail-ed1-f45.google.com with SMTP id cq23so10511771edb.12; Mon, 16 Aug 2021 11:27:02 -0700 (PDT) X-Gm-Message-State: AOAM532GfXz/E7QYLNICPFEJnKPMAas4YX86IuUPLBojl73tDlpX2xeH rHU/D+dKNi7i8jui8dvcwl3djBaAAR4Vy6xEQQ== X-Google-Smtp-Source: ABdhPJz6YhgNYjBk8iIsDDdHBbb7lpGhLb6RzR0UMxHzXXHppoWWDik/vzQWomeYCgfQTi6gAbFbYjX0iK/BvYvkAKc= X-Received: by 2002:a05:6402:557:: with SMTP id i23mr21699802edx.373.1629138420901; Mon, 16 Aug 2021 11:27:00 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Rob Herring Date: Mon, 16 Aug 2021 13:26:49 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v7 08/10] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware To: Mauro Carvalho Chehab Cc: Vinod Koul , Bjorn Helgaas , Linuxarm , mauro.chehab@huawei.com, Manivannan Sadhasivam , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Binghui Wang , Lorenzo Pieralisi , Wei Xu , Xiaowei Song , devicetree@vger.kernel.org, linux-arm-kernel , "linux-kernel@vger.kernel.org" , PCI Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Jul 21, 2021 at 3:39 AM Mauro Carvalho Chehab wrote: > > From: Manivannan Sadhasivam > > Add DTS bindings for the HiKey 970 board's PCIe hardware. > > Co-developed-by: Mauro Carvalho Chehab > Signed-off-by: Manivannan Sadhasivam > Signed-off-by: Mauro Carvalho Chehab > --- > arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 71 +++++++++++++++++++ > .../boot/dts/hisilicon/hikey970-pmic.dtsi | 1 - > drivers/pci/controller/dwc/pcie-kirin.c | 12 ---- > 3 files changed, 71 insertions(+), 13 deletions(-) > > diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi > index 1f228612192c..6dfcfcfeedae 100644 > --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi > @@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 { > #clock-cells = <1>; > }; > > + pmctrl: pmctrl@fff31000 { > + compatible = "hisilicon,hi3670-pmctrl", "syscon"; > + reg = <0x0 0xfff31000 0x0 0x1000>; > + #clock-cells = <1>; > + }; > + > iomcu: iomcu@ffd7e000 { > compatible = "hisilicon,hi3670-iomcu", "syscon"; > reg = <0x0 0xffd7e000 0x0 0x1000>; > @@ -660,6 +666,71 @@ gpio28: gpio@fff1d000 { > clock-names = "apb_pclk"; > }; > > + its_pcie: interrupt-controller@f4000000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + reg = <0x0 0xf5100000 0x0 0x100000>; How does this h/w have a GIC-400 (which is GICv2) and then a GIC v3 ITS? > + }; > + > + pcie_phy: pcie-phy@fc000000 { > + compatible = "hisilicon,hi970-pcie-phy"; > + reg = <0x0 0xfc000000 0x0 0x80000>; > + > + phy-supply = <&ldo33>; > + > + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, > + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, > + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, > + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, > + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; > + clock-names = "phy_ref", "aux", > + "apb_phy", "apb_sys", > + "aclk"; > + > + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, > + <&gpio3 1 0 >, <&gpio27 4 0 >; > + > + clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, > + <&gpio17 0 0 >; > + > + /* vboost iboost pre post main */ > + hisilicon,eye-diagram-param = <0xFFFFFFFF 0xFFFFFFFF > + 0xFFFFFFFF 0xFFFFFFFF > + 0xFFFFFFFF>; > + > + #phy-cells = <0>; > + }; > + > + pcie@f4000000 { > + compatible = "hisilicon,kirin970-pcie"; > + reg = <0x0 0xf4000000 0x0 0x1000000>, > + <0x0 0xfc180000 0x0 0x1000>, > + <0x0 0xf5000000 0x0 0x2000>; > + reg-names = "dbi", "apb", "config"; > + bus-range = <0x0 0x1>; > + msi-parent = <&its_pcie>; This means the PCI host doesn't have a MSI controller... > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + phys = <&pcie_phy>; > + ranges = <0x02000000 0x0 0x00000000 > + 0x0 0xf6000000 > + 0x0 0x02000000>; > + num-lanes = <1>; > + #interrupt-cells = <1>; > + interrupts = <0 283 4>; > + interrupt-names = "msi"; But then this says it does...