From: Rob Herring <robh@kernel.org>
To: Sowjanya Komatineni <skomatineni@nvidia.com>
Cc: "mark.rutland@arm.com" <mark.rutland@arm.com>,
Mikko Perttunen <mperttunen@nvidia.com>,
"thierry.reding@gmail.com" <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
"adrian.hunter@intel.com" <adrian.hunter@intel.com>,
"ulf.hansson@linaro.org" <ulf.hansson@linaro.org>,
Preetham Chandru <pchandru@nvidia.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>
Subject: Re: [PATCH V2 1/3] dt-bindings: mmc: tegra: Add pinctrl for pad drive strength config
Date: Thu, 3 Jan 2019 12:35:10 -0600 [thread overview]
Message-ID: <CAL_JsqLWqhspMNPeqYvh-_ynej-KmwVW93OeQ3E7ic+XSDXngg@mail.gmail.com> (raw)
In-Reply-To: <BN7PR12MB2836C77E851E7AC4BCD38BF0C2B00@BN7PR12MB2836.namprd12.prod.outlook.com>
On Fri, Dec 28, 2018 at 6:08 PM Sowjanya Komatineni
<skomatineni@nvidia.com> wrote:
>
> Hi Rob,
>
> >> Add pinctrl for 3V3 and 1V8 pad drive strength configuration for
> >> Tegra210 sdmmc which has pad configuration registers in the pinmux
> >> reigster domain.
> >
> > typo
> >
> >>
> >> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> >> ---
> >> Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 6
> >> +++++-
> >> 1 file changed, 5 insertions(+), 1 deletion(-)
> >>
> >> diff --git
> >> a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> >> b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> >> index 32b4b4e41923..2cecdc71d94c 100644
> >> --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> >> +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> >> @@ -39,12 +39,16 @@ sdhci@c8000200 {
> >> bus-width = <8>;
> >> };
> >>
> >> -Optional properties for Tegra210 and Tegra186:
> >> +Optional properties for Tegra210, Tegra186 and Tegra194:
> >
> >Adding Tegra194, but this patch concerns Tegra210...
> Yes this is mainly part of Tegra210 Patch but pinctrls sdmmc-1v8 and sdmmc-3v3
> also applies for Tegra194 and since it was not mentioned, added Tegra194 as well.
> Does adding Tegra194 in this should come as separate patch?
Same patch is fine, just make the commit message match.
> >
> >> - pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage
> >> configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
> >> for controllers supporting multiple voltage levels. The order of names
> >> should correspond to the pin configuration states in pinctrl-0 and
> >> pinctrl-1.
> >> +- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable
> >> +for
> >
> >These are in addition to the previous values?
> Yes these are additional pinctrl states for pad drive settings which are in pinmux
> Domain and are applicable during calibration process.
Maybe '-cal' instead of '-drv' since that's the mode they apply to.
Rob
prev parent reply other threads:[~2019-01-03 18:35 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-19 22:55 [PATCH V2 1/3] dt-bindings: mmc: tegra: Add pinctrl for pad drive strength config Sowjanya Komatineni
2018-12-19 22:55 ` [PATCH V2 2/3] arm64: dts: tegra210: Add SDMMC Auto-cal settings Sowjanya Komatineni
2018-12-19 22:55 ` [PATCH V2 3/3] mmc: tegra: SDMMC pads auto-calibration Sowjanya Komatineni
2018-12-22 22:33 ` kbuild test robot
2018-12-27 21:33 ` [PATCH V2 1/3] dt-bindings: mmc: tegra: Add pinctrl for pad drive strength config Rob Herring
2018-12-29 0:08 ` Sowjanya Komatineni
2019-01-03 18:35 ` Rob Herring [this message]
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