[PATCH v3 00/37] JZ4780 & CI20 support

[PATCH v3 00/37] JZ4780 & CI20 support

[Paul Burton]

This series introduces initial support for the Ingenic JZ4780 SoC and
the Imagination Technologies MIPS Creator CI20 board which is built
around it. In the process the existing JZ4740 & qi_lb60 code gains
initial support for using DeviceTree such that much of the existing
platform code under arch/mips/jz4740 can be shared.

The series has undergone quite a bit of restructure since v2. Each
patch contains a changelog indicating its differences, but a rough
overview for changes across the series would be:

  - s/jz47xx/ingenic/ in various places, to reflect the fact that
    Ingenic have changed the naming scheme for their newest SoCs
    (now Mxxx).

  - Restructure the Kconfig entries to provide a MACH_INGENIC
    indicating and Ingenic SoC, and have boards select the
    appropriate SoC symbol.

  - Merge DT binding documentation where SoC bindings differ only
    by compatible strings.

  - Capitalise "JZ" in SoC names, where not identifiers in code,
    to match the way Ingenic write them.

  - Further clean up the Ingenic SoC interrupt controller driver
    and move it under drivers/irqchip/.

Review appreciated, and hopefully this can make it into v4.2.

Thanks,
    Paul

Paul Burton (37):
  devicetree/bindings: add Ingenic Semiconductor vendor prefix
  devicetree/bindings: add Qi Hardware vendor prefix
  MIPS: JZ4740: introduce CONFIG_MACH_INGENIC
  MIPS: ingenic: add newer vendor IDs
  MIPS: JZ4740: require & include DT
  MIPS: irq_cpu: declare irqchip table entry
  MIPS: JZ4740: probe CPU interrupt controller via DT
  MIPS: JZ4740: use generic plat_irq_dispatch
  MIPS: JZ4740: move arch_init_irq out of arch/mips/jz4740/irq.c
  devicetree: document Ingenic SoC interrupt controller binding
  MIPS: JZ4740: probe interrupt controller via DT
  MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT
  MIPS: JZ4740: register an irq_domain for the interrupt controller
  MIPS: JZ4740: drop intc debugfs code
  MIPS: JZ4740: remove jz_intc_base global
  MIPS: JZ4740: support >32 interrupts
  MIPS: JZ4740: define IRQ numbers based on number of intc IRQs
  MIPS: JZ4740: read intc base address from DT
  MIPS: JZ4740: avoid JZ4740-specific naming
  MIPS: JZ4740: support newer SoC interrupt controllers
  irqchip: move Ingenic SoC intc driver to drivers/irqchip
  MIPS: JZ4740: call jz4740_clock_init earlier
  MIPS: JZ4740: replace use of jz4740_clock_bdata
  devicetree: add Ingenic CGU binding documentation
  clk: ingenic: add driver for Ingenic SoC CGU clocks
  MIPS,clk: migrate JZ4740 to common clock framework
  MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu
  MIPS,clk: move jz4740 UDC auto suspend functions to jz4740-cgu
  MIPS,clk: move jz4740 clock suspend,resume functions to jz4740-cgu
  clk: ingenic: add JZ4780 CGU support
  MIPS: JZ4740: remove clock.h
  MIPS: JZ4740: only detect RAM size if not specified in DT
  devicetree: document Ingenic SoC UART binding
  serial: 8250_ingenic: support for Ingenic SoC UARTs
  MIPS: JZ4740: use Ingenic SoC UART driver
  MIPS: ingenic: initial JZ4780 support
  MIPS: ingenic: initial MIPS Creator CI20 support

 .../devicetree/bindings/clock/ingenic,cgu.txt      |  53 ++
 .../bindings/interrupt-controller/ingenic,intc.txt |  25 +
 .../devicetree/bindings/serial/ingenic,uart.txt    |  22 +
 .../devicetree/bindings/vendor-prefixes.txt        |   2 +
 arch/mips/Kconfig                                  |  11 +-
 arch/mips/boot/dts/Makefile                        |   1 +
 arch/mips/boot/dts/ingenic/Makefile                |  10 +
 arch/mips/boot/dts/ingenic/ci20.dts                |  21 +
 arch/mips/boot/dts/ingenic/jz4740.dtsi             |  68 ++
 arch/mips/boot/dts/ingenic/jz4780.dtsi             | 101 +++
 arch/mips/boot/dts/ingenic/qi_lb60.dts             |  15 +
 arch/mips/configs/ci20_defconfig                   | 169 ++++
 arch/mips/configs/qi_lb60_defconfig                |   3 +-
 arch/mips/include/asm/cpu-type.h                   |   2 +-
 arch/mips/include/asm/cpu.h                        |   6 +-
 arch/mips/include/asm/mach-jz4740/clock.h          |   3 +
 .../asm/mach-jz4740/cpu-feature-overrides.h        |   3 -
 arch/mips/include/asm/mach-jz4740/irq.h            |  14 +-
 arch/mips/include/asm/mach-jz4740/platform.h       |   2 -
 arch/mips/jz4740/Kconfig                           |  17 +-
 arch/mips/jz4740/Makefile                          |   8 +-
 arch/mips/jz4740/Platform                          |   8 +-
 arch/mips/jz4740/board-qi_lb60.c                   |   7 -
 arch/mips/jz4740/clock-debugfs.c                   | 108 ---
 arch/mips/jz4740/clock.c                           | 924 ---------------------
 arch/mips/jz4740/clock.h                           |  76 --
 arch/mips/jz4740/gpio.c                            |   7 +-
 arch/mips/jz4740/irq.c                             | 162 ----
 arch/mips/jz4740/platform.c                        |  38 +-
 arch/mips/jz4740/pm.c                              |   2 -
 arch/mips/jz4740/prom.c                            |  13 -
 arch/mips/jz4740/reset.c                           |  13 +-
 arch/mips/jz4740/serial.c                          |  33 -
 arch/mips/jz4740/serial.h                          |  23 -
 arch/mips/jz4740/setup.c                           |  36 +-
 arch/mips/jz4740/time.c                            |  19 +-
 arch/mips/kernel/cpu-probe.c                       |   4 +-
 arch/mips/kernel/irq_cpu.c                         |   3 +
 drivers/clk/Makefile                               |   1 +
 drivers/clk/ingenic/Makefile                       |   3 +
 drivers/clk/ingenic/cgu.c                          | 711 ++++++++++++++++
 drivers/clk/ingenic/cgu.h                          | 223 +++++
 drivers/clk/ingenic/jz4740-cgu.c                   | 301 +++++++
 drivers/clk/ingenic/jz4780-cgu.c                   | 732 ++++++++++++++++
 drivers/irqchip/Kconfig                            |   5 +
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-ingenic.c                      | 171 ++++
 drivers/tty/serial/8250/8250_ingenic.c             | 261 ++++++
 drivers/tty/serial/8250/Kconfig                    |   9 +
 drivers/tty/serial/8250/Makefile                   |   3 +
 include/dt-bindings/clock/jz4740-cgu.h             |  37 +
 include/dt-bindings/clock/jz4780-cgu.h             |  88 ++
 .../irq.h => include/linux/irqchip/ingenic.h       |   8 +-
 53 files changed, 3162 insertions(+), 1424 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ingenic,cgu.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
 create mode 100644 Documentation/devicetree/bindings/serial/ingenic,uart.txt
 create mode 100644 arch/mips/boot/dts/ingenic/Makefile
 create mode 100644 arch/mips/boot/dts/ingenic/ci20.dts
 create mode 100644 arch/mips/boot/dts/ingenic/jz4740.dtsi
 create mode 100644 arch/mips/boot/dts/ingenic/jz4780.dtsi
 create mode 100644 arch/mips/boot/dts/ingenic/qi_lb60.dts
 create mode 100644 arch/mips/configs/ci20_defconfig
 delete mode 100644 arch/mips/jz4740/clock-debugfs.c
 delete mode 100644 arch/mips/jz4740/clock.c
 delete mode 100644 arch/mips/jz4740/clock.h
 delete mode 100644 arch/mips/jz4740/irq.c
 delete mode 100644 arch/mips/jz4740/serial.c
 delete mode 100644 arch/mips/jz4740/serial.h
 create mode 100644 drivers/clk/ingenic/Makefile
 create mode 100644 drivers/clk/ingenic/cgu.c
 create mode 100644 drivers/clk/ingenic/cgu.h
 create mode 100644 drivers/clk/ingenic/jz4740-cgu.c
 create mode 100644 drivers/clk/ingenic/jz4780-cgu.c
 create mode 100644 drivers/irqchip/irq-ingenic.c
 create mode 100644 drivers/tty/serial/8250/8250_ingenic.c
 create mode 100644 include/dt-bindings/clock/jz4740-cgu.h
 create mode 100644 include/dt-bindings/clock/jz4780-cgu.h
 rename arch/mips/jz4740/irq.h => include/linux/irqchip/ingenic.h (74%)

-- 
2.3.5

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[PATCH v3 01/37] devicetree/bindings: add Ingenic Semiconductor vendor prefix

[Paul Burton]

Define a vendor prefix for Ingenic Semiconductor, a vendor of MIPS-based
SoCs. Simply use 'ingenic'.

Signed-off-by: Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
Cc: Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
Changes in v3:
  - Rebase.

Changes in v2:
  - None.
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index c0e55db..721b14e 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -100,6 +100,7 @@ ibm	International Business Machines (IBM)
 idt	Integrated Device Technologies, Inc.
 iom	Iomega Corporation
 img	Imagination Technologies Ltd.
+ingenic	Ingenic Semiconductor
 innolux	Innolux Corporation
 intel	Intel Corporation
 intercontrol	Inter Control Group
-- 
2.3.5

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[PATCH v3 02/37] devicetree/bindings: add Qi Hardware vendor prefix

[Paul Burton]

Define a vendor prefix for Qi Hardware, creators of the Ben Nanonote
(qi_lb60) among other open devices.

Signed-off-by: Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
Cc: Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
Changes in v3:
  - New patch.
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 721b14e..5aa0bd8 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -155,6 +155,7 @@ powervr	PowerVR (deprecated, use img)
 qca	Qualcomm Atheros, Inc.
 qcom	Qualcomm Technologies, Inc
 qemu	QEMU, a generic and open source machine emulator and virtualizer
+qi	Qi Hardware
 qnap	QNAP Systems, Inc.
 radxa	Radxa
 raidsonic	RaidSonic Technology GmbH
-- 
2.3.5

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[PATCH v3 10/37] devicetree: document Ingenic SoC interrupt controller binding

[Paul Burton]

Add binding documentation for Ingenic SoC interrupt controllers.

Signed-off-by: Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
Cc: Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
Changes in v3:
  - Merge documentation for various Ingenic SoCs, which only differ by
    their compatible strings.

Changes in v2:
  - None.
---
 .../bindings/interrupt-controller/ingenic,intc.txt | 25 ++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt

diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
new file mode 100644
index 0000000..5d652e4
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
@@ -0,0 +1,25 @@
+Ingenic SoC Interrupt Controller
+
+Required properties:
+
+- compatible : should be "ingenic,<socname>-intc". For example
+  "ingenic,jz4740-intc" or "ingenic,jz4780-intc".
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+- interrupt-parent : phandle of the CPU interrupt controller.
+- interrupts : Specifies the CPU interrupt the controller is connected to.
+
+Example:
+
+intc: intc@10001000 {
+	compatible = "ingenic,jz4740-intc";
+	reg = <0x10001000 0x14>;
+
+	interrupt-controller;
+	#interrupt-cells = <1>;
+
+	interrupt-parent = <&cpuintc>;
+	interrupts = <2>;
+};
-- 
2.3.5

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[PATCH v3 24/37] devicetree: add Ingenic CGU binding documentation

[Paul Burton]

Document the devicetree binding for Ingenic SoC CGUs, and add headers
defining the clock specifiers for clocks provided by the JZ4740 & JZ4780
CGU blocks.

Signed-off-by: Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
Cc: Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>
Cc: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
Changes in v3:
  - Merge binding documentation for various Ingenic SoCs which differ only
    by compatible strings.

Changes in v2:
  - None.
---
 .../devicetree/bindings/clock/ingenic,cgu.txt      | 53 +++++++++++++
 include/dt-bindings/clock/jz4740-cgu.h             | 37 +++++++++
 include/dt-bindings/clock/jz4780-cgu.h             | 88 ++++++++++++++++++++++
 3 files changed, 178 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/ingenic,cgu.txt
 create mode 100644 include/dt-bindings/clock/jz4740-cgu.h
 create mode 100644 include/dt-bindings/clock/jz4780-cgu.h

diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
new file mode 100644
index 0000000..7421f8c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
@@ -0,0 +1,53 @@
+Ingenic SoC CGU binding
+
+The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
+typically includes a variety of PLLs, multiplexers, dividers & gates in order
+to provide many different clock signals derived from only 2 external source
+clocks.
+
+Required properties:
+- compatible : Should be "ingenic,<soctype>-cgu".
+  For example "ingenic,jz4740-cgu" or "ingenic,jz4780-cgu".
+- reg : The address & length of the CGU registers.
+- clocks : List of phandle & clock specifiers for clocks external to the TCU.
+  Two such external clocks should be specified - first the external crystal
+  "ext" and second the RTC clock source "rtc".
+- clock-names : List of name strings for the external clocks.
+- #clock-cells: Should be 1.
+  Clock consumers specify this argument to identify a clock. The valid values
+  may be found in <dt-bindings/clock/<soctype>-cgu.h>.
+
+Example SoC include file:
+
+/ {
+	cgu: jz4740-cgu {
+		compatible = "ingenic,jz4740-cgu";
+		reg = <0x10000000 0x100>;
+		#clock-cells = <1>;
+	};
+
+	uart0: serial@10030000 {
+		clocks = <&cgu JZ4740_CLK_UART0>;
+	};
+};
+
+Example board file:
+
+/ {
+	ext: clock@0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <12000000>;
+	};
+
+	rtc: clock@1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+	};
+
+	&cgu {
+		clocks = <&ext> <&rtc>;
+		clock-names: "ext", "rtc";
+	};
+};
diff --git a/include/dt-bindings/clock/jz4740-cgu.h b/include/dt-bindings/clock/jz4740-cgu.h
new file mode 100644
index 0000000..43153d3
--- /dev/null
+++ b/include/dt-bindings/clock/jz4740-cgu.h
@@ -0,0 +1,37 @@
+/*
+ * This header provides clock numbers for the ingenic,jz4740-cgu DT binding.
+ *
+ * They are roughly ordered as:
+ *   - external clocks
+ *   - PLLs
+ *   - muxes/dividers in the order they appear in the jz4740 programmers manual
+ *   - gates in order of their bit in the CLKGR* registers
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__
+#define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__
+
+#define JZ4740_CLK_EXT		0
+#define JZ4740_CLK_RTC		1
+#define JZ4740_CLK_PLL		2
+#define JZ4740_CLK_PLL_HALF	3
+#define JZ4740_CLK_CCLK		4
+#define JZ4740_CLK_HCLK		5
+#define JZ4740_CLK_PCLK		6
+#define JZ4740_CLK_MCLK		7
+#define JZ4740_CLK_LCD		8
+#define JZ4740_CLK_LCD_PCLK	9
+#define JZ4740_CLK_I2S		10
+#define JZ4740_CLK_SPI		11
+#define JZ4740_CLK_MMC		12
+#define JZ4740_CLK_UHC		13
+#define JZ4740_CLK_UDC		14
+#define JZ4740_CLK_UART0	15
+#define JZ4740_CLK_UART1	16
+#define JZ4740_CLK_DMA		17
+#define JZ4740_CLK_IPU		18
+#define JZ4740_CLK_ADC		19
+#define JZ4740_CLK_I2C		20
+#define JZ4740_CLK_AIC		21
+
+#endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */
diff --git a/include/dt-bindings/clock/jz4780-cgu.h b/include/dt-bindings/clock/jz4780-cgu.h
new file mode 100644
index 0000000..467165e
--- /dev/null
+++ b/include/dt-bindings/clock/jz4780-cgu.h
@@ -0,0 +1,88 @@
+/*
+ * This header provides clock numbers for the ingenic,jz4780-cgu DT binding.
+ *
+ * They are roughly ordered as:
+ *   - external clocks
+ *   - PLLs
+ *   - muxes/dividers in the order they appear in the jz4780 programmers manual
+ *   - gates in order of their bit in the CLKGR* registers
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
+#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
+
+#define JZ4780_CLK_EXCLK	0
+#define JZ4780_CLK_RTCLK	1
+#define JZ4780_CLK_APLL		2
+#define JZ4780_CLK_MPLL		3
+#define JZ4780_CLK_EPLL		4
+#define JZ4780_CLK_VPLL		5
+#define JZ4780_CLK_OTGPHY	6
+#define JZ4780_CLK_SCLKA	7
+#define JZ4780_CLK_CPUMUX	8
+#define JZ4780_CLK_CPU		9
+#define JZ4780_CLK_L2CACHE	10
+#define JZ4780_CLK_AHB0		11
+#define JZ4780_CLK_AHB2PMUX	12
+#define JZ4780_CLK_AHB2		13
+#define JZ4780_CLK_PCLK		14
+#define JZ4780_CLK_DDR		15
+#define JZ4780_CLK_VPU		16
+#define JZ4780_CLK_I2SPLL	17
+#define JZ4780_CLK_I2S		18
+#define JZ4780_CLK_LCD0PIXCLK	19
+#define JZ4780_CLK_LCD1PIXCLK	20
+#define JZ4780_CLK_MSCMUX	21
+#define JZ4780_CLK_MSC0		22
+#define JZ4780_CLK_MSC1		23
+#define JZ4780_CLK_MSC2		24
+#define JZ4780_CLK_UHC		25
+#define JZ4780_CLK_SSIPLL	26
+#define JZ4780_CLK_SSI		27
+#define JZ4780_CLK_CIMMCLK	28
+#define JZ4780_CLK_PCMPLL	29
+#define JZ4780_CLK_PCM		30
+#define JZ4780_CLK_GPU		31
+#define JZ4780_CLK_HDMI		32
+#define JZ4780_CLK_BCH		33
+#define JZ4780_CLK_NEMC		34
+#define JZ4780_CLK_OTG0		35
+#define JZ4780_CLK_SSI0		36
+#define JZ4780_CLK_SMB0		37
+#define JZ4780_CLK_SMB1		38
+#define JZ4780_CLK_SCC		39
+#define JZ4780_CLK_AIC		40
+#define JZ4780_CLK_TSSI0	41
+#define JZ4780_CLK_OWI		42
+#define JZ4780_CLK_KBC		43
+#define JZ4780_CLK_SADC		44
+#define JZ4780_CLK_UART0	45
+#define JZ4780_CLK_UART1	46
+#define JZ4780_CLK_UART2	47
+#define JZ4780_CLK_UART3	48
+#define JZ4780_CLK_SSI1		49
+#define JZ4780_CLK_SSI2		50
+#define JZ4780_CLK_PDMA		51
+#define JZ4780_CLK_GPS		52
+#define JZ4780_CLK_MAC		53
+#define JZ4780_CLK_SMB2		54
+#define JZ4780_CLK_CIM		55
+#define JZ4780_CLK_LCD		56
+#define JZ4780_CLK_TVE		57
+#define JZ4780_CLK_IPU		58
+#define JZ4780_CLK_DDR0		59
+#define JZ4780_CLK_DDR1		60
+#define JZ4780_CLK_SMB3		61
+#define JZ4780_CLK_TSSI1	62
+#define JZ4780_CLK_COMPRESS	63
+#define JZ4780_CLK_AIC1		64
+#define JZ4780_CLK_GPVLC	65
+#define JZ4780_CLK_OTG1		66
+#define JZ4780_CLK_UART4	67
+#define JZ4780_CLK_AHBMON	68
+#define JZ4780_CLK_SMB4		69
+#define JZ4780_CLK_DES		70
+#define JZ4780_CLK_X2D		71
+#define JZ4780_CLK_CORE1	72
+
+#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */
-- 
2.3.5

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[PATCH v3 33/37] devicetree: document Ingenic SoC UART binding

[Paul Burton]

Add binding documentation for the UARTs found in Ingenic SoCs.

Signed-off-by: Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
Cc: Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
Changes in v3:
  - Merge binding documentation for Ingenic SoCs whose bindings differ
    only by their compatible strings.

Changes in v2:
  - None.
---
 .../devicetree/bindings/serial/ingenic,uart.txt    | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/serial/ingenic,uart.txt

diff --git a/Documentation/devicetree/bindings/serial/ingenic,uart.txt b/Documentation/devicetree/bindings/serial/ingenic,uart.txt
new file mode 100644
index 0000000..c2d3b3a
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/ingenic,uart.txt
@@ -0,0 +1,22 @@
+* Ingenic SoC UART
+
+Required properties:
+- compatible : "ingenic,jz4740-uart" or "ingenic,jz4780-uart"
+- reg : offset and length of the register set for the device.
+- interrupts : should contain uart interrupt.
+- clocks : phandles to the module & baud clocks.
+- clock-names: tuple listing input clock names.
+	Required elements: "baud", "module"
+
+Example:
+
+uart0: serial@10030000 {
+	compatible = "ingenic,jz4740-uart";
+	reg = <0x10030000 0x100>;
+
+	interrupt-parent = <&intc>;
+	interrupts = <9>;
+
+	clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
+	clock-names = "baud", "module";
+};
-- 
2.3.5

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Re: [PATCH v3 00/37] JZ4780 & CI20 support

[Paul Burton]

On Tue, Apr 21, 2015 at 03:46:27PM +0100, Paul Burton wrote:
> This series introduces initial support for the Ingenic JZ4780 SoC and
> the Imagination Technologies MIPS Creator CI20 board which is built
> around it. In the process the existing JZ4740 & qi_lb60 code gains
> initial support for using DeviceTree such that much of the existing
> platform code under arch/mips/jz4740 can be shared.
> 
> The series has undergone quite a bit of restructure since v2. Each
> patch contains a changelog indicating its differences, but a rough
> overview for changes across the series would be:
> 
>   - s/jz47xx/ingenic/ in various places, to reflect the fact that
>     Ingenic have changed the naming scheme for their newest SoCs
>     (now Mxxx).
> 
>   - Restructure the Kconfig entries to provide a MACH_INGENIC
>     indicating and Ingenic SoC, and have boards select the
>     appropriate SoC symbol.
> 
>   - Merge DT binding documentation where SoC bindings differ only
>     by compatible strings.
> 
>   - Capitalise "JZ" in SoC names, where not identifiers in code,
>     to match the way Ingenic write them.
> 
>   - Further clean up the Ingenic SoC interrupt controller driver
>     and move it under drivers/irqchip/.
> 
> Review appreciated, and hopefully this can make it into v4.2.

(Of course I forgot something... This applies atop next-20150421 :) )

Thanks,
    Paul

> Thanks,
>     Paul
> 
> Paul Burton (37):
>   devicetree/bindings: add Ingenic Semiconductor vendor prefix
>   devicetree/bindings: add Qi Hardware vendor prefix
>   MIPS: JZ4740: introduce CONFIG_MACH_INGENIC
>   MIPS: ingenic: add newer vendor IDs
>   MIPS: JZ4740: require & include DT
>   MIPS: irq_cpu: declare irqchip table entry
>   MIPS: JZ4740: probe CPU interrupt controller via DT
>   MIPS: JZ4740: use generic plat_irq_dispatch
>   MIPS: JZ4740: move arch_init_irq out of arch/mips/jz4740/irq.c
>   devicetree: document Ingenic SoC interrupt controller binding
>   MIPS: JZ4740: probe interrupt controller via DT
>   MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT
>   MIPS: JZ4740: register an irq_domain for the interrupt controller
>   MIPS: JZ4740: drop intc debugfs code
>   MIPS: JZ4740: remove jz_intc_base global
>   MIPS: JZ4740: support >32 interrupts
>   MIPS: JZ4740: define IRQ numbers based on number of intc IRQs
>   MIPS: JZ4740: read intc base address from DT
>   MIPS: JZ4740: avoid JZ4740-specific naming
>   MIPS: JZ4740: support newer SoC interrupt controllers
>   irqchip: move Ingenic SoC intc driver to drivers/irqchip
>   MIPS: JZ4740: call jz4740_clock_init earlier
>   MIPS: JZ4740: replace use of jz4740_clock_bdata
>   devicetree: add Ingenic CGU binding documentation
>   clk: ingenic: add driver for Ingenic SoC CGU clocks
>   MIPS,clk: migrate JZ4740 to common clock framework
>   MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu
>   MIPS,clk: move jz4740 UDC auto suspend functions to jz4740-cgu
>   MIPS,clk: move jz4740 clock suspend,resume functions to jz4740-cgu
>   clk: ingenic: add JZ4780 CGU support
>   MIPS: JZ4740: remove clock.h
>   MIPS: JZ4740: only detect RAM size if not specified in DT
>   devicetree: document Ingenic SoC UART binding
>   serial: 8250_ingenic: support for Ingenic SoC UARTs
>   MIPS: JZ4740: use Ingenic SoC UART driver
>   MIPS: ingenic: initial JZ4780 support
>   MIPS: ingenic: initial MIPS Creator CI20 support
> 
>  .../devicetree/bindings/clock/ingenic,cgu.txt      |  53 ++
>  .../bindings/interrupt-controller/ingenic,intc.txt |  25 +
>  .../devicetree/bindings/serial/ingenic,uart.txt    |  22 +
>  .../devicetree/bindings/vendor-prefixes.txt        |   2 +
>  arch/mips/Kconfig                                  |  11 +-
>  arch/mips/boot/dts/Makefile                        |   1 +
>  arch/mips/boot/dts/ingenic/Makefile                |  10 +
>  arch/mips/boot/dts/ingenic/ci20.dts                |  21 +
>  arch/mips/boot/dts/ingenic/jz4740.dtsi             |  68 ++
>  arch/mips/boot/dts/ingenic/jz4780.dtsi             | 101 +++
>  arch/mips/boot/dts/ingenic/qi_lb60.dts             |  15 +
>  arch/mips/configs/ci20_defconfig                   | 169 ++++
>  arch/mips/configs/qi_lb60_defconfig                |   3 +-
>  arch/mips/include/asm/cpu-type.h                   |   2 +-
>  arch/mips/include/asm/cpu.h                        |   6 +-
>  arch/mips/include/asm/mach-jz4740/clock.h          |   3 +
>  .../asm/mach-jz4740/cpu-feature-overrides.h        |   3 -
>  arch/mips/include/asm/mach-jz4740/irq.h            |  14 +-
>  arch/mips/include/asm/mach-jz4740/platform.h       |   2 -
>  arch/mips/jz4740/Kconfig                           |  17 +-
>  arch/mips/jz4740/Makefile                          |   8 +-
>  arch/mips/jz4740/Platform                          |   8 +-
>  arch/mips/jz4740/board-qi_lb60.c                   |   7 -
>  arch/mips/jz4740/clock-debugfs.c                   | 108 ---
>  arch/mips/jz4740/clock.c                           | 924 ---------------------
>  arch/mips/jz4740/clock.h                           |  76 --
>  arch/mips/jz4740/gpio.c                            |   7 +-
>  arch/mips/jz4740/irq.c                             | 162 ----
>  arch/mips/jz4740/platform.c                        |  38 +-
>  arch/mips/jz4740/pm.c                              |   2 -
>  arch/mips/jz4740/prom.c                            |  13 -
>  arch/mips/jz4740/reset.c                           |  13 +-
>  arch/mips/jz4740/serial.c                          |  33 -
>  arch/mips/jz4740/serial.h                          |  23 -
>  arch/mips/jz4740/setup.c                           |  36 +-
>  arch/mips/jz4740/time.c                            |  19 +-
>  arch/mips/kernel/cpu-probe.c                       |   4 +-
>  arch/mips/kernel/irq_cpu.c                         |   3 +
>  drivers/clk/Makefile                               |   1 +
>  drivers/clk/ingenic/Makefile                       |   3 +
>  drivers/clk/ingenic/cgu.c                          | 711 ++++++++++++++++
>  drivers/clk/ingenic/cgu.h                          | 223 +++++
>  drivers/clk/ingenic/jz4740-cgu.c                   | 301 +++++++
>  drivers/clk/ingenic/jz4780-cgu.c                   | 732 ++++++++++++++++
>  drivers/irqchip/Kconfig                            |   5 +
>  drivers/irqchip/Makefile                           |   1 +
>  drivers/irqchip/irq-ingenic.c                      | 171 ++++
>  drivers/tty/serial/8250/8250_ingenic.c             | 261 ++++++
>  drivers/tty/serial/8250/Kconfig                    |   9 +
>  drivers/tty/serial/8250/Makefile                   |   3 +
>  include/dt-bindings/clock/jz4740-cgu.h             |  37 +
>  include/dt-bindings/clock/jz4780-cgu.h             |  88 ++
>  .../irq.h => include/linux/irqchip/ingenic.h       |   8 +-
>  53 files changed, 3162 insertions(+), 1424 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/ingenic,cgu.txt
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
>  create mode 100644 Documentation/devicetree/bindings/serial/ingenic,uart.txt
>  create mode 100644 arch/mips/boot/dts/ingenic/Makefile
>  create mode 100644 arch/mips/boot/dts/ingenic/ci20.dts
>  create mode 100644 arch/mips/boot/dts/ingenic/jz4740.dtsi
>  create mode 100644 arch/mips/boot/dts/ingenic/jz4780.dtsi
>  create mode 100644 arch/mips/boot/dts/ingenic/qi_lb60.dts
>  create mode 100644 arch/mips/configs/ci20_defconfig
>  delete mode 100644 arch/mips/jz4740/clock-debugfs.c
>  delete mode 100644 arch/mips/jz4740/clock.c
>  delete mode 100644 arch/mips/jz4740/clock.h
>  delete mode 100644 arch/mips/jz4740/irq.c
>  delete mode 100644 arch/mips/jz4740/serial.c
>  delete mode 100644 arch/mips/jz4740/serial.h
>  create mode 100644 drivers/clk/ingenic/Makefile
>  create mode 100644 drivers/clk/ingenic/cgu.c
>  create mode 100644 drivers/clk/ingenic/cgu.h
>  create mode 100644 drivers/clk/ingenic/jz4740-cgu.c
>  create mode 100644 drivers/clk/ingenic/jz4780-cgu.c
>  create mode 100644 drivers/irqchip/irq-ingenic.c
>  create mode 100644 drivers/tty/serial/8250/8250_ingenic.c
>  create mode 100644 include/dt-bindings/clock/jz4740-cgu.h
>  create mode 100644 include/dt-bindings/clock/jz4780-cgu.h
>  rename arch/mips/jz4740/irq.h => include/linux/irqchip/ingenic.h (74%)
> 
> -- 
> 2.3.5
> 
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Re: [PATCH v3 10/37] devicetree: document Ingenic SoC interrupt controller binding

[Sergei Shtylyov]

Hello.

On 04/21/2015 05:46 PM, Paul Burton wrote:

> Add binding documentation for Ingenic SoC interrupt controllers.

> Signed-off-by: Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
> Cc: Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
> Changes in v3:
>    - Merge documentation for various Ingenic SoCs, which only differ by
>      their compatible strings.

> Changes in v2:
>    - None.
> ---
>   .../bindings/interrupt-controller/ingenic,intc.txt | 25 ++++++++++++++++++++++
>   1 file changed, 25 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt

> diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
> new file mode 100644
> index 0000000..5d652e4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
> @@ -0,0 +1,25 @@
> +Ingenic SoC Interrupt Controller
> +
> +Required properties:
> +
> +- compatible : should be "ingenic,<socname>-intc". For example
> +  "ingenic,jz4740-intc" or "ingenic,jz4780-intc".
> +- reg : Specifies base physical address and size of the registers.
> +- interrupt-controller : Identifies the node as an interrupt controller
> +- #interrupt-cells : Specifies the number of cells needed to encode an
> +  interrupt source. The value shall be 1.
> +- interrupt-parent : phandle of the CPU interrupt controller.
> +- interrupts : Specifies the CPU interrupt the controller is connected to.
> +
> +Example:
> +
> +intc: intc@10001000 {

    The node should be named "interrupt-controller@10001000", according to the 
epAPR standard.

WBR, Sergei

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Re: [PATCH v3 24/37] devicetree: add Ingenic CGU binding documentation

[James Hogan]

[-- Attachment #1: Type: text/plain, Size: 7581 bytes --]

On Tue, Apr 21, 2015 at 03:46:51PM +0100, Paul Burton wrote:
> Document the devicetree binding for Ingenic SoC CGUs, and add headers
> defining the clock specifiers for clocks provided by the JZ4740 & JZ4780
> CGU blocks.
> 
> Signed-off-by: Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
> Cc: Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>
> Cc: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
> Changes in v3:
>   - Merge binding documentation for various Ingenic SoCs which differ only
>     by compatible strings.
> 
> Changes in v2:
>   - None.
> ---
>  .../devicetree/bindings/clock/ingenic,cgu.txt      | 53 +++++++++++++
>  include/dt-bindings/clock/jz4740-cgu.h             | 37 +++++++++
>  include/dt-bindings/clock/jz4780-cgu.h             | 88 ++++++++++++++++++++++
>  3 files changed, 178 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/ingenic,cgu.txt
>  create mode 100644 include/dt-bindings/clock/jz4740-cgu.h
>  create mode 100644 include/dt-bindings/clock/jz4780-cgu.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
> new file mode 100644
> index 0000000..7421f8c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
> @@ -0,0 +1,53 @@
> +Ingenic SoC CGU binding
> +
> +The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
> +typically includes a variety of PLLs, multiplexers, dividers & gates in order
> +to provide many different clock signals derived from only 2 external source
> +clocks.
> +
> +Required properties:
> +- compatible : Should be "ingenic,<soctype>-cgu".
> +  For example "ingenic,jz4740-cgu" or "ingenic,jz4780-cgu".
> +- reg : The address & length of the CGU registers.
> +- clocks : List of phandle & clock specifiers for clocks external to the TCU.

Suspect TCU is a typo for CGU.

Cheers
James

> +  Two such external clocks should be specified - first the external crystal
> +  "ext" and second the RTC clock source "rtc".
> +- clock-names : List of name strings for the external clocks.
> +- #clock-cells: Should be 1.
> +  Clock consumers specify this argument to identify a clock. The valid values
> +  may be found in <dt-bindings/clock/<soctype>-cgu.h>.
> +
> +Example SoC include file:
> +
> +/ {
> +	cgu: jz4740-cgu {
> +		compatible = "ingenic,jz4740-cgu";
> +		reg = <0x10000000 0x100>;
> +		#clock-cells = <1>;
> +	};
> +
> +	uart0: serial@10030000 {
> +		clocks = <&cgu JZ4740_CLK_UART0>;
> +	};
> +};
> +
> +Example board file:
> +
> +/ {
> +	ext: clock@0 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <12000000>;
> +	};
> +
> +	rtc: clock@1 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <32768>;
> +	};
> +
> +	&cgu {
> +		clocks = <&ext> <&rtc>;
> +		clock-names: "ext", "rtc";
> +	};
> +};
> diff --git a/include/dt-bindings/clock/jz4740-cgu.h b/include/dt-bindings/clock/jz4740-cgu.h
> new file mode 100644
> index 0000000..43153d3
> --- /dev/null
> +++ b/include/dt-bindings/clock/jz4740-cgu.h
> @@ -0,0 +1,37 @@
> +/*
> + * This header provides clock numbers for the ingenic,jz4740-cgu DT binding.
> + *
> + * They are roughly ordered as:
> + *   - external clocks
> + *   - PLLs
> + *   - muxes/dividers in the order they appear in the jz4740 programmers manual
> + *   - gates in order of their bit in the CLKGR* registers
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__
> +#define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__
> +
> +#define JZ4740_CLK_EXT		0
> +#define JZ4740_CLK_RTC		1
> +#define JZ4740_CLK_PLL		2
> +#define JZ4740_CLK_PLL_HALF	3
> +#define JZ4740_CLK_CCLK		4
> +#define JZ4740_CLK_HCLK		5
> +#define JZ4740_CLK_PCLK		6
> +#define JZ4740_CLK_MCLK		7
> +#define JZ4740_CLK_LCD		8
> +#define JZ4740_CLK_LCD_PCLK	9
> +#define JZ4740_CLK_I2S		10
> +#define JZ4740_CLK_SPI		11
> +#define JZ4740_CLK_MMC		12
> +#define JZ4740_CLK_UHC		13
> +#define JZ4740_CLK_UDC		14
> +#define JZ4740_CLK_UART0	15
> +#define JZ4740_CLK_UART1	16
> +#define JZ4740_CLK_DMA		17
> +#define JZ4740_CLK_IPU		18
> +#define JZ4740_CLK_ADC		19
> +#define JZ4740_CLK_I2C		20
> +#define JZ4740_CLK_AIC		21
> +
> +#endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */
> diff --git a/include/dt-bindings/clock/jz4780-cgu.h b/include/dt-bindings/clock/jz4780-cgu.h
> new file mode 100644
> index 0000000..467165e
> --- /dev/null
> +++ b/include/dt-bindings/clock/jz4780-cgu.h
> @@ -0,0 +1,88 @@
> +/*
> + * This header provides clock numbers for the ingenic,jz4780-cgu DT binding.
> + *
> + * They are roughly ordered as:
> + *   - external clocks
> + *   - PLLs
> + *   - muxes/dividers in the order they appear in the jz4780 programmers manual
> + *   - gates in order of their bit in the CLKGR* registers
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
> +#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
> +
> +#define JZ4780_CLK_EXCLK	0
> +#define JZ4780_CLK_RTCLK	1
> +#define JZ4780_CLK_APLL		2
> +#define JZ4780_CLK_MPLL		3
> +#define JZ4780_CLK_EPLL		4
> +#define JZ4780_CLK_VPLL		5
> +#define JZ4780_CLK_OTGPHY	6
> +#define JZ4780_CLK_SCLKA	7
> +#define JZ4780_CLK_CPUMUX	8
> +#define JZ4780_CLK_CPU		9
> +#define JZ4780_CLK_L2CACHE	10
> +#define JZ4780_CLK_AHB0		11
> +#define JZ4780_CLK_AHB2PMUX	12
> +#define JZ4780_CLK_AHB2		13
> +#define JZ4780_CLK_PCLK		14
> +#define JZ4780_CLK_DDR		15
> +#define JZ4780_CLK_VPU		16
> +#define JZ4780_CLK_I2SPLL	17
> +#define JZ4780_CLK_I2S		18
> +#define JZ4780_CLK_LCD0PIXCLK	19
> +#define JZ4780_CLK_LCD1PIXCLK	20
> +#define JZ4780_CLK_MSCMUX	21
> +#define JZ4780_CLK_MSC0		22
> +#define JZ4780_CLK_MSC1		23
> +#define JZ4780_CLK_MSC2		24
> +#define JZ4780_CLK_UHC		25
> +#define JZ4780_CLK_SSIPLL	26
> +#define JZ4780_CLK_SSI		27
> +#define JZ4780_CLK_CIMMCLK	28
> +#define JZ4780_CLK_PCMPLL	29
> +#define JZ4780_CLK_PCM		30
> +#define JZ4780_CLK_GPU		31
> +#define JZ4780_CLK_HDMI		32
> +#define JZ4780_CLK_BCH		33
> +#define JZ4780_CLK_NEMC		34
> +#define JZ4780_CLK_OTG0		35
> +#define JZ4780_CLK_SSI0		36
> +#define JZ4780_CLK_SMB0		37
> +#define JZ4780_CLK_SMB1		38
> +#define JZ4780_CLK_SCC		39
> +#define JZ4780_CLK_AIC		40
> +#define JZ4780_CLK_TSSI0	41
> +#define JZ4780_CLK_OWI		42
> +#define JZ4780_CLK_KBC		43
> +#define JZ4780_CLK_SADC		44
> +#define JZ4780_CLK_UART0	45
> +#define JZ4780_CLK_UART1	46
> +#define JZ4780_CLK_UART2	47
> +#define JZ4780_CLK_UART3	48
> +#define JZ4780_CLK_SSI1		49
> +#define JZ4780_CLK_SSI2		50
> +#define JZ4780_CLK_PDMA		51
> +#define JZ4780_CLK_GPS		52
> +#define JZ4780_CLK_MAC		53
> +#define JZ4780_CLK_SMB2		54
> +#define JZ4780_CLK_CIM		55
> +#define JZ4780_CLK_LCD		56
> +#define JZ4780_CLK_TVE		57
> +#define JZ4780_CLK_IPU		58
> +#define JZ4780_CLK_DDR0		59
> +#define JZ4780_CLK_DDR1		60
> +#define JZ4780_CLK_SMB3		61
> +#define JZ4780_CLK_TSSI1	62
> +#define JZ4780_CLK_COMPRESS	63
> +#define JZ4780_CLK_AIC1		64
> +#define JZ4780_CLK_GPVLC	65
> +#define JZ4780_CLK_OTG1		66
> +#define JZ4780_CLK_UART4	67
> +#define JZ4780_CLK_AHBMON	68
> +#define JZ4780_CLK_SMB4		69
> +#define JZ4780_CLK_DES		70
> +#define JZ4780_CLK_X2D		71
> +#define JZ4780_CLK_CORE1	72
> +
> +#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */
> -- 
> 2.3.5
> 
> 

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Re: [PATCH v3 00/37] JZ4780 & CI20 support

[Rob Herring]

On Tue, Apr 21, 2015 at 9:46 AM, Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org> wrote:
> This series introduces initial support for the Ingenic JZ4780 SoC and
> the Imagination Technologies MIPS Creator CI20 board which is built
> around it. In the process the existing JZ4740 & qi_lb60 code gains
> initial support for using DeviceTree such that much of the existing
> platform code under arch/mips/jz4740 can be shared.
>
> The series has undergone quite a bit of restructure since v2. Each
> patch contains a changelog indicating its differences, but a rough
> overview for changes across the series would be:
>
>   - s/jz47xx/ingenic/ in various places, to reflect the fact that
>     Ingenic have changed the naming scheme for their newest SoCs
>     (now Mxxx).
>
>   - Restructure the Kconfig entries to provide a MACH_INGENIC
>     indicating and Ingenic SoC, and have boards select the
>     appropriate SoC symbol.
>
>   - Merge DT binding documentation where SoC bindings differ only
>     by compatible strings.
>
>   - Capitalise "JZ" in SoC names, where not identifiers in code,
>     to match the way Ingenic write them.
>
>   - Further clean up the Ingenic SoC interrupt controller driver
>     and move it under drivers/irqchip/.
>
> Review appreciated, and hopefully this can make it into v4.2.
>
> Thanks,
>     Paul
>
> Paul Burton (37):
>   devicetree/bindings: add Ingenic Semiconductor vendor prefix
>   devicetree/bindings: add Qi Hardware vendor prefix
>   MIPS: JZ4740: introduce CONFIG_MACH_INGENIC
>   MIPS: ingenic: add newer vendor IDs
>   MIPS: JZ4740: require & include DT
>   MIPS: irq_cpu: declare irqchip table entry
>   MIPS: JZ4740: probe CPU interrupt controller via DT
>   MIPS: JZ4740: use generic plat_irq_dispatch
>   MIPS: JZ4740: move arch_init_irq out of arch/mips/jz4740/irq.c
>   devicetree: document Ingenic SoC interrupt controller binding

For patches 1, 2, and 10:

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

>   MIPS: JZ4740: probe interrupt controller via DT
>   MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT
>   MIPS: JZ4740: register an irq_domain for the interrupt controller
>   MIPS: JZ4740: drop intc debugfs code
>   MIPS: JZ4740: remove jz_intc_base global
>   MIPS: JZ4740: support >32 interrupts
>   MIPS: JZ4740: define IRQ numbers based on number of intc IRQs
>   MIPS: JZ4740: read intc base address from DT
>   MIPS: JZ4740: avoid JZ4740-specific naming
>   MIPS: JZ4740: support newer SoC interrupt controllers
>   irqchip: move Ingenic SoC intc driver to drivers/irqchip
>   MIPS: JZ4740: call jz4740_clock_init earlier
>   MIPS: JZ4740: replace use of jz4740_clock_bdata
>   devicetree: add Ingenic CGU binding documentation
>   clk: ingenic: add driver for Ingenic SoC CGU clocks
>   MIPS,clk: migrate JZ4740 to common clock framework
>   MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu
>   MIPS,clk: move jz4740 UDC auto suspend functions to jz4740-cgu
>   MIPS,clk: move jz4740 clock suspend,resume functions to jz4740-cgu
>   clk: ingenic: add JZ4780 CGU support
>   MIPS: JZ4740: remove clock.h
>   MIPS: JZ4740: only detect RAM size if not specified in DT
>   devicetree: document Ingenic SoC UART binding
>   serial: 8250_ingenic: support for Ingenic SoC UARTs
>   MIPS: JZ4740: use Ingenic SoC UART driver
>   MIPS: ingenic: initial JZ4780 support
>   MIPS: ingenic: initial MIPS Creator CI20 support
>
>  .../devicetree/bindings/clock/ingenic,cgu.txt      |  53 ++
>  .../bindings/interrupt-controller/ingenic,intc.txt |  25 +
>  .../devicetree/bindings/serial/ingenic,uart.txt    |  22 +
>  .../devicetree/bindings/vendor-prefixes.txt        |   2 +
>  arch/mips/Kconfig                                  |  11 +-
>  arch/mips/boot/dts/Makefile                        |   1 +
>  arch/mips/boot/dts/ingenic/Makefile                |  10 +
>  arch/mips/boot/dts/ingenic/ci20.dts                |  21 +
>  arch/mips/boot/dts/ingenic/jz4740.dtsi             |  68 ++
>  arch/mips/boot/dts/ingenic/jz4780.dtsi             | 101 +++
>  arch/mips/boot/dts/ingenic/qi_lb60.dts             |  15 +
>  arch/mips/configs/ci20_defconfig                   | 169 ++++
>  arch/mips/configs/qi_lb60_defconfig                |   3 +-
>  arch/mips/include/asm/cpu-type.h                   |   2 +-
>  arch/mips/include/asm/cpu.h                        |   6 +-
>  arch/mips/include/asm/mach-jz4740/clock.h          |   3 +
>  .../asm/mach-jz4740/cpu-feature-overrides.h        |   3 -
>  arch/mips/include/asm/mach-jz4740/irq.h            |  14 +-
>  arch/mips/include/asm/mach-jz4740/platform.h       |   2 -
>  arch/mips/jz4740/Kconfig                           |  17 +-
>  arch/mips/jz4740/Makefile                          |   8 +-
>  arch/mips/jz4740/Platform                          |   8 +-
>  arch/mips/jz4740/board-qi_lb60.c                   |   7 -
>  arch/mips/jz4740/clock-debugfs.c                   | 108 ---
>  arch/mips/jz4740/clock.c                           | 924 ---------------------
>  arch/mips/jz4740/clock.h                           |  76 --
>  arch/mips/jz4740/gpio.c                            |   7 +-
>  arch/mips/jz4740/irq.c                             | 162 ----
>  arch/mips/jz4740/platform.c                        |  38 +-
>  arch/mips/jz4740/pm.c                              |   2 -
>  arch/mips/jz4740/prom.c                            |  13 -
>  arch/mips/jz4740/reset.c                           |  13 +-
>  arch/mips/jz4740/serial.c                          |  33 -
>  arch/mips/jz4740/serial.h                          |  23 -
>  arch/mips/jz4740/setup.c                           |  36 +-
>  arch/mips/jz4740/time.c                            |  19 +-
>  arch/mips/kernel/cpu-probe.c                       |   4 +-
>  arch/mips/kernel/irq_cpu.c                         |   3 +
>  drivers/clk/Makefile                               |   1 +
>  drivers/clk/ingenic/Makefile                       |   3 +
>  drivers/clk/ingenic/cgu.c                          | 711 ++++++++++++++++
>  drivers/clk/ingenic/cgu.h                          | 223 +++++
>  drivers/clk/ingenic/jz4740-cgu.c                   | 301 +++++++
>  drivers/clk/ingenic/jz4780-cgu.c                   | 732 ++++++++++++++++
>  drivers/irqchip/Kconfig                            |   5 +
>  drivers/irqchip/Makefile                           |   1 +
>  drivers/irqchip/irq-ingenic.c                      | 171 ++++
>  drivers/tty/serial/8250/8250_ingenic.c             | 261 ++++++
>  drivers/tty/serial/8250/Kconfig                    |   9 +
>  drivers/tty/serial/8250/Makefile                   |   3 +
>  include/dt-bindings/clock/jz4740-cgu.h             |  37 +
>  include/dt-bindings/clock/jz4780-cgu.h             |  88 ++
>  .../irq.h => include/linux/irqchip/ingenic.h       |   8 +-
>  53 files changed, 3162 insertions(+), 1424 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/ingenic,cgu.txt
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
>  create mode 100644 Documentation/devicetree/bindings/serial/ingenic,uart.txt
>  create mode 100644 arch/mips/boot/dts/ingenic/Makefile
>  create mode 100644 arch/mips/boot/dts/ingenic/ci20.dts
>  create mode 100644 arch/mips/boot/dts/ingenic/jz4740.dtsi
>  create mode 100644 arch/mips/boot/dts/ingenic/jz4780.dtsi
>  create mode 100644 arch/mips/boot/dts/ingenic/qi_lb60.dts
>  create mode 100644 arch/mips/configs/ci20_defconfig
>  delete mode 100644 arch/mips/jz4740/clock-debugfs.c
>  delete mode 100644 arch/mips/jz4740/clock.c
>  delete mode 100644 arch/mips/jz4740/clock.h
>  delete mode 100644 arch/mips/jz4740/irq.c
>  delete mode 100644 arch/mips/jz4740/serial.c
>  delete mode 100644 arch/mips/jz4740/serial.h
>  create mode 100644 drivers/clk/ingenic/Makefile
>  create mode 100644 drivers/clk/ingenic/cgu.c
>  create mode 100644 drivers/clk/ingenic/cgu.h
>  create mode 100644 drivers/clk/ingenic/jz4740-cgu.c
>  create mode 100644 drivers/clk/ingenic/jz4780-cgu.c
>  create mode 100644 drivers/irqchip/irq-ingenic.c
>  create mode 100644 drivers/tty/serial/8250/8250_ingenic.c
>  create mode 100644 include/dt-bindings/clock/jz4740-cgu.h
>  create mode 100644 include/dt-bindings/clock/jz4780-cgu.h
>  rename arch/mips/jz4740/irq.h => include/linux/irqchip/ingenic.h (74%)
>
> --
> 2.3.5
>
> --
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Re: [PATCH v3 33/37] devicetree: document Ingenic SoC UART binding

[Rob Herring]

On Tue, Apr 21, 2015 at 9:47 AM, Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org> wrote:
> Add binding documentation for the UARTs found in Ingenic SoCs.
>
> Signed-off-by: Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
> Cc: Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org

And for this one too:

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

> ---
> Changes in v3:
>   - Merge binding documentation for Ingenic SoCs whose bindings differ
>     only by their compatible strings.
>
> Changes in v2:
>   - None.
> ---
>  .../devicetree/bindings/serial/ingenic,uart.txt    | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/serial/ingenic,uart.txt
>
> diff --git a/Documentation/devicetree/bindings/serial/ingenic,uart.txt b/Documentation/devicetree/bindings/serial/ingenic,uart.txt
> new file mode 100644
> index 0000000..c2d3b3a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/ingenic,uart.txt
> @@ -0,0 +1,22 @@
> +* Ingenic SoC UART
> +
> +Required properties:
> +- compatible : "ingenic,jz4740-uart" or "ingenic,jz4780-uart"
> +- reg : offset and length of the register set for the device.
> +- interrupts : should contain uart interrupt.
> +- clocks : phandles to the module & baud clocks.
> +- clock-names: tuple listing input clock names.
> +       Required elements: "baud", "module"
> +
> +Example:
> +
> +uart0: serial@10030000 {
> +       compatible = "ingenic,jz4740-uart";
> +       reg = <0x10030000 0x100>;
> +
> +       interrupt-parent = <&intc>;
> +       interrupts = <9>;
> +
> +       clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
> +       clock-names = "baud", "module";
> +};
> --
> 2.3.5
>
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