From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Date: Mon, 15 Jul 2019 11:03:32 -0600 Message-ID: References: <20190713034634.44585-1-icenowy@aosc.io> <20190713034634.44585-8-icenowy@aosc.io> Reply-To: robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <20190713034634.44585-8-icenowy-h8G6r0blFSE@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Icenowy Zheng Cc: Maxime Ripard , Chen-Yu Tsai , Linus Walleij , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , linux-clk , "open list:GPIO SUBSYSTEM" , linux-sunxi List-Id: devicetree@vger.kernel.org On Fri, Jul 12, 2019 at 9:49 PM Icenowy Zheng wrote: > > The Lichee Zero Plus is a core board made by Sipeed, with a microUSB > connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash. > It has a gold finger connector for expansion, and UART is available from > reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or > Allwinner V3L SoCs. > > Add the device tree binding of the basic version of the core board -- > w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. > > Signed-off-by: Icenowy Zheng > --- > No changes since v3. > > Patch introduced in v2. > > Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ > 1 file changed, 5 insertions(+) Reviewed-by: Rob Herring Rob