From: Rob Herring <robh+dt@kernel.org>
To: Adam Skladowski <a39.skl@gmail.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: phone-devel@vger.kernel.org,
~postmarketos/upstreaming@lists.sr.ht,
Rob Clark <robdclark@gmail.com>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>,
Kalyan Thota <quic_kalyant@quicinc.com>,
Jessica Zhang <quic_jesszhan@quicinc.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@somainline.org>,
Loic Poulain <loic.poulain@linaro.org>,
Vinod Koul <vkoul@kernel.org>,
Konrad Dybcio <konrad.dybcio@somainline.org>,
Vinod Polimera <quic_vpolimer@quicinc.com>,
Jason Wang <wangborong@cdjrlc.com>,
Kuogee Hsieh <quic_khsieh@quicinc.com>,
Stephen Boyd <swboyd@chromium.org>,
Douglas Anderson <dianders@chromium.org>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] dt-bindings: display/msm: add support for SM6115
Date: Tue, 29 Nov 2022 11:08:34 -0600 [thread overview]
Message-ID: <CAL_JsqLkhCScw6Rbp8xiMG23UmRNsApyrexvZPabfjZmVBfD_A@mail.gmail.com> (raw)
In-Reply-To: <20221124001708.25720-2-a39.skl@gmail.com>
On Wed, Nov 23, 2022 at 6:17 PM Adam Skladowski <a39.skl@gmail.com> wrote:
>
> Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm
> SM6115 platform.
> Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused.
> Lack of dsi phy supply in example is intended
> due to fact on qcm2290, sm6115 and sm6125
> this phy is supplied via power domain, not regulator.
>
> Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
> ---
> .../bindings/display/msm/qcom,sm6115-dpu.yaml | 94 +++++++++
> .../display/msm/qcom,sm6115-mdss.yaml | 182 ++++++++++++++++++
> 2 files changed, 276 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml
> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml
> new file mode 100644
> index 000000000000..4a39a3031409
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml
> @@ -0,0 +1,94 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Display DPU dt properties for SM6115 target
> +
> +maintainers:
> + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> +
> +$ref: /schemas/display/msm/dpu-common.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,sm6115-dpu
> +
> + reg:
> + items:
> + - description: MDP register set
> + - description: VBIF register set
> +
> + reg-names:
> + items:
> + - const: mdp
> + - const: vbif
> +
> + clocks:
> + items:
> + - description: Display AXI
> + - description: Display AHB
> + - description: Display core
> + - description: Display lut
> + - description: Display rotator
> + - description: Display vsync
> +
> + clock-names:
> + items:
> + - const: bus
> + - const: iface
> + - const: core
> + - const: lut
> + - const: rot
> + - const: vsync
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
> + #include <dt-bindings/clock/qcom,gcc-sm6115.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + display-controller@5e01000 {
> + compatible = "qcom,sm6115-dpu";
> + reg = <0x05e01000 0x8f000>,
> + <0x05eb0000 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc DISP_CC_MDSS_ROT_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
> +
> + operating-points-v2 = <&mdp_opp_table>;
> + power-domains = <&rpmpd SM6115_VDDCX>;
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + endpoint {
> + remote-endpoint = <&dsi0_in>;
> + };
> + };
> + };
> + };
> +...
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
> new file mode 100644
> index 000000000000..a86d7f53fa84
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
> @@ -0,0 +1,182 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM6115 Display MDSS
> +
> +maintainers:
> + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> +
> +description:
> + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
> + sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
> + are mentioned for SM6115 target.
> +
> +$ref: /schemas/display/msm/mdss-common.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,sm6115-mdss
> +
> + clocks:
> + items:
> + - description: Display AHB clock from gcc
> + - description: Display AXI clock
> + - description: Display core clock
> +
> + iommus:
> + maxItems: 2
> +
> +patternProperties:
> + "^display-controller@[0-9a-f]+$":
> + type: object
> + properties:
> + compatible:
> + const: qcom,sm6115-dpu
> +
> + "^dsi@[0-9a-f]+$":
> + type: object
> + properties:
> + compatible:
> + const: qcom,dsi-ctrl-6g-qcm2290
> +
> + "^phy@[0-9a-f]+$":
> + type: object
> + properties:
> + compatible:
> + const: qcom,dsi-phy-14nm-2290
> +
> +required:
> + - compatible
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
> + #include <dt-bindings/clock/qcom,gcc-sm6115.h>
> + #include <dt-bindings/clock/qcom,rpmcc.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + mdss@5e00000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "qcom,sm6115-mdss";
> + reg = <0x05e00000 0x1000>;
> + reg-names = "mdss";
> + power-domains = <&dispcc MDSS_GDSC>;
> + clocks = <&gcc GCC_DISP_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> +
> + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + iommus = <&apps_smmu 0x420 0x2>,
> + <&apps_smmu 0x421 0x0>;
> + ranges;
> +
> + display-controller@5e01000 {
> + compatible = "qcom,sm6115-dpu";
> + reg = <0x05e01000 0x8f000>,
> + <0x05eb0000 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc DISP_CC_MDSS_ROT_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
> +
> + operating-points-v2 = <&mdp_opp_table>;
> + power-domains = <&rpmpd SM6115_VDDCX>;
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&dsi0_in>;
> + };
> + };
> + };
> + };
> +
> + dsi@5e94000 {
> + compatible = "qcom,dsi-ctrl-6g-qcm2290";
> + reg = <0x05e94000 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <4>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>;
> + clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
> + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
> +
> + operating-points-v2 = <&dsi_opp_table>;
> + power-domains = <&rpmpd SM6115_VDDCX>;
> + phys = <&dsi0_phy>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint = <&dpu_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + };
> + };
> + };
> + };
> +
> + dsi0_phy: phy@5e94400 {
> + compatible = "qcom,dsi-phy-14nm-2290";
Now that this is in linux-next, there's a warning:
/builds/robherring/linux-dt/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.example.dtb:
phy@5e94400: 'vcca-supply' is a required property
From schema:
/builds/robherring/linux-dt/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
Perhaps some change in dsi-phy-14nm.yaml.
Rob
next prev parent reply other threads:[~2022-11-29 17:08 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-24 0:16 [PATCH v2 0/2] Add SM6115 MDSS/DPU support Adam Skladowski
2022-11-24 0:16 ` [PATCH v2 1/2] dt-bindings: display/msm: add support for SM6115 Adam Skladowski
2022-11-25 8:06 ` Krzysztof Kozlowski
2022-11-29 17:08 ` Rob Herring [this message]
2022-11-24 0:16 ` [PATCH v2 2/2] drm/msm/disp/dpu1: add support for display on SM6115 Adam Skladowski
2022-11-24 0:19 ` Konrad Dybcio
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