From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 312FD37158 for ; Fri, 27 Oct 2023 15:57:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MDiCaM3t" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AD84EC433C9; Fri, 27 Oct 2023 15:57:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698422224; bh=GNGO9Dy7lzklLJ0376C9oy3DviV7FdG3YmJvVG6RcJU=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=MDiCaM3t2THhJi7+cn47CasKWbC8pAVOfWCAjNYsIusrJ60gyEtXM1m6Dw7O7hAsR afCid2ZmkgQMfoxVPboGgJGiQxWC9ulUvVasMUtZgYRyi1JQ2H6xe4Xthksx4KUE08 lBSInXSgJjM6NVYPLy+JStqPeUhVBJO4i2aTIp+HG1Cl0IS6byl9boIORYO38iXQa5 kSqnBqF83ktKU5QSx8lt51x9n/k9yk62dJPK0Rce8cQ4i7L0nldbjBIJSDCBT/ChZt BQbKS73oixYAQIguSc20zSV3bFsPKimSJnYdFnBeu97Rtgr3yKHXloSP9bRI4M/WJv 8YqZADn7PQTYA== Received: by mail-lj1-f175.google.com with SMTP id 38308e7fff4ca-2b9d07a8d84so29514721fa.3; Fri, 27 Oct 2023 08:57:04 -0700 (PDT) X-Gm-Message-State: AOJu0YxXNKPLkvVAp+FD4R1v+axY6Ld39G5jrUZwl4hVCDd8cGjEkUeg J1T6dmkw8GcN61LIV7UpKOPn0/7mxSedp9tK3g== X-Google-Smtp-Source: AGHT+IEwlNZ95i/dFoxCnlHoH5+6/K3HPIFaerat8lMtZIKbwrzp3SFQx76pV2pk3V3UCLFHaP2Fj7ehg6iUmiep7DU= X-Received: by 2002:ac2:4d90:0:b0:507:a6b6:e5de with SMTP id g16-20020ac24d90000000b00507a6b6e5demr2084401lfe.23.1698422222865; Fri, 27 Oct 2023 08:57:02 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20231024151014.240695-1-nks@flawful.org> <20231024151014.240695-2-nks@flawful.org> <20231024-zoology-preteen-5627e1125ae0@spud> <20231026183501.GB4122054-robh@kernel.org> In-Reply-To: From: Rob Herring Date: Fri, 27 Oct 2023 10:56:50 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 1/4] dt-bindings: PCI: dwc: rockchip: Add atu property To: Niklas Cassel Cc: Conor Dooley , Niklas Cassel , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Lin , Simon Xue , Damien Le Moal , Sebastian Reichel , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-rockchip@lists.infradead.org" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Oct 27, 2023 at 9:35=E2=80=AFAM Niklas Cassel wrote: > > Hello Rob, > > On Thu, Oct 26, 2023 at 01:35:01PM -0500, Rob Herring wrote: > > On Wed, Oct 25, 2023 at 08:02:32PM +0000, Niklas Cassel wrote: > > > Hello Conor, > > > > > > On Tue, Oct 24, 2023 at 05:29:28PM +0100, Conor Dooley wrote: > > > > On Tue, Oct 24, 2023 at 05:10:08PM +0200, Niklas Cassel wrote: > > > > > From: Niklas Cassel > > > > > > > > > > Even though rockchip-dw-pcie.yaml inherits snps,dw-pcie.yaml > > > > > using: > > > > > > > > > > allOf: > > > > > - $ref: /schemas/pci/snps,dw-pcie.yaml# > > > > > > > > > > and snps,dw-pcie.yaml does have the atu property defined, in orde= r to be > > > > > able to use this property, while still making sure 'make CHECK_DT= BS=3Dy' > > > > > pass, we need to add this property to rockchip-dw-pcie.yaml. > > > > > > > > > > Signed-off-by: Niklas Cassel > > > > > --- > > > > > Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 4 = ++++ > > > > > 1 file changed, 4 insertions(+) > > > > > > > > > > diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pc= ie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > > > > index 1ae8dcfa072c..229f8608c535 100644 > > > > > --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > > > > +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > > > > @@ -29,16 +29,20 @@ properties: > > > > > - const: rockchip,rk3568-pcie > > > > > > > > > > reg: > > > > > + minItems: 3 > > > > > items: > > > > > - description: Data Bus Interface (DBI) registers > > > > > - description: Rockchip designed configuration registers > > > > > - description: Config registers > > > > > + - description: iATU registers > > > > > > > > Is this extra register only for the ..88 or for the ..68 and for th= e > > > > ..88 models? > > > > > > Looking at the rk3568 Technical Reference Manual (TRM): > > > https://dl.radxa.com/rock3/docs/hw/datasheet/Rockchip%20RK3568%20TRM%= 20Part2%20V1.1-20210301.pdf > > > > > > The iATU register register range exists for all 3 PCIe controllers > > > found on the rk3568. > > > > > > This register range is currently not defined in the rk3568.dtsi, so t= he driver > > > will currently use the default register offset (which is correct), bu= t with > > > the driver fallback register size that is only big enough to cover 8 = inbound > > > and 8 outbound iATUs (internal Address Translation Units). > > > > We should probably make the driver smarter instead or in addition. We > > have the DBI size, Just make atu_size =3D dbi_size - DEFAULT_DBI_ATU_OF= FSET. > > I though about that, but it seems that some drivers don't use > res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi") > > but instead set pci->dbi_base from non-common code, e.g.: > drivers/pci/controller/dwc/pci-dra7xx.c: pci->dbi_base =3D devm_pl= atform_ioremap_resource_byname(pdev, "ep_dbics"); > drivers/pci/controller/dwc/pci-dra7xx.c: pci->dbi_base =3D devm_pl= atform_ioremap_resource_byname(pdev, "rc_dbics"); > drivers/pci/controller/dwc/pci-imx6.c: pci->dbi_base =3D devm_platform_g= et_and_ioremap_resource(pdev, 0, &dbi_base); > drivers/pci/controller/dwc/pci-keystone.c: pci->dbi_base =3D base; > drivers/pci/controller/dwc/pci-layerscape-ep.c: dbi_base =3D platform_get= _resource_byname(pdev, IORESOURCE_MEM, "regs"); > drivers/pci/controller/dwc/pci-layerscape-ep.c: pci->dbi_base =3D devm_pc= i_remap_cfg_resource(dev, dbi_base); > drivers/pci/controller/dwc/pci-layerscape.c: dbi_base =3D platform_get= _resource_byname(pdev, IORESOURCE_MEM, "regs"); > drivers/pci/controller/dwc/pci-layerscape.c: pci->dbi_base =3D devm_pc= i_remap_cfg_resource(dev, dbi_base); > drivers/pci/controller/dwc/pci-meson.c: pci->dbi_base =3D devm_platform_i= oremap_resource_byname(pdev, "elbi"); > drivers/pci/controller/dwc/pcie-al.c: void __iomem *dbi_base =3D pcie->= dbi_base; > drivers/pci/controller/dwc/pcie-al.c: al_pcie->dbi_base =3D devm_pci_re= map_cfg_resource(dev, res); > drivers/pci/controller/dwc/pcie-armada8k.c: pci->dbi_base =3D devm_pc= i_remap_cfg_resource(dev, base); > drivers/pci/controller/dwc/pcie-designware.c: pci->dbi_base =3D= devm_pci_remap_cfg_resource(pci->dev, res); > drivers/pci/controller/dwc/pcie-histb.c: pci->dbi_base =3D devm_pl= atform_ioremap_resource_byname(pdev, "rc-dbi"); > drivers/pci/controller/dwc/pcie-qcom-ep.c: pci->dbi_base =3D devm_pc= i_remap_cfg_resource(dev, res); > drivers/pci/controller/dwc/pcie-tegra194-acpi.c: pcie_ecam->dbi_ba= se =3D cfg->win + SZ_512K; > > So I don't think that we can always get the size of the dbi. > And a solution that does not work for all platforms is not > that appealing. Do I get a chance to respond before you send a new version? Does something like the patch below not work for everyone? We could store the DBI size as well if we want more than 8 regions to work without a 'dbi' nor 'atu' region defined. We shouldn't have new users doing that though. diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 250cf7f40b85..3dc71ea7fa76 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -105,11 +105,13 @@ int dw_pcie_get_resources(struct dw_pcie *pci) struct platform_device *pdev =3D to_platform_device(pci->dev); struct device_node *np =3D dev_of_node(pci->dev); struct resource *res; + size_t dbi_size =3D DEFAULT_DBI_ATU_OFFSET + SZ_4K; int ret; if (!pci->dbi_base) { res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, = "dbi"); pci->dbi_base =3D devm_pci_remap_cfg_resource(pci->dev, res= ); + dbi_size =3D resource_size(res); if (IS_ERR(pci->dbi_base)) return PTR_ERR(pci->dbi_base); } @@ -136,13 +138,10 @@ int dw_pcie_get_resources(struct dw_pcie *pci) return PTR_ERR(pci->atu_base); } else { pci->atu_base =3D pci->dbi_base + DEFAULT_DBI_ATU_O= FFSET; + pci->atu_size =3D dbi_size - DEFAULT_DBI_ATU_OFFSET= ; } } - /* Set a default value suitable for at most 8 in and 8 out windows = */ - if (!pci->atu_size) - pci->atu_size =3D SZ_4K; - /* eDMA region can be mapped to a custom base address */ if (!pci->edma.reg_base) { res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, = "dma");