From: Evan Green <evan@rivosinc.com>
To: Jesse Taube <jesse@rivosinc.com>
Cc: linux-riscv@lists.infradead.org,
"Jonathan Corbet" <corbet@lwn.net>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Clément Léger" <cleger@rivosinc.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Charlie Jenkins" <charlie@rivosinc.com>,
"Xiao Wang" <xiao.w.wang@intel.com>,
"Andy Chiu" <andy.chiu@sifive.com>,
"Eric Biggers" <ebiggers@google.com>,
"Greentime Hu" <greentime.hu@sifive.com>,
"Björn Töpel" <bjorn@rivosinc.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Costa Shulyupin" <costa.shul@redhat.com>,
"Andrew Morton" <akpm@linux-foundation.org>,
"Baoquan He" <bhe@redhat.com>,
"Anup Patel" <apatel@ventanamicro.com>,
"Zong Li" <zong.li@sifive.com>,
"Sami Tolvanen" <samitolvanen@google.com>,
"Ben Dooks" <ben.dooks@codethink.co.uk>,
"Alexandre Ghiti" <alexghiti@rivosinc.com>,
"Gustavo A. R. Silva" <gustavoars@kernel.org>,
"Erick Archer" <erick.archer@gmx.com>,
"Joel Granados" <j.granados@samsung.com>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH v3 3/8] RISC-V: Check scalar unaligned access on all CPUs
Date: Wed, 10 Jul 2024 08:55:35 -0700 [thread overview]
Message-ID: <CALs-HsvE9PzTrhVO0umh3KaJuLQLdk-h8sYKBg7XA4a-MXAmOg@mail.gmail.com> (raw)
In-Reply-To: <20240625005001.37901-4-jesse@rivosinc.com>
On Mon, Jun 24, 2024 at 5:51 PM Jesse Taube <jesse@rivosinc.com> wrote:
>
> Originally, the check_unaligned_access_emulated_all_cpus function
> only checked the boot hart. This fixes the function to check all
> harts.
>
> Fixes: 71c54b3d169d ("riscv: report misaligned accesses emulation to hwprobe")
> Signed-off-by: Jesse Taube <jesse@rivosinc.com>
> Cc: stable@vger.kernel.org
> ---
> V1 -> V2:
> - New patch
> V2 -> V3:
> - Split patch
> ---
> arch/riscv/kernel/traps_misaligned.c | 23 ++++++-----------------
> 1 file changed, 6 insertions(+), 17 deletions(-)
>
> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> index b62d5a2f4541..8fadbe00dd62 100644
> --- a/arch/riscv/kernel/traps_misaligned.c
> +++ b/arch/riscv/kernel/traps_misaligned.c
> @@ -526,31 +526,17 @@ int handle_misaligned_store(struct pt_regs *regs)
> return 0;
> }
>
> -static bool check_unaligned_access_emulated(int cpu)
> +static void check_unaligned_access_emulated(struct work_struct *unused)
> {
> + int cpu = smp_processor_id();
> long *mas_ptr = per_cpu_ptr(&misaligned_access_speed, cpu);
> unsigned long tmp_var, tmp_val;
> - bool misaligned_emu_detected;
>
> *mas_ptr = RISCV_HWPROBE_MISALIGNED_UNKNOWN;
>
> __asm__ __volatile__ (
> " "REG_L" %[tmp], 1(%[ptr])\n"
> : [tmp] "=r" (tmp_val) : [ptr] "r" (&tmp_var) : "memory");
> -
> - misaligned_emu_detected = (*mas_ptr == RISCV_HWPROBE_MISALIGNED_EMULATED);
> - /*
> - * If unaligned_ctl is already set, this means that we detected that all
> - * CPUS uses emulated misaligned access at boot time. If that changed
> - * when hotplugging the new cpu, this is something we don't handle.
> - */
> - if (unlikely(unaligned_ctl && !misaligned_emu_detected)) {
> - pr_crit("CPU misaligned accesses non homogeneous (expected all emulated)\n");
> - while (true)
> - cpu_relax();
> - }
This chunk was meant to detect and refuse to run on a system where a
heterogeneous CPU is hotplugged into a previously homogenous system.
The commit message doesn't mention this change, how come you
deleted it?
> -
> - return misaligned_emu_detected;
> }
>
> bool check_unaligned_access_emulated_all_cpus(void)
> @@ -562,8 +548,11 @@ bool check_unaligned_access_emulated_all_cpus(void)
> * accesses emulated since tasks requesting such control can run on any
> * CPU.
> */
> + schedule_on_each_cpu(check_unaligned_access_emulated);
> +
> for_each_online_cpu(cpu)
> - if (!check_unaligned_access_emulated(cpu))
> + if (per_cpu(misaligned_access_speed, cpu)
> + != RISCV_HWPROBE_MISALIGNED_EMULATED)
> return false;
>
> unaligned_ctl = true;
> --
> 2.45.2
>
next prev parent reply other threads:[~2024-07-10 15:56 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-25 0:49 [PATCH v3 0/8] RISC-V: Detect and report speed of unaligned vector accesses Jesse Taube
2024-06-25 0:49 ` [PATCH v3 1/8] RISC-V: Add Zicclsm to cpufeature and hwprobe Jesse Taube
2024-06-26 14:41 ` Conor Dooley
2024-06-25 0:49 ` [PATCH v3 2/8] dt-bindings: riscv: Add Zicclsm ISA extension description Jesse Taube
2024-06-25 0:49 ` [PATCH v3 3/8] RISC-V: Check scalar unaligned access on all CPUs Jesse Taube
2024-07-10 15:55 ` Evan Green [this message]
2024-07-11 20:25 ` Jesse Taube
2024-06-25 0:49 ` [PATCH v3 4/8] RISC-V: Check Zicclsm to set unaligned access speed Jesse Taube
2024-06-26 14:39 ` Conor Dooley
2024-06-27 21:20 ` Charlie Jenkins
2024-07-01 7:15 ` Clément Léger
2024-07-01 13:58 ` Conor Dooley
2024-07-01 14:20 ` Clément Léger
2024-07-02 22:22 ` Charlie Jenkins
2024-07-03 7:13 ` Clément Léger
2024-07-03 21:47 ` Jesse Taube
2024-06-25 0:49 ` [PATCH v3 5/8] RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED Jesse Taube
2024-06-26 14:39 ` Conor Dooley
2024-06-25 0:49 ` [PATCH v3 6/8] RISC-V: Detect unaligned vector accesses supported Jesse Taube
2024-07-01 15:13 ` Samuel Holland
2024-06-25 0:50 ` [PATCH v3 7/8] RISC-V: Report vector unaligned access speed hwprobe Jesse Taube
2024-07-01 22:51 ` Evan Green
2024-07-11 20:35 ` Jesse Taube
2024-06-25 0:50 ` [PATCH v3 8/8] RISC-V: hwprobe: Document unaligned vector perf key Jesse Taube
2024-06-26 14:37 ` Conor Dooley
2024-07-01 22:55 ` Evan Green
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