[PATCH v5 0/5] MCPM backend for Exynos5420

[PATCH v5 0/5] MCPM backend for Exynos5420

[Abhilash Kesavan]

This is v5 of the series adding MCPM backend support for SMP secondary boot
and core switching on Samsung's Exynos5420. The patches are based on the mcpm
support added for Exynos5420 in the Chromium kernel repository here:
https://chromium.googlesource.com/chromiumos/third_party/kernel-next/+/chromeos-3.8

This patchset depends on:
- [v2,1/2] ARM: EXYNOS: Map SYSRAM through generic SRAM bindings
(https://patchwork.kernel.org/patch/4101091/)

The patches have been prepared on linux-next(20140502) and tested on SMDK5420
EVT1 using the "/dev/b.L_switcher" user interface. Secondary core boot-up has
also been tested on an Exynos5420-based chromebook.

Changes since v4:
Addressed the following comments from Nicolas Pitre:
	- Fixed the location of L2 prefetching disable code.
	- Fixed the location of the "TODO" comment.
	- Fixed a possible race in mcpm cluster state check in
	  exynos_power_up().
	
Changes since v3:
	- Rebased on top of the latest SYSRAM DT patchset from Sachin Kamat.

Addressed the following comments from Lorenzo Pieralisi and Nicolas Pitre:
	- Dropped the patch "arm: exynos: Add /dev/bL_status user interface on
	  Exynos5420".
	- Fixed the header ordering and removed unnecessary header inclusions.
	- Made the code symmetric in exynos_cluster_power_control().
	- Fixed the error path in exynos_power_up.
	- Got rid of "cnt" variable used for last man checking.
	- Removed stale comments.
	- Replaced "soc_is" with "of_find_compatible_node" check for exynos5420.
	- Added L2 prefetching disable code needed during A15 power down.

Changes since v2:
Addressed the following comments from Nicolas Pitre and Daniel Lezcano:
	- Added generic common (cluster) configuration functions to pm.c
	  which may be used by other subsystems.
	- Removed unused "cpumask" variable in mcpm code.
	- Re-worked exynos_power_down_finish() referencing the tc2_pm code.
	- Removed the status checks in core and cluster power functions. We
	  just set the power control bit and do not check the previous state
	  anymore.
	- Removed incorrect jiffies timeout usage in path where IRQs are
	  disabled.

Changes since v1:
Addressed the following comments from Dave Martin and Nicolas Pitre:
	- Fixed help text for EXYNOS5420_MCPM symbol.
	- Removed mcpm-exynos-setup.S file and added similar code from tc2_pm.c.
	- Changed the spinlock name from "bl_lock" to "exynos_mcpm_lock".
	- Removed snoop enable/disable calls due to possible cpuidle issue and
	  not having numbers proving a significant power savings. Dropped the
	  "drivers/bus: arm-cci: Add common control interface for ACE ports"
	  patch from v1 as it was no longer needed.
	- Created a macro for exynos-specific v7_exit_coherency_flush which
	  handles an erratum. This was done to prevent duplication of code.
	- Removed "outer_flush_all" call.
	- Removed redundant dsb in power_down function.
	- Removed unnecessary initialization of global variables to zero.
	- Split the /dev/bL_status debug interface into another patch.
	- Fixed error handling in exynos_mcpm_init().
	- Called mcpm_smp_set_ops directly from exynos_mcpm_init().
	- Added a TODO for supporting cluster down on exynos5420.

NOTE:
- Have added Leela Krishna's generic cpu power control function series
  as part of this patchset.
- Only the patch "arm: exynos: Add MCPM call-back functions" has changed
  from v3.
- I have tested with and without the erratum 799270 workaround and both
  work fine. I have kept the erratum fix for the time being.

Abhilash Kesavan (2):
  arm: exynos: Add generic cluster power control functions
  arm: exynos: Add MCPM call-back functions

Andrew Bresticker (1):
  ARM: dts: exynos5420: add CCI node

Leela Krishna Amudala (2):
  ARM: EXYNOS: Add generic cpu power control functions for all exynos
    based SoCs
  ARM: EXYNOS: use generic exynos cpu power control functions

 arch/arm/boot/dts/exynos5420.dtsi  |   27 +++
 arch/arm/mach-exynos/Kconfig       |    8 +
 arch/arm/mach-exynos/Makefile      |    2 +
 arch/arm/mach-exynos/common.h      |    6 +
 arch/arm/mach-exynos/mcpm-exynos.c |  344 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/platsmp.c     |    9 +-
 arch/arm/mach-exynos/pm.c          |   66 +++++++
 arch/arm/mach-exynos/regs-pmu.h    |   15 ++
 8 files changed, 471 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/mach-exynos/mcpm-exynos.c

-- 
1.7.9.5

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[PATCH v5 1/5] ARM: EXYNOS: Add generic cpu power control functions for all exynos based SoCs

[Abhilash Kesavan]

From: Leela Krishna Amudala <leela.krishna-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

Add generic cpu power control functions for exynos based SoCS
for cpu power up/down and to know the cpu status.

Signed-off-by: Leela Krishna Amudala <leela.krishna-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
 arch/arm/mach-exynos/common.h   |    3 +++
 arch/arm/mach-exynos/pm.c       |   36 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/regs-pmu.h |    6 ++++++
 3 files changed, 45 insertions(+)

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 47cbab0..a7dbb5f 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -63,5 +63,8 @@ struct exynos_pmu_conf {
 };
 
 extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
+extern void exynos_cpu_powerdown(int cpu);
+extern void exynos_cpu_powerup(int cpu);
+extern int  exynos_cpu_power_state(int cpu);
 
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 15af0ce..6651028 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -100,6 +100,42 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
 	return -ENOENT;
 }
 
+/**
+ * exynos_cpu_powerdown : power down the specified cpu
+ * @cpu : the cpu to power down
+ *
+ * Power downs the specified cpu. The sequence must be finished by a
+ * call to cpu_do_idle()
+ *
+ */
+void exynos_cpu_powerdown(int cpu)
+{
+	__raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+}
+
+/**
+ * exynos_cpu_powerup : power up the specified cpu
+ * @cpu : the cpu to power up
+ *
+ * Power up the specified cpu
+ */
+void exynos_cpu_powerup(int cpu)
+{
+	__raw_writel(S5P_CORE_LOCAL_PWR_EN,
+		     EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+}
+
+/**
+ * exynos_cpu_power_state : returns the power state of the cpu
+ * @cpu : the cpu to retrieve the power state from
+ *
+ */
+int exynos_cpu_power_state(int cpu)
+{
+	return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
+			S5P_CORE_LOCAL_PWR_EN);
+}
+
 /* For Cortex-A9 Diagnostic and Power control register */
 static unsigned int save_arm_register[2];
 
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4f6a256..0bdfcbc 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -121,6 +121,12 @@
 
 #define S5P_CHECK_SLEEP				0x00000BAD
 
+#define EXYNOS_ARM_CORE0_CONFIGURATION		S5P_PMUREG(0x2000)
+#define EXYNOS_ARM_CORE_CONFIGURATION(_nr)	\
+			(EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
+#define EXYNOS_ARM_CORE_STATUS(_nr)		\
+			(EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
+
 /* Only for EXYNOS4210 */
 #define S5P_CMU_CLKSTOP_LCD1_LOWPWR	S5P_PMUREG(0x1154)
 #define S5P_CMU_RESET_LCD1_LOWPWR	S5P_PMUREG(0x1174)
-- 
1.7.9.5

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[PATCH v5 2/5] ARM: EXYNOS: use generic exynos cpu power control functions

[Abhilash Kesavan]

From: Leela Krishna Amudala <leela.krishna-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

Use generic exynos cpu power control functions to power up/down
and to know the status of the cpu.

Signed-off-by: Leela Krishna Amudala <leela.krishna-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
 arch/arm/mach-exynos/platsmp.c |    9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 0aac032..d442a66 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -130,15 +130,12 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
 	 */
 	write_pen_release(phys_cpu);
 
-	if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
-		__raw_writel(S5P_CORE_LOCAL_PWR_EN,
-			     S5P_ARM_CORE1_CONFIGURATION);
-
+	if (!exynos_cpu_power_state(cpu)) {
+		exynos_cpu_powerup(cpu);
 		timeout = 10;
 
 		/* wait max 10 ms until cpu1 is on */
-		while ((__raw_readl(S5P_ARM_CORE1_STATUS)
-			& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
+		while (exynos_cpu_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN) {
 			if (timeout-- == 0)
 				break;
 
-- 
1.7.9.5

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[PATCH v5 3/5] arm: exynos: Add generic cluster power control functions

[Abhilash Kesavan]

Add generic cluster power control functions for exynos based SoCS
for cluster power up/down and to know the cluster status.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 arch/arm/mach-exynos/common.h   |    3 +++
 arch/arm/mach-exynos/pm.c       |   30 ++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/regs-pmu.h |    6 ++++++
 3 files changed, 39 insertions(+)

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index a7dbb5f..03b8bb2 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -66,5 +66,8 @@ extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
 extern void exynos_cpu_powerdown(int cpu);
 extern void exynos_cpu_powerup(int cpu);
 extern int  exynos_cpu_power_state(int cpu);
+extern void exynos_cluster_powerdown(int cluster);
+extern void exynos_cluster_powerup(int cluster);
+extern int  exynos_cluster_power_state(int cluster);
 
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 6651028..f02d864 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -136,6 +136,36 @@ int exynos_cpu_power_state(int cpu)
 			S5P_CORE_LOCAL_PWR_EN);
 }
 
+/**
+ * exynos_common_powerdown : power down the specified cluster
+ * @cluster : the cluster to power down
+ */
+void exynos_cluster_powerdown(int cluster)
+{
+	__raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
+}
+
+/**
+ * exynos_cluster_powerup : power up the specified cluster
+ * @cluster : the cluster to power up
+ */
+void exynos_cluster_powerup(int cluster)
+{
+	__raw_writel(S5P_CORE_LOCAL_PWR_EN,
+		     EXYNOS_COMMON_CONFIGURATION(cluster));
+}
+
+/**
+ * exynos_cluster_power_state : returns the power state of the cluster
+ * @cluster : the cluster to retrieve the power state from
+ *
+ */
+int exynos_cluster_power_state(int cluster)
+{
+	return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
+			S5P_CORE_LOCAL_PWR_EN);
+}
+
 /* For Cortex-A9 Diagnostic and Power control register */
 static unsigned int save_arm_register[2];
 
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 0bdfcbc..6685ebf 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -127,6 +127,12 @@
 #define EXYNOS_ARM_CORE_STATUS(_nr)		\
 			(EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
 
+#define EXYNOS_ARM_COMMON_CONFIGURATION		S5P_PMUREG(0x2500)
+#define EXYNOS_COMMON_CONFIGURATION(_nr)	\
+			(EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr)))
+#define EXYNOS_COMMON_STATUS(_nr)		\
+			(EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4)
+
 /* Only for EXYNOS4210 */
 #define S5P_CMU_CLKSTOP_LCD1_LOWPWR	S5P_PMUREG(0x1154)
 #define S5P_CMU_RESET_LCD1_LOWPWR	S5P_PMUREG(0x1174)
-- 
1.7.9.5

[PATCH v5 4/5] ARM: dts: exynos5420: add CCI node

[Abhilash Kesavan]

From: Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>

Add device-tree bindings for the ARM CCI-400 on Exynos5420.  There
are two slave interfaces: one for the A15 cluster and one for the
A7 cluster.

Signed-off-by: Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Abhilash Kesavan <a.kesavan-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
 arch/arm/boot/dts/exynos5420.dtsi |   27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index ff496ad..3140138 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -58,6 +58,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <0x0>;
 			clock-frequency = <1800000000>;
+			cci-control-port = <&cci_control1>;
 		};
 
 		cpu1: cpu@1 {
@@ -65,6 +66,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <0x1>;
 			clock-frequency = <1800000000>;
+			cci-control-port = <&cci_control1>;
 		};
 
 		cpu2: cpu@2 {
@@ -72,6 +74,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <0x2>;
 			clock-frequency = <1800000000>;
+			cci-control-port = <&cci_control1>;
 		};
 
 		cpu3: cpu@3 {
@@ -79,6 +82,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <0x3>;
 			clock-frequency = <1800000000>;
+			cci-control-port = <&cci_control1>;
 		};
 
 		cpu4: cpu@100 {
@@ -86,6 +90,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x100>;
 			clock-frequency = <1000000000>;
+			cci-control-port = <&cci_control0>;
 		};
 
 		cpu5: cpu@101 {
@@ -93,6 +98,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x101>;
 			clock-frequency = <1000000000>;
+			cci-control-port = <&cci_control0>;
 		};
 
 		cpu6: cpu@102 {
@@ -100,6 +106,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x102>;
 			clock-frequency = <1000000000>;
+			cci-control-port = <&cci_control0>;
 		};
 
 		cpu7: cpu@103 {
@@ -107,6 +114,26 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x103>;
 			clock-frequency = <1000000000>;
+			cci-control-port = <&cci_control0>;
+		};
+	};
+
+	cci@10d20000 {
+		compatible = "arm,cci-400";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x10d20000 0x1000>;
+		ranges = <0x0 0x10d20000 0x6000>;
+
+		cci_control0: slave-if@4000 {
+			compatible = "arm,cci-400-ctrl-if";
+			interface-type = "ace";
+			reg = <0x4000 0x1000>;
+		};
+		cci_control1: slave-if@5000 {
+			compatible = "arm,cci-400-ctrl-if";
+			interface-type = "ace";
+			reg = <0x5000 0x1000>;
 		};
 	};
 
-- 
1.7.9.5

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[PATCH v5 5/5] arm: exynos: Add MCPM call-back functions

[Abhilash Kesavan]

Add machine-dependent MCPM call-backs for Exynos5420. These are used
to power up/down the secondary CPUs during boot, shutdown, s2r and
switching.

Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Inderpal Singh <inderpal.s@samsung.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 arch/arm/mach-exynos/Kconfig       |    8 +
 arch/arm/mach-exynos/Makefile      |    2 +
 arch/arm/mach-exynos/mcpm-exynos.c |  344 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/regs-pmu.h    |    3 +
 4 files changed, 357 insertions(+)
 create mode 100644 arch/arm/mach-exynos/mcpm-exynos.c

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 5c34dc2..138070e 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -73,4 +73,12 @@ config SOC_EXYNOS5440
 
 endmenu
 
+config EXYNOS5420_MCPM
+	bool "Exynos5420 Multi-Cluster PM support"
+	depends on MCPM && SOC_EXYNOS5420
+	select ARM_CCI
+	help
+	  This is needed to provide CPU and cluster power management
+	  on Exynos5420 implementing big.LITTLE.
+
 endif
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index a656dbe..01bc9b9 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -29,3 +29,5 @@ obj-$(CONFIG_ARCH_EXYNOS)	+= firmware.o
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_exynos-smc.o		:=-Wa,-march=armv7-a$(plus_sec)
+
+obj-$(CONFIG_EXYNOS5420_MCPM)	+= mcpm-exynos.o
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
new file mode 100644
index 0000000..e578007
--- /dev/null
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -0,0 +1,344 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * arch/arm/mach-exynos/mcpm-exynos.c
+ *
+ * Based on arch/arm/mach-vexpress/dcscb.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/arm-cci.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+#include <asm/mcpm.h>
+
+#include "regs-pmu.h"
+#include "common.h"
+
+#define EXYNOS5420_CPUS_PER_CLUSTER	4
+#define EXYNOS5420_NR_CLUSTERS		2
+
+/* Non-secure iRAM base address */
+static void __iomem *ns_sram_base_addr;
+
+/*
+ * The common v7_exit_coherency_flush API could not be used because of the
+ * Erratum 799270 workaround. This macro is the same as the common one (in
+ * arch/arm/include/asm/cacheflush.h) except for the erratum handling.
+ */
+#define exynos_v7_exit_coherency_flush(level) \
+	asm volatile( \
+	"stmfd	sp!, {fp, ip}\n\t"\
+	"mrc	p15, 0, r0, c1, c0, 0	@ get SCTLR\n\t" \
+	"bic	r0, r0, #"__stringify(CR_C)"\n\t" \
+	"mcr	p15, 0, r0, c1, c0, 0	@ set SCTLR\n\t" \
+	"isb\n\t"\
+	"bl	v7_flush_dcache_"__stringify(level)"\n\t" \
+	"clrex\n\t"\
+	"mrc	p15, 0, r0, c1, c0, 1	@ get ACTLR\n\t" \
+	"bic	r0, r0, #(1 << 6)	@ disable local coherency\n\t" \
+	/* Dummy Load of a device register to avoid Erratum 799270 */ \
+	"ldr	r4, [%0]\n\t" \
+	"and	r4, r4, #0\n\t" \
+	"orr	r0, r0, r4\n\t" \
+	"mcr	p15, 0, r0, c1, c0, 1	@ set ACTLR\n\t" \
+	"isb\n\t" \
+	"dsb\n\t" \
+	"ldmfd	sp!, {fp, ip}" \
+	: \
+	: "Ir" (S5P_INFORM0) \
+	: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
+	  "r9", "r10", "lr", "memory")
+
+/*
+ * We can't use regular spinlocks. In the switcher case, it is possible
+ * for an outbound CPU to call power_down() after its inbound counterpart
+ * is already live using the same logical CPU number which trips lockdep
+ * debugging.
+ */
+static arch_spinlock_t exynos_mcpm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+static int
+cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS];
+
+#define exynos_cluster_usecnt(cluster) \
+	(cpu_use_count[0][cluster] +   \
+	 cpu_use_count[1][cluster] +   \
+	 cpu_use_count[2][cluster] +   \
+	 cpu_use_count[3][cluster])
+
+#define exynos_cluster_unused(cluster) !exynos_cluster_usecnt(cluster)
+
+static int exynos_cluster_power_control(unsigned int cluster, int enable)
+{
+	unsigned int tries = 100;
+	unsigned int val;
+
+	if (enable) {
+		exynos_cluster_powerup(cluster);
+		val = S5P_CORE_LOCAL_PWR_EN;
+	} else {
+		exynos_cluster_powerdown(cluster);
+		val = 0;
+	}
+
+	/* Wait until cluster power control is applied */
+	while (tries--) {
+		if (exynos_cluster_power_state(cluster) == val)
+			return 0;
+
+		cpu_relax();
+	}
+	pr_warn("timed out waiting for cluster %u to power %s\n", cluster,
+		enable ? "on" : "off");
+
+	return -ETIMEDOUT;
+}
+
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+	unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+	int err = 0;
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+		cluster >= EXYNOS5420_NR_CLUSTERS)
+		return -EINVAL;
+
+	/*
+	 * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+	 * variant exists, we need to disable IRQs manually here.
+	 */
+	local_irq_disable();
+	arch_spin_lock(&exynos_mcpm_lock);
+
+	cpu_use_count[cpu][cluster]++;
+	if (cpu_use_count[cpu][cluster] == 1) {
+		bool was_cluster_down =
+			(exynos_cluster_usecnt(cluster) == 1);
+
+		/*
+		 * Turn on the cluster (L2/COMMON) and then power on the
+		 * cores.
+		 */
+		if (was_cluster_down)
+			err = exynos_cluster_power_control(cluster, 1);
+
+		if (!err)
+			exynos_cpu_powerup(cpunr);
+		else
+			exynos_cluster_power_control(cluster, 0);
+	} else if (cpu_use_count[cpu][cluster] != 2) {
+		/*
+		 * The only possible values are:
+		 * 0 = CPU down
+		 * 1 = CPU (still) up
+		 * 2 = CPU requested to be up before it had a chance
+		 *     to actually make itself down.
+		 * Any other value is a bug.
+		 */
+		BUG();
+	}
+
+	arch_spin_unlock(&exynos_mcpm_lock);
+	local_irq_enable();
+
+	return err;
+}
+
+static void exynos_power_down(void)
+{
+	unsigned int mpidr, cpu, cluster;
+	bool last_man = false, skip_wfi = false;
+	unsigned int cpunr;
+
+	mpidr = read_cpuid_mpidr();
+	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+	cpunr =  cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+			cluster >= EXYNOS5420_NR_CLUSTERS);
+
+	__mcpm_cpu_going_down(cpu, cluster);
+
+	arch_spin_lock(&exynos_mcpm_lock);
+	BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+	cpu_use_count[cpu][cluster]--;
+	if (cpu_use_count[cpu][cluster] == 0) {
+		exynos_cpu_powerdown(cpunr);
+
+		if (exynos_cluster_unused(cluster))
+			/* TODO: Turn off the cluster here to save power. */
+			last_man = true;
+	} else if (cpu_use_count[cpu][cluster] == 1) {
+		/*
+		 * A power_up request went ahead of us.
+		 * Even if we do not want to shut this CPU down,
+		 * the caller expects a certain state as if the WFI
+		 * was aborted.  So let's continue with cache cleaning.
+		 */
+		skip_wfi = true;
+	} else {
+		BUG();
+	}
+
+	if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+		arch_spin_unlock(&exynos_mcpm_lock);
+
+		if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
+			/*
+			 * On the Cortex-A15 we need to disable
+			 * L2 prefetching before flushing the cache.
+			 */
+			asm volatile(
+			"mcr	p15, 1, %0, c15, c0, 3\n\t"
+			"isb\n\t"
+			"dsb"
+			: : "r" (0x400));
+		}
+
+		/* Flush all cache levels for this cluster. */
+		exynos_v7_exit_coherency_flush(all);
+
+		/*
+		 * Disable cluster-level coherency by masking
+		 * incoming snoops and DVM messages:
+		 */
+		cci_disable_port_by_cpu(mpidr);
+
+		__mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+	} else {
+		arch_spin_unlock(&exynos_mcpm_lock);
+
+		/* Disable and flush the local CPU cache. */
+		exynos_v7_exit_coherency_flush(louis);
+	}
+
+	__mcpm_cpu_down(cpu, cluster);
+
+	/* Now we are prepared for power-down, do it: */
+	if (!skip_wfi)
+		wfi();
+
+	/* Not dead at this point?  Let our caller cope. */
+}
+
+static int exynos_power_down_finish(unsigned int cpu, unsigned int cluster)
+{
+	unsigned int tries = 100;
+	unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+			cluster >= EXYNOS5420_NR_CLUSTERS);
+
+	/* Wait for the core state to be OFF */
+	while (tries--) {
+		if (ACCESS_ONCE(cpu_use_count[cpu][cluster]) == 0) {
+			if ((exynos_cpu_power_state(cpunr) == 0))
+				return 0; /* success: the CPU is halted */
+		}
+
+		/* Otherwise, wait and retry: */
+		msleep(1);
+	}
+
+	return -ETIMEDOUT; /* timeout */
+}
+
+static const struct mcpm_platform_ops exynos_power_ops = {
+	.power_up		= exynos_power_up,
+	.power_down		= exynos_power_down,
+	.power_down_finish	= exynos_power_down_finish,
+};
+
+static void __init exynos_mcpm_usage_count_init(void)
+{
+	unsigned int mpidr, cpu, cluster;
+
+	mpidr = read_cpuid_mpidr();
+	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER  ||
+			cluster >= EXYNOS5420_NR_CLUSTERS);
+
+	cpu_use_count[cpu][cluster] = 1;
+}
+
+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ */
+static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
+{
+	asm volatile ("\n"
+	"cmp	r0, #1\n"
+	"bxne	lr\n"
+	"b	cci_enable_port_for_self");
+}
+
+static int __init exynos_mcpm_init(void)
+{
+	struct device_node *node;
+	int ret = 0;
+
+	node = of_find_compatible_node(NULL, NULL, "samsung,exynos5420");
+	if (!node)
+		return -ENODEV;
+	of_node_put(node);
+
+	if (!cci_probed())
+		return -ENODEV;
+
+	node = of_find_compatible_node(NULL, NULL,
+			"samsung,exynos4210-sram-ns");
+	if (!node)
+		return -ENODEV;
+
+	ns_sram_base_addr = of_iomap(node, 0);
+	of_node_put(node);
+	if (!ns_sram_base_addr) {
+		pr_err("failed to map non-secure iRAM base address\n");
+		return -ENOMEM;
+	}
+
+	/*
+	 * To increase the stability of KFC reset we need to program
+	 * the PMU SPARE3 register
+	 */
+	__raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
+
+	exynos_mcpm_usage_count_init();
+
+	ret = mcpm_platform_register(&exynos_power_ops);
+	if (!ret)
+		ret = mcpm_sync_init(exynos_pm_power_up_setup);
+	if (ret) {
+		iounmap(ns_sram_base_addr);
+		return ret;
+	}
+
+	mcpm_smp_set_ops();
+
+	pr_info("Exynos MCPM support installed\n");
+
+	/*
+	 * Future entries into the kernel can now go
+	 * through the cluster entry vectors.
+	 */
+	__raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 0x1c);
+
+	return ret;
+}
+
+early_initcall(exynos_mcpm_init);
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 6685ebf..f44d318 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -38,6 +38,7 @@
 #define S5P_INFORM5				S5P_PMUREG(0x0814)
 #define S5P_INFORM6				S5P_PMUREG(0x0818)
 #define S5P_INFORM7				S5P_PMUREG(0x081C)
+#define S5P_PMU_SPARE3				S5P_PMUREG(0x090C)
 
 #define S5P_ARM_CORE0_LOWPWR			S5P_PMUREG(0x1000)
 #define S5P_DIS_IRQ_CORE0			S5P_PMUREG(0x1004)
@@ -325,4 +326,6 @@
 
 #define EXYNOS5_OPTION_USE_RETENTION				(1 << 4)
 
+#define EXYNOS5420_SWRESET_KFC_SEL				0x3
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
-- 
1.7.9.5

Re: [PATCH v5 5/5] arm: exynos: Add MCPM call-back functions

[Nicolas Pitre]

On Mon, 5 May 2014, Abhilash Kesavan wrote:

> Add machine-dependent MCPM call-backs for Exynos5420. These are used
> to power up/down the secondary CPUs during boot, shutdown, s2r and
> switching.
> 
> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
> Signed-off-by: Inderpal Singh <inderpal.s@samsung.com>
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>

Reviewed-by: Nicolas Pitre <nicoo@linaro.org>


> ---
>  arch/arm/mach-exynos/Kconfig       |    8 +
>  arch/arm/mach-exynos/Makefile      |    2 +
>  arch/arm/mach-exynos/mcpm-exynos.c |  344 ++++++++++++++++++++++++++++++++++++
>  arch/arm/mach-exynos/regs-pmu.h    |    3 +
>  4 files changed, 357 insertions(+)
>  create mode 100644 arch/arm/mach-exynos/mcpm-exynos.c
> 
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index 5c34dc2..138070e 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -73,4 +73,12 @@ config SOC_EXYNOS5440
>  
>  endmenu
>  
> +config EXYNOS5420_MCPM
> +	bool "Exynos5420 Multi-Cluster PM support"
> +	depends on MCPM && SOC_EXYNOS5420
> +	select ARM_CCI
> +	help
> +	  This is needed to provide CPU and cluster power management
> +	  on Exynos5420 implementing big.LITTLE.
> +
>  endif
> diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
> index a656dbe..01bc9b9 100644
> --- a/arch/arm/mach-exynos/Makefile
> +++ b/arch/arm/mach-exynos/Makefile
> @@ -29,3 +29,5 @@ obj-$(CONFIG_ARCH_EXYNOS)	+= firmware.o
>  
>  plus_sec := $(call as-instr,.arch_extension sec,+sec)
>  AFLAGS_exynos-smc.o		:=-Wa,-march=armv7-a$(plus_sec)
> +
> +obj-$(CONFIG_EXYNOS5420_MCPM)	+= mcpm-exynos.o
> diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
> new file mode 100644
> index 0000000..e578007
> --- /dev/null
> +++ b/arch/arm/mach-exynos/mcpm-exynos.c
> @@ -0,0 +1,344 @@
> +/*
> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
> + *		http://www.samsung.com
> + *
> + * arch/arm/mach-exynos/mcpm-exynos.c
> + *
> + * Based on arch/arm/mach-vexpress/dcscb.c
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/arm-cci.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/of_address.h>
> +
> +#include <asm/cputype.h>
> +#include <asm/cp15.h>
> +#include <asm/mcpm.h>
> +
> +#include "regs-pmu.h"
> +#include "common.h"
> +
> +#define EXYNOS5420_CPUS_PER_CLUSTER	4
> +#define EXYNOS5420_NR_CLUSTERS		2
> +
> +/* Non-secure iRAM base address */
> +static void __iomem *ns_sram_base_addr;
> +
> +/*
> + * The common v7_exit_coherency_flush API could not be used because of the
> + * Erratum 799270 workaround. This macro is the same as the common one (in
> + * arch/arm/include/asm/cacheflush.h) except for the erratum handling.
> + */
> +#define exynos_v7_exit_coherency_flush(level) \
> +	asm volatile( \
> +	"stmfd	sp!, {fp, ip}\n\t"\
> +	"mrc	p15, 0, r0, c1, c0, 0	@ get SCTLR\n\t" \
> +	"bic	r0, r0, #"__stringify(CR_C)"\n\t" \
> +	"mcr	p15, 0, r0, c1, c0, 0	@ set SCTLR\n\t" \
> +	"isb\n\t"\
> +	"bl	v7_flush_dcache_"__stringify(level)"\n\t" \
> +	"clrex\n\t"\
> +	"mrc	p15, 0, r0, c1, c0, 1	@ get ACTLR\n\t" \
> +	"bic	r0, r0, #(1 << 6)	@ disable local coherency\n\t" \
> +	/* Dummy Load of a device register to avoid Erratum 799270 */ \
> +	"ldr	r4, [%0]\n\t" \
> +	"and	r4, r4, #0\n\t" \
> +	"orr	r0, r0, r4\n\t" \
> +	"mcr	p15, 0, r0, c1, c0, 1	@ set ACTLR\n\t" \
> +	"isb\n\t" \
> +	"dsb\n\t" \
> +	"ldmfd	sp!, {fp, ip}" \
> +	: \
> +	: "Ir" (S5P_INFORM0) \
> +	: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
> +	  "r9", "r10", "lr", "memory")
> +
> +/*
> + * We can't use regular spinlocks. In the switcher case, it is possible
> + * for an outbound CPU to call power_down() after its inbound counterpart
> + * is already live using the same logical CPU number which trips lockdep
> + * debugging.
> + */
> +static arch_spinlock_t exynos_mcpm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
> +static int
> +cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS];
> +
> +#define exynos_cluster_usecnt(cluster) \
> +	(cpu_use_count[0][cluster] +   \
> +	 cpu_use_count[1][cluster] +   \
> +	 cpu_use_count[2][cluster] +   \
> +	 cpu_use_count[3][cluster])
> +
> +#define exynos_cluster_unused(cluster) !exynos_cluster_usecnt(cluster)
> +
> +static int exynos_cluster_power_control(unsigned int cluster, int enable)
> +{
> +	unsigned int tries = 100;
> +	unsigned int val;
> +
> +	if (enable) {
> +		exynos_cluster_powerup(cluster);
> +		val = S5P_CORE_LOCAL_PWR_EN;
> +	} else {
> +		exynos_cluster_powerdown(cluster);
> +		val = 0;
> +	}
> +
> +	/* Wait until cluster power control is applied */
> +	while (tries--) {
> +		if (exynos_cluster_power_state(cluster) == val)
> +			return 0;
> +
> +		cpu_relax();
> +	}
> +	pr_warn("timed out waiting for cluster %u to power %s\n", cluster,
> +		enable ? "on" : "off");
> +
> +	return -ETIMEDOUT;
> +}
> +
> +static int exynos_power_up(unsigned int cpu, unsigned int cluster)
> +{
> +	unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
> +	int err = 0;
> +
> +	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
> +	if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
> +		cluster >= EXYNOS5420_NR_CLUSTERS)
> +		return -EINVAL;
> +
> +	/*
> +	 * Since this is called with IRQs enabled, and no arch_spin_lock_irq
> +	 * variant exists, we need to disable IRQs manually here.
> +	 */
> +	local_irq_disable();
> +	arch_spin_lock(&exynos_mcpm_lock);
> +
> +	cpu_use_count[cpu][cluster]++;
> +	if (cpu_use_count[cpu][cluster] == 1) {
> +		bool was_cluster_down =
> +			(exynos_cluster_usecnt(cluster) == 1);
> +
> +		/*
> +		 * Turn on the cluster (L2/COMMON) and then power on the
> +		 * cores.
> +		 */
> +		if (was_cluster_down)
> +			err = exynos_cluster_power_control(cluster, 1);
> +
> +		if (!err)
> +			exynos_cpu_powerup(cpunr);
> +		else
> +			exynos_cluster_power_control(cluster, 0);
> +	} else if (cpu_use_count[cpu][cluster] != 2) {
> +		/*
> +		 * The only possible values are:
> +		 * 0 = CPU down
> +		 * 1 = CPU (still) up
> +		 * 2 = CPU requested to be up before it had a chance
> +		 *     to actually make itself down.
> +		 * Any other value is a bug.
> +		 */
> +		BUG();
> +	}
> +
> +	arch_spin_unlock(&exynos_mcpm_lock);
> +	local_irq_enable();
> +
> +	return err;
> +}
> +
> +static void exynos_power_down(void)
> +{
> +	unsigned int mpidr, cpu, cluster;
> +	bool last_man = false, skip_wfi = false;
> +	unsigned int cpunr;
> +
> +	mpidr = read_cpuid_mpidr();
> +	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
> +	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
> +	cpunr =  cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
> +
> +	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
> +	BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
> +			cluster >= EXYNOS5420_NR_CLUSTERS);
> +
> +	__mcpm_cpu_going_down(cpu, cluster);
> +
> +	arch_spin_lock(&exynos_mcpm_lock);
> +	BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
> +	cpu_use_count[cpu][cluster]--;
> +	if (cpu_use_count[cpu][cluster] == 0) {
> +		exynos_cpu_powerdown(cpunr);
> +
> +		if (exynos_cluster_unused(cluster))
> +			/* TODO: Turn off the cluster here to save power. */
> +			last_man = true;
> +	} else if (cpu_use_count[cpu][cluster] == 1) {
> +		/*
> +		 * A power_up request went ahead of us.
> +		 * Even if we do not want to shut this CPU down,
> +		 * the caller expects a certain state as if the WFI
> +		 * was aborted.  So let's continue with cache cleaning.
> +		 */
> +		skip_wfi = true;
> +	} else {
> +		BUG();
> +	}
> +
> +	if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
> +		arch_spin_unlock(&exynos_mcpm_lock);
> +
> +		if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
> +			/*
> +			 * On the Cortex-A15 we need to disable
> +			 * L2 prefetching before flushing the cache.
> +			 */
> +			asm volatile(
> +			"mcr	p15, 1, %0, c15, c0, 3\n\t"
> +			"isb\n\t"
> +			"dsb"
> +			: : "r" (0x400));
> +		}
> +
> +		/* Flush all cache levels for this cluster. */
> +		exynos_v7_exit_coherency_flush(all);
> +
> +		/*
> +		 * Disable cluster-level coherency by masking
> +		 * incoming snoops and DVM messages:
> +		 */
> +		cci_disable_port_by_cpu(mpidr);
> +
> +		__mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
> +	} else {
> +		arch_spin_unlock(&exynos_mcpm_lock);
> +
> +		/* Disable and flush the local CPU cache. */
> +		exynos_v7_exit_coherency_flush(louis);
> +	}
> +
> +	__mcpm_cpu_down(cpu, cluster);
> +
> +	/* Now we are prepared for power-down, do it: */
> +	if (!skip_wfi)
> +		wfi();
> +
> +	/* Not dead at this point?  Let our caller cope. */
> +}
> +
> +static int exynos_power_down_finish(unsigned int cpu, unsigned int cluster)
> +{
> +	unsigned int tries = 100;
> +	unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
> +
> +	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
> +	BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
> +			cluster >= EXYNOS5420_NR_CLUSTERS);
> +
> +	/* Wait for the core state to be OFF */
> +	while (tries--) {
> +		if (ACCESS_ONCE(cpu_use_count[cpu][cluster]) == 0) {
> +			if ((exynos_cpu_power_state(cpunr) == 0))
> +				return 0; /* success: the CPU is halted */
> +		}
> +
> +		/* Otherwise, wait and retry: */
> +		msleep(1);
> +	}
> +
> +	return -ETIMEDOUT; /* timeout */
> +}
> +
> +static const struct mcpm_platform_ops exynos_power_ops = {
> +	.power_up		= exynos_power_up,
> +	.power_down		= exynos_power_down,
> +	.power_down_finish	= exynos_power_down_finish,
> +};
> +
> +static void __init exynos_mcpm_usage_count_init(void)
> +{
> +	unsigned int mpidr, cpu, cluster;
> +
> +	mpidr = read_cpuid_mpidr();
> +	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
> +	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
> +
> +	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
> +	BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER  ||
> +			cluster >= EXYNOS5420_NR_CLUSTERS);
> +
> +	cpu_use_count[cpu][cluster] = 1;
> +}
> +
> +/*
> + * Enable cluster-level coherency, in preparation for turning on the MMU.
> + */
> +static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
> +{
> +	asm volatile ("\n"
> +	"cmp	r0, #1\n"
> +	"bxne	lr\n"
> +	"b	cci_enable_port_for_self");
> +}
> +
> +static int __init exynos_mcpm_init(void)
> +{
> +	struct device_node *node;
> +	int ret = 0;
> +
> +	node = of_find_compatible_node(NULL, NULL, "samsung,exynos5420");
> +	if (!node)
> +		return -ENODEV;
> +	of_node_put(node);
> +
> +	if (!cci_probed())
> +		return -ENODEV;
> +
> +	node = of_find_compatible_node(NULL, NULL,
> +			"samsung,exynos4210-sram-ns");
> +	if (!node)
> +		return -ENODEV;
> +
> +	ns_sram_base_addr = of_iomap(node, 0);
> +	of_node_put(node);
> +	if (!ns_sram_base_addr) {
> +		pr_err("failed to map non-secure iRAM base address\n");
> +		return -ENOMEM;
> +	}
> +
> +	/*
> +	 * To increase the stability of KFC reset we need to program
> +	 * the PMU SPARE3 register
> +	 */
> +	__raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
> +
> +	exynos_mcpm_usage_count_init();
> +
> +	ret = mcpm_platform_register(&exynos_power_ops);
> +	if (!ret)
> +		ret = mcpm_sync_init(exynos_pm_power_up_setup);
> +	if (ret) {
> +		iounmap(ns_sram_base_addr);
> +		return ret;
> +	}
> +
> +	mcpm_smp_set_ops();
> +
> +	pr_info("Exynos MCPM support installed\n");
> +
> +	/*
> +	 * Future entries into the kernel can now go
> +	 * through the cluster entry vectors.
> +	 */
> +	__raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 0x1c);
> +
> +	return ret;
> +}
> +
> +early_initcall(exynos_mcpm_init);
> diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
> index 6685ebf..f44d318 100644
> --- a/arch/arm/mach-exynos/regs-pmu.h
> +++ b/arch/arm/mach-exynos/regs-pmu.h
> @@ -38,6 +38,7 @@
>  #define S5P_INFORM5				S5P_PMUREG(0x0814)
>  #define S5P_INFORM6				S5P_PMUREG(0x0818)
>  #define S5P_INFORM7				S5P_PMUREG(0x081C)
> +#define S5P_PMU_SPARE3				S5P_PMUREG(0x090C)
>  
>  #define S5P_ARM_CORE0_LOWPWR			S5P_PMUREG(0x1000)
>  #define S5P_DIS_IRQ_CORE0			S5P_PMUREG(0x1004)
> @@ -325,4 +326,6 @@
>  
>  #define EXYNOS5_OPTION_USE_RETENTION				(1 << 4)
>  
> +#define EXYNOS5420_SWRESET_KFC_SEL				0x3
> +
>  #endif /* __ASM_ARCH_REGS_PMU_H */
> -- 
> 1.7.9.5
> 

RE: [PATCH v5 1/5] ARM: EXYNOS: Add generic cpu power control functions for all exynos based SoCs

[Kukjin Kim]

Abhilash Kesavan wrote:
> 
+ Jonghwan Choi, Seungkon Hwang

> From: Leela Krishna Amudala <leela.krishna@linaro.org>
> 
> Add generic cpu power control functions for exynos based SoCS
> for cpu power up/down and to know the cpu status.
> 
> Signed-off-by: Leela Krishna Amudala <leela.krishna@linaro.org>

In this case, Abhilash's signed-off-by should be added here.

> ---
>  arch/arm/mach-exynos/common.h   |    3 +++
>  arch/arm/mach-exynos/pm.c       |   36
++++++++++++++++++++++++++++++++++++
>  arch/arm/mach-exynos/regs-pmu.h |    6 ++++++
>  3 files changed, 45 insertions(+)
> 
> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
> index 47cbab0..a7dbb5f 100644
> --- a/arch/arm/mach-exynos/common.h
> +++ b/arch/arm/mach-exynos/common.h
> @@ -63,5 +63,8 @@ struct exynos_pmu_conf {
>  };
> 
>  extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
> +extern void exynos_cpu_powerdown(int cpu);

IMO, using 'xxx_power_down' would be better.

> +extern void exynos_cpu_powerup(int cpu);
> +extern int  exynos_cpu_power_state(int cpu);

Hmm...is it really 'cpu' related? Or 'core' related? As I know, when the
function is called, ARM core and L1 cache will be power_up/down except L2
cache...But I have no strong objection to use 'cpu' here

> 
>  #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
> diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
> index 15af0ce..6651028 100644
> --- a/arch/arm/mach-exynos/pm.c
> +++ b/arch/arm/mach-exynos/pm.c
> @@ -100,6 +100,42 @@ static int exynos_irq_set_wake(struct irq_data *data,
> unsigned int state)
>  	return -ENOENT;
>  }
> 
> +/**
> + * exynos_cpu_powerdown : power down the specified cpu
> + * @cpu : the cpu to power down
> + *
> + * Power downs the specified cpu. The sequence must be finished by a
> + * call to cpu_do_idle()
> + *
> + */
> +void exynos_cpu_powerdown(int cpu)
> +{
> +	__raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
> +}
> +
> +/**
> + * exynos_cpu_powerup : power up the specified cpu
> + * @cpu : the cpu to power up
> + *
> + * Power up the specified cpu
> + */
> +void exynos_cpu_powerup(int cpu)
> +{
> +	__raw_writel(S5P_CORE_LOCAL_PWR_EN,
> +		     EXYNOS_ARM_CORE_CONFIGURATION(cpu));
> +}
> +
> +/**
> + * exynos_cpu_power_state : returns the power state of the cpu
> + * @cpu : the cpu to retrieve the power state from
> + *
> + */
> +int exynos_cpu_power_state(int cpu)
> +{
> +	return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
> +			S5P_CORE_LOCAL_PWR_EN);
> +}
> +
>  /* For Cortex-A9 Diagnostic and Power control register */
>  static unsigned int save_arm_register[2];
> 
> diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-
> pmu.h
> index 4f6a256..0bdfcbc 100644
> --- a/arch/arm/mach-exynos/regs-pmu.h
> +++ b/arch/arm/mach-exynos/regs-pmu.h
> @@ -121,6 +121,12 @@
> 
>  #define S5P_CHECK_SLEEP				0x00000BAD
> 
> +#define EXYNOS_ARM_CORE0_CONFIGURATION		S5P_PMUREG(0x2000)

This can be put in order of address.

> +#define EXYNOS_ARM_CORE_CONFIGURATION(_nr)	\
> +			(EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
> +#define EXYNOS_ARM_CORE_STATUS(_nr)		\
> +			(EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)

Can you please cleanup codes following definitions are used with using above
definitions?

S5P_ARM_CORE1_CONFIGURATION and S5P_ARM_CORE1_STATUS in hotplug.c and
platsmp.c 

> +
>  /* Only for EXYNOS4210 */
>  #define S5P_CMU_CLKSTOP_LCD1_LOWPWR	S5P_PMUREG(0x1154)
>  #define S5P_CMU_RESET_LCD1_LOWPWR	S5P_PMUREG(0x1174)
> --
> 1.7.9.5

RE: [PATCH v5 2/5] ARM: EXYNOS: use generic exynos cpu power control functions

[Kukjin Kim]

Abhilash Kesavan wrote:
> 
> From: Leela Krishna Amudala <leela.krishna@linaro.org>
> 
> Use generic exynos cpu power control functions to power up/down
> and to know the status of the cpu.
> 
> Signed-off-by: Leela Krishna Amudala <leela.krishna@linaro.org>

Same as previous comment.

> ---
>  arch/arm/mach-exynos/platsmp.c |    9 +++------
>  1 file changed, 3 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-
> exynos/platsmp.c
> index 0aac032..d442a66 100644
> --- a/arch/arm/mach-exynos/platsmp.c
> +++ b/arch/arm/mach-exynos/platsmp.c
> @@ -130,15 +130,12 @@ static int exynos_boot_secondary(unsigned int cpu,
> struct task_struct *idle)
>  	 */
>  	write_pen_release(phys_cpu);
> 
> -	if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
> -		__raw_writel(S5P_CORE_LOCAL_PWR_EN,
> -			     S5P_ARM_CORE1_CONFIGURATION);
> -
> +	if (!exynos_cpu_power_state(cpu)) {
> +		exynos_cpu_powerup(cpu);
>  		timeout = 10;
> 
>  		/* wait max 10 ms until cpu1 is on */
> -		while ((__raw_readl(S5P_ARM_CORE1_STATUS)
> -			& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
> +		while (exynos_cpu_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN)
> {
>  			if (timeout-- == 0)
>  				break;
> 
> --

You may cleanup the definitions of 'S5P_ARM_CORE1_CONFIGURATION/STATUS' in
regs-pmu.h once hotplug.c uses the generic power control functions.

- Kukjin

Re: [PATCH v5 1/5] ARM: EXYNOS: Add generic cpu power control functions for all exynos based SoCs

[Abhilash Kesavan]

Hi Kukjin,

On Tue, May 13, 2014 at 7:54 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Abhilash Kesavan wrote:
>>
> + Jonghwan Choi, Seungkon Hwang
>
>> From: Leela Krishna Amudala <leela.krishna@linaro.org>
>>
>> Add generic cpu power control functions for exynos based SoCS
>> for cpu power up/down and to know the cpu status.
>>
>> Signed-off-by: Leela Krishna Amudala <leela.krishna@linaro.org>
>
> In this case, Abhilash's signed-off-by should be added here.
Will add.
>
>> ---
>>  arch/arm/mach-exynos/common.h   |    3 +++
>>  arch/arm/mach-exynos/pm.c       |   36
> ++++++++++++++++++++++++++++++++++++
>>  arch/arm/mach-exynos/regs-pmu.h |    6 ++++++
>>  3 files changed, 45 insertions(+)
>>
>> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
>> index 47cbab0..a7dbb5f 100644
>> --- a/arch/arm/mach-exynos/common.h
>> +++ b/arch/arm/mach-exynos/common.h
>> @@ -63,5 +63,8 @@ struct exynos_pmu_conf {
>>  };
>>
>>  extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
>> +extern void exynos_cpu_powerdown(int cpu);
>
> IMO, using 'xxx_power_down' would be better.
Will change.
>
>> +extern void exynos_cpu_powerup(int cpu);
>> +extern int  exynos_cpu_power_state(int cpu);
>
> Hmm...is it really 'cpu' related? Or 'core' related? As I know, when the
> function is called, ARM core and L1 cache will be power_up/down except L2
> cache...But I have no strong objection to use 'cpu' here
OK, I am keeping cpu as it is then.
>
>>
>>  #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
>> diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
>> index 15af0ce..6651028 100644
>> --- a/arch/arm/mach-exynos/pm.c
>> +++ b/arch/arm/mach-exynos/pm.c
>> @@ -100,6 +100,42 @@ static int exynos_irq_set_wake(struct irq_data *data,
>> unsigned int state)
>>       return -ENOENT;
>>  }
>>
>> +/**
>> + * exynos_cpu_powerdown : power down the specified cpu
>> + * @cpu : the cpu to power down
>> + *
>> + * Power downs the specified cpu. The sequence must be finished by a
>> + * call to cpu_do_idle()
>> + *
>> + */
>> +void exynos_cpu_powerdown(int cpu)
>> +{
>> +     __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
>> +}
>> +
>> +/**
>> + * exynos_cpu_powerup : power up the specified cpu
>> + * @cpu : the cpu to power up
>> + *
>> + * Power up the specified cpu
>> + */
>> +void exynos_cpu_powerup(int cpu)
>> +{
>> +     __raw_writel(S5P_CORE_LOCAL_PWR_EN,
>> +                  EXYNOS_ARM_CORE_CONFIGURATION(cpu));
>> +}
>> +
>> +/**
>> + * exynos_cpu_power_state : returns the power state of the cpu
>> + * @cpu : the cpu to retrieve the power state from
>> + *
>> + */
>> +int exynos_cpu_power_state(int cpu)
>> +{
>> +     return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
>> +                     S5P_CORE_LOCAL_PWR_EN);
>> +}
>> +
>>  /* For Cortex-A9 Diagnostic and Power control register */
>>  static unsigned int save_arm_register[2];
>>
>> diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-
>> pmu.h
>> index 4f6a256..0bdfcbc 100644
>> --- a/arch/arm/mach-exynos/regs-pmu.h
>> +++ b/arch/arm/mach-exynos/regs-pmu.h
>> @@ -121,6 +121,12 @@
>>
>>  #define S5P_CHECK_SLEEP                              0x00000BAD
>>
>> +#define EXYNOS_ARM_CORE0_CONFIGURATION               S5P_PMUREG(0x2000)
>
> This can be put in order of address.
OK, will fix.
>
>> +#define EXYNOS_ARM_CORE_CONFIGURATION(_nr)   \
>> +                     (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
>> +#define EXYNOS_ARM_CORE_STATUS(_nr)          \
>> +                     (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
>
> Can you please cleanup codes following definitions are used with using above
> definitions?
>
> S5P_ARM_CORE1_CONFIGURATION and S5P_ARM_CORE1_STATUS in hotplug.c and
> platsmp.c
Will remove these.

Regards,
Abhilash
>
>> +
>>  /* Only for EXYNOS4210 */
>>  #define S5P_CMU_CLKSTOP_LCD1_LOWPWR  S5P_PMUREG(0x1154)
>>  #define S5P_CMU_RESET_LCD1_LOWPWR    S5P_PMUREG(0x1174)
>> --
>> 1.7.9.5
>

Re: [PATCH v5 2/5] ARM: EXYNOS: use generic exynos cpu power control functions

[Abhilash Kesavan]

Hi Kukjin,

On Tue, May 13, 2014 at 7:58 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Abhilash Kesavan wrote:
>>
>> From: Leela Krishna Amudala <leela.krishna@linaro.org>
>>
>> Use generic exynos cpu power control functions to power up/down
>> and to know the status of the cpu.
>>
>> Signed-off-by: Leela Krishna Amudala <leela.krishna@linaro.org>
>
> Same as previous comment.
>
>> ---
>>  arch/arm/mach-exynos/platsmp.c |    9 +++------
>>  1 file changed, 3 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-
>> exynos/platsmp.c
>> index 0aac032..d442a66 100644
>> --- a/arch/arm/mach-exynos/platsmp.c
>> +++ b/arch/arm/mach-exynos/platsmp.c
>> @@ -130,15 +130,12 @@ static int exynos_boot_secondary(unsigned int cpu,
>> struct task_struct *idle)
>>        */
>>       write_pen_release(phys_cpu);
>>
>> -     if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
>> -             __raw_writel(S5P_CORE_LOCAL_PWR_EN,
>> -                          S5P_ARM_CORE1_CONFIGURATION);
>> -
>> +     if (!exynos_cpu_power_state(cpu)) {
>> +             exynos_cpu_powerup(cpu);
>>               timeout = 10;
>>
>>               /* wait max 10 ms until cpu1 is on */
>> -             while ((__raw_readl(S5P_ARM_CORE1_STATUS)
>> -                     & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
>> +             while (exynos_cpu_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN)
>> {
>>                       if (timeout-- == 0)
>>                               break;
>>
>> --
>
> You may cleanup the definitions of 'S5P_ARM_CORE1_CONFIGURATION/STATUS' in
> regs-pmu.h once hotplug.c uses the generic power control functions.
OK, will re-post a new version rebased on your for-next branch soon.

Regards,
Abhilash
>
> - Kukjin
>

Re: [PATCH v5 1/5] ARM: EXYNOS: Add generic cpu power control functions for all exynos based SoCs

[Tomasz Figa]

Hi Abhilash,

On 13.05.2014 12:12, Abhilash Kesavan wrote:
> On Tue, May 13, 2014 at 7:54 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:

[snip]

>>> diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-
>>> pmu.h
>>> index 4f6a256..0bdfcbc 100644
>>> --- a/arch/arm/mach-exynos/regs-pmu.h
>>> +++ b/arch/arm/mach-exynos/regs-pmu.h
>>> @@ -121,6 +121,12 @@
>>>
>>>  #define S5P_CHECK_SLEEP                              0x00000BAD
>>>
>>> +#define EXYNOS_ARM_CORE0_CONFIGURATION               S5P_PMUREG(0x2000)
>>
>> This can be put in order of address.
> OK, will fix.
>>
>>> +#define EXYNOS_ARM_CORE_CONFIGURATION(_nr)   \
>>> +                     (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
>>> +#define EXYNOS_ARM_CORE_STATUS(_nr)          \
>>> +                     (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)

My patches posted quite a while ago [1] to fix DT CPU topology already
add these, remove S5P_ARM_CORE1* and fix corresponding usage in
hotplug.c and platsmp.c.

[1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/29573

So I think you should rebase on top of them or at least on top of
patches 1 and 2 from that series, as 3 and 4 should be dropped.

Best regards,
Tomasz

Re: [PATCH v5 1/5] ARM: EXYNOS: Add generic cpu power control functions for all exynos based SoCs

[Abhilash Kesavan]

Hi Tomasz,

On Fri, May 16, 2014 at 2:41 AM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Hi Abhilash,
>
> On 13.05.2014 12:12, Abhilash Kesavan wrote:
>> On Tue, May 13, 2014 at 7:54 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
>
> [snip]
>
>>>> diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-
>>>> pmu.h
>>>> index 4f6a256..0bdfcbc 100644
>>>> --- a/arch/arm/mach-exynos/regs-pmu.h
>>>> +++ b/arch/arm/mach-exynos/regs-pmu.h
>>>> @@ -121,6 +121,12 @@
>>>>
>>>>  #define S5P_CHECK_SLEEP                              0x00000BAD
>>>>
>>>> +#define EXYNOS_ARM_CORE0_CONFIGURATION               S5P_PMUREG(0x2000)
>>>
>>> This can be put in order of address.
>> OK, will fix.
>>>
>>>> +#define EXYNOS_ARM_CORE_CONFIGURATION(_nr)   \
>>>> +                     (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
>>>> +#define EXYNOS_ARM_CORE_STATUS(_nr)          \
>>>> +                     (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
>
> My patches posted quite a while ago [1] to fix DT CPU topology already
> add these, remove S5P_ARM_CORE1* and fix corresponding usage in
> hotplug.c and platsmp.c.
>
> [1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/29573
>
> So I think you should rebase on top of them or at least on top of
> patches 1 and 2 from that series, as 3 and 4 should be dropped.

Patch 2 of your series does not apply on kgene's for-next or
linux-next. Are you planning on re-sending this ?

Regards,
Abhilash
>
> Best regards,
> Tomasz

Re: [PATCH v5 1/5] ARM: EXYNOS: Add generic cpu power control functions for all exynos based SoCs

[Tomasz Figa]

On 16.05.2014 07:07, Abhilash Kesavan wrote:
> Hi Tomasz,
> 
> On Fri, May 16, 2014 at 2:41 AM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
>> Hi Abhilash,
>>
>> On 13.05.2014 12:12, Abhilash Kesavan wrote:
>>> On Tue, May 13, 2014 at 7:54 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
>>
>> [snip]
>>
>>>>> diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-
>>>>> pmu.h
>>>>> index 4f6a256..0bdfcbc 100644
>>>>> --- a/arch/arm/mach-exynos/regs-pmu.h
>>>>> +++ b/arch/arm/mach-exynos/regs-pmu.h
>>>>> @@ -121,6 +121,12 @@
>>>>>
>>>>>  #define S5P_CHECK_SLEEP                              0x00000BAD
>>>>>
>>>>> +#define EXYNOS_ARM_CORE0_CONFIGURATION               S5P_PMUREG(0x2000)
>>>>
>>>> This can be put in order of address.
>>> OK, will fix.
>>>>
>>>>> +#define EXYNOS_ARM_CORE_CONFIGURATION(_nr)   \
>>>>> +                     (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
>>>>> +#define EXYNOS_ARM_CORE_STATUS(_nr)          \
>>>>> +                     (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
>>
>> My patches posted quite a while ago [1] to fix DT CPU topology already
>> add these, remove S5P_ARM_CORE1* and fix corresponding usage in
>> hotplug.c and platsmp.c.
>>
>> [1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/29573
>>
>> So I think you should rebase on top of them or at least on top of
>> patches 1 and 2 from that series, as 3 and 4 should be dropped.
> 
> Patch 2 of your series does not apply on kgene's for-next or
> linux-next. Are you planning on re-sending this ?

OK, it seems like Kukjin has already applied your v6 series, so let's
drop my series for now. I'll remove patch 1 from my series and rebase it
on top of your v6.

Best regards,
Tomasz

Re: [PATCH v5 1/5] ARM: EXYNOS: Add generic cpu power control functions for all exynos based SoCs

[Abhilash Kesavan]

Hi Tomasz,

On Sat, May 17, 2014 at 6:02 AM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
>
>
> On 16.05.2014 07:07, Abhilash Kesavan wrote:
>> Hi Tomasz,
>>
>> On Fri, May 16, 2014 at 2:41 AM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
>>> Hi Abhilash,
>>>
>>> On 13.05.2014 12:12, Abhilash Kesavan wrote:
>>>> On Tue, May 13, 2014 at 7:54 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
>>>
>>> [snip]
>>>
>>>>>> diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-
>>>>>> pmu.h
>>>>>> index 4f6a256..0bdfcbc 100644
>>>>>> --- a/arch/arm/mach-exynos/regs-pmu.h
>>>>>> +++ b/arch/arm/mach-exynos/regs-pmu.h
>>>>>> @@ -121,6 +121,12 @@
>>>>>>
>>>>>>  #define S5P_CHECK_SLEEP                              0x00000BAD
>>>>>>
>>>>>> +#define EXYNOS_ARM_CORE0_CONFIGURATION               S5P_PMUREG(0x2000)
>>>>>
>>>>> This can be put in order of address.
>>>> OK, will fix.
>>>>>
>>>>>> +#define EXYNOS_ARM_CORE_CONFIGURATION(_nr)   \
>>>>>> +                     (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
>>>>>> +#define EXYNOS_ARM_CORE_STATUS(_nr)          \
>>>>>> +                     (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
>>>
>>> My patches posted quite a while ago [1] to fix DT CPU topology already
>>> add these, remove S5P_ARM_CORE1* and fix corresponding usage in
>>> hotplug.c and platsmp.c.
>>>
>>> [1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/29573
>>>
>>> So I think you should rebase on top of them or at least on top of
>>> patches 1 and 2 from that series, as 3 and 4 should be dropped.
>>
>> Patch 2 of your series does not apply on kgene's for-next or
>> linux-next. Are you planning on re-sending this ?
>
> OK, it seems like Kukjin has already applied your v6 series, so let's
> drop my series for now. I'll remove patch 1 from my series and rebase it
> on top of your v6.
Ok, thanks.

Regards,
Abhilash
>
> Best regards,
> Tomasz

Re: [PATCH v5 5/5] arm: exynos: Add MCPM call-back functions

[Arnd Bergmann]

On Monday 05 May 2014, Abhilash Kesavan wrote:
> +static const struct mcpm_platform_ops exynos_power_ops = {
> +       .power_up               = exynos_power_up,
> +       .power_down             = exynos_power_down,
> +       .power_down_finish      = exynos_power_down_finish,
> +};


I'm getting a build error in linux-next because there is no .power_down_finish
member in mcpm_platform_ops here.

	Arnd

RE: [PATCH v5 5/5] arm: exynos: Add MCPM call-back functions

[Kukjin Kim]

Arnd Bergmann wrote:
> 
> On Monday 05 May 2014, Abhilash Kesavan wrote:
> > +static const struct mcpm_platform_ops exynos_power_ops = {
> > +       .power_up               = exynos_power_up,
> > +       .power_down             = exynos_power_down,
> > +       .power_down_finish      = exynos_power_down_finish,
> > +};
> 
> 
> I'm getting a build error in linux-next because there is
> no .power_down_finish
> member in mcpm_platform_ops here.
> 
Yeah, commit 166aaf39 ("ARM: 8029/1: mcpm: Rename the power_down_finish()
functions to be less confusing") changed the name to
wait_for_cpu_powerdown...

So need to change it accordingly...

diff --git a/arch/arm/mach-exynos/mcpm-exynos.c
b/arch/arm/mach-exynos/mcpm-exynos.c
index 1ac618c..34c4e6f 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -235,7 +235,7 @@ static void exynos_power_down(void)
 	/* Not dead at this point?  Let our caller cope. */
 }
 
-static int exynos_power_down_finish(unsigned int cpu, unsigned int cluster)
+static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int
cluster)
 {
 	unsigned int tries = 100;
 	unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
@@ -261,7 +261,7 @@ static int exynos_power_down_finish(unsigned int cpu,
unsigned int cluster)
 static const struct mcpm_platform_ops exynos_power_ops = {
 	.power_up		= exynos_power_up,
 	.power_down		= exynos_power_down,
-	.power_down_finish	= exynos_power_down_finish,
+	.wait_for_powerdown	= exynos_wait_for_powerdown,
 };
 
 static void __init exynos_mcpm_usage_count_init(void)

Thanks,
Kukjin

Re: [PATCH v5 5/5] arm: exynos: Add MCPM call-back functions

[Abhilash Kesavan]

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Hi Kukjin and Arnd,

On Tue, May 27, 2014 at 5:09 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:

> Arnd Bergmann wrote:
> >
> > On Monday 05 May 2014, Abhilash Kesavan wrote:
> > > +static const struct mcpm_platform_ops exynos_power_ops = {
> > > +       .power_up               = exynos_power_up,
> > > +       .power_down             = exynos_power_down,
> > > +       .power_down_finish      = exynos_power_down_finish,
> > > +};
> >
> >
> > I'm getting a build error in linux-next because there is
> > no .power_down_finish
> > member in mcpm_platform_ops here.
> >
> Yeah, commit 166aaf39 ("ARM: 8029/1: mcpm: Rename the power_down_finish()
> functions to be less confusing") changed the name to
> wait_for_cpu_powerdown...
>
> So need to change it accordingly...
>
> diff --git a/arch/arm/mach-exynos/mcpm-exynos.c
> b/arch/arm/mach-exynos/mcpm-exynos.c
> index 1ac618c..34c4e6f 100644
> --- a/arch/arm/mach-exynos/mcpm-exynos.c
> +++ b/arch/arm/mach-exynos/mcpm-exynos.c
> @@ -235,7 +235,7 @@ static void exynos_power_down(void)
>         /* Not dead at this point?  Let our caller cope. */
>  }
>
> -static int exynos_power_down_finish(unsigned int cpu, unsigned int
> cluster)
> +static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int
> cluster)
>  {
>         unsigned int tries = 100;
>         unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
> @@ -261,7 +261,7 @@ static int exynos_power_down_finish(unsigned int cpu,
> unsigned int cluster)
>  static const struct mcpm_platform_ops exynos_power_ops = {
>         .power_up               = exynos_power_up,
>         .power_down             = exynos_power_down,
> -       .power_down_finish      = exynos_power_down_finish,
> +       .wait_for_powerdown     = exynos_wait_for_powerdown,
>  };
>
>  static void __init exynos_mcpm_usage_count_init(void)
>

The above change seems fine. Will this be directly applied or do I need to
send out a patch ?

Regards,
Abhilash

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Re: [PATCH v5 5/5] arm: exynos: Add MCPM call-back functions

[Kukjin Kim]

On 05/27/14 20:39, Kukjin Kim wrote:
> Arnd Bergmann wrote:
>>
>> On Monday 05 May 2014, Abhilash Kesavan wrote:
>>> +static const struct mcpm_platform_ops exynos_power_ops = {
>>> +       .power_up               = exynos_power_up,
>>> +       .power_down             = exynos_power_down,
>>> +       .power_down_finish      = exynos_power_down_finish,
>>> +};
>>
>>
>> I'm getting a build error in linux-next because there is
>> no .power_down_finish
>> member in mcpm_platform_ops here.
>>
> Yeah, commit 166aaf39 ("ARM: 8029/1: mcpm: Rename the power_down_finish()
> functions to be less confusing") changed the name to
> wait_for_cpu_powerdown...
>
> So need to change it accordingly...
>
> diff --git a/arch/arm/mach-exynos/mcpm-exynos.c
> b/arch/arm/mach-exynos/mcpm-exynos.c
> index 1ac618c..34c4e6f 100644
> --- a/arch/arm/mach-exynos/mcpm-exynos.c
> +++ b/arch/arm/mach-exynos/mcpm-exynos.c
> @@ -235,7 +235,7 @@ static void exynos_power_down(void)
>   	/* Not dead at this point?  Let our caller cope. */
>   }
>
> -static int exynos_power_down_finish(unsigned int cpu, unsigned int cluster)
> +static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int
> cluster)
>   {
>   	unsigned int tries = 100;
>   	unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
> @@ -261,7 +261,7 @@ static int exynos_power_down_finish(unsigned int cpu,
> unsigned int cluster)
>   static const struct mcpm_platform_ops exynos_power_ops = {
>   	.power_up		= exynos_power_up,
>   	.power_down		= exynos_power_down,
> -	.power_down_finish	= exynos_power_down_finish,
> +	.wait_for_powerdown	= exynos_wait_for_powerdown,
>   };
>
>   static void __init exynos_mcpm_usage_count_init(void)
>
Arnd,

Fixed with above patch.
So I hope it should be fine with tomorrow -next tree.

Thanks,
Kukjin