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AJvYcCVpV3yeTkTg6Gsb5eLo45BmrFkCt+BhZdDJ5y3UiguMXSCgkhAkR5mJyaqksjqp8ZzZEVVH2LWd0uwQ@vger.kernel.org X-Gm-Message-State: AOJu0Yzq2+mrxWzJuV3F/wCeXZzimLejVcMhkgf/hUXGonX4bvgFxrVa LyLdLa/o283hEoLAfgktr4LcnASbLJDvWywIjtnMytM8z8bsTrOYUH9tzUnX+/1PnJ52AbsjzVa mg95+6IMpHciUjPaPEUx7609ZFBJGsCVGr1yFC9Ziaw== X-Gm-Gg: ASbGncviCBQ+ee8A1WUtSPjwt1mTHzICTV2/EJkSp4T6wb3r/mAxVR9ApHWs5327o1A 3u5M6H5Tz0EAgM8OcTAmF91vzBkHK3zjuyg2IDpCpvUUR8eyhgxQb6ClQA0EizgyoUX37ZE+J7t dLdf9V2bXea/4vNvaXE6s4dpeNutDL7Ls6FJxcTobVh/V1RGfKX7gpRgo9Oo0R6Y8= X-Google-Smtp-Source: AGHT+IG+4ruICaQP9WjnJtvSTT9EmK06oaor1STRsfEcgxfGLSMohUV22g53UcbTlMgO8PAYrxi/zYRyt6cxM4CKTj0= X-Received: by 2002:a05:6512:3a89:b0:553:2ce6:c749 with SMTP id 2adb3069b0e04-55342f5f525mr4032820e87.24.1748957728189; Tue, 03 Jun 2025 06:35:28 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250530-apr_14_for_sending-v3-0-83d5744d997c@samsung.com> <20250530-apr_14_for_sending-v3-1-83d5744d997c@samsung.com> <4519844e-b1c0-40a7-b856-a6e4a80c6334@samsung.com> <20250603-cuddly-certain-mussel-4fbe96@kuoka> In-Reply-To: <20250603-cuddly-certain-mussel-4fbe96@kuoka> From: Bartosz Golaszewski Date: Tue, 3 Jun 2025 15:35:16 +0200 X-Gm-Features: AX0GCFuDYKD0oEvnMgBkM50gIAPDgZLFL7Iyce01c_hFdppjyHLpA9k0Aap5-Uk Message-ID: Subject: Re: [PATCH v3 1/8] dt-bindings: power: Add T-HEAD TH1520 GPU power sequencer To: Krzysztof Kozlowski Cc: Michal Wilczynski , Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Jun 3, 2025 at 3:19=E2=80=AFPM Krzysztof Kozlowski wrote: > > On Mon, Jun 02, 2025 at 10:29:13PM GMT, Michal Wilczynski wrote: > > >> +description: | > > >> + This binding describes the power sequencer for the T-HEAD TH1520 = GPU. > > >> + This sequencer handles the specific power-up and power-down seque= nces > > >> + required by the GPU, including managing clocks and resets from bo= th the > > >> + sequencer and the GPU device itself. > > >> + > > >> +properties: > > >> + compatible: > > >> + const: thead,th1520-gpu-pwrseq > > >> + > > > > > > Before I review the rest: is this actually a physical device that > > > takes care of the power sequencing? Some kind of a power management > > > unit for the GPU? If so, I bet it's not called "power sequencer" so > > > let's use its actual name as per the datasheet? > > > > Hi Bart, > > Thanks for your feedback. > > > > The hardware block responsible for powering up the components in the > > TH1520 SoC datasheet is called AON (Always On). However, we already hav= e > > a DT node named aon that serves as a power domain provider > > (Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml). > > So no. One device, one device node (sometimes with cildren nodes). You > do not get another device node just because someone wrote incomplete > binding or because driver looks differently. > > > > > Following the discussion [1] about needing a separate DT node for the > > power sequencing capabilities of this AON block, and thinking further > > about it, I think the binding should be more generic. The AON block can > > manage power sequences for more than just the GPU (e.g. NPU, AUDIO, > > DSP). > > > > The compatible string could be updated like so: > > "thead,th1520-aon-pwrseq" > > Should not be separate node, you already have one for AON. > Agreed. And as far as implementation goes, you can have the same driver be a PM domain AND pwrseq provider. It just has to bind to the device node that represents an actual component, not a made-up "convenience" node. Bartosz