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AJvYcCWzZOdvmafsmLDZezHZY4gaSOiA1RK7n0YA16dOsMrDJH1CZJLjx/+ByvTjZxbO3ufkM69UJhJL6xXInMkAmeHpOGgpmmpQI1KajA== X-Gm-Message-State: AOJu0YxXSDcpZCitS35GFdERIZ2LdJMwHgC4p2Pya/QIrSBvr9qA1nbK TIsndQr9Nd7N+wY/BfJ25TXf4NKft98Dj6Iyj0gJEEn+nZ+Hqec2D4AWvMvxvFXwycrTpXfEARN +9Vf5ee3t1gu99BP/EXOlMnyryc6uxnX81KcIoA== X-Google-Smtp-Source: AGHT+IHnz+jiST2ObwGwpRhNGzS4fV2cd2JpTXgrhQgW5flC1P8gqI9c+i+tCJ6lqjrnPn65ZSzmomPtcHF6WLtuRP0= X-Received: by 2002:a50:c054:0:b0:57d:669:cafb with SMTP id 4fb4d7f45d1cf-57d70075c73mr1867346a12.40.1719310648918; Tue, 25 Jun 2024 03:17:28 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240605-atrium-neuron-c2512b34d3da@spud> <40a7d568-3855-48fb-a73c-339e1790f12f@ghiti.fr> <20240621-viewless-mural-f5992a247992@wendy> <20240621-9bf9365533a2f8f97cbf1f5e@orel> <20240621-glutton-platonic-2ec41021b81b@spud> <20240621-a56e848050ebbf1f7394e51f@orel> <20240621-surging-flounder-58a653747e1d@spud> <20240621-8422c24612ae40600f349f7c@orel> <20240622-stride-unworn-6e3270a326e5@spud> In-Reply-To: <20240622-stride-unworn-6e3270a326e5@spud> From: Yong-Xuan Wang Date: Tue, 25 Jun 2024 18:17:16 +0800 Message-ID: Subject: Re: [PATCH v5 2/4] dt-bindings: riscv: Add Svade and Svadu Entries To: Conor Dooley Cc: Andrew Jones , Alexandre Ghiti , Conor Dooley , Anup Patel , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, greentime.hu@sifive.com, vincent.chen@sifive.com, Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , devicetree@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Conor, On Sat, Jun 22, 2024 at 8:01=E2=80=AFPM Conor Dooley wro= te: > > On Fri, Jun 21, 2024 at 05:08:01PM +0200, Andrew Jones wrote: > > On Fri, Jun 21, 2024 at 03:58:18PM GMT, Conor Dooley wrote: > > > On Fri, Jun 21, 2024 at 04:52:09PM +0200, Andrew Jones wrote: > > > > On Fri, Jun 21, 2024 at 03:04:47PM GMT, Conor Dooley wrote: > > > > > On Fri, Jun 21, 2024 at 03:15:10PM +0200, Andrew Jones wrote: > > > > > > On Fri, Jun 21, 2024 at 02:42:15PM GMT, Alexandre Ghiti wrote: > > > > > > > > > I understand the concern; old SBI implementations will leave sv= adu in the > > > > > > DT but not actually enable it. Then, since svade may not be in = the DT if > > > > > > the platform doesn't support it or it was left out on purpose, = Linux will > > > > > > only see svadu and get unexpected exceptions. This is something= we could > > > > > > force easily with QEMU and an SBI implementation which doesn't = do anything > > > > > > for svadu. I hope vendors of real platforms, which typically pr= ovide their > > > > > > own firmware and DTs, would get this right, though, especially = since Linux > > > > > > should fail fast in their testing when they get it wrong. > > > > > > > > > > I'll admit, I wasn't really thinking here about something like QE= MU that > > > > > puts extensions into the dtb before their exact meanings are deci= ded > > > > > upon. I almost only ever think about "real" systems, and in those= cases > > > > > I would expect that if you can update the representation of the h= ardware > > > > > provided to (or by the firmware to Linux) with new properties, th= en updating > > > > > the firmware itself should be possible. > > > > > > > > > > Does QEMU have the this exact problem at the moment? I know it pu= ts > > > > > Svadu in the max cpu, but does it enable the behaviour by default= , even > > > > > without the SBI implementation asking for it? > > > > > > > > Yes, because QEMU has done hardware A/D updating since it first sta= rted > > > > supporting riscv, which means it did svadu when neither svadu nor s= vade > > > > were in the DT. The "fix" for that was to ensure we have svadu and = !svade > > > > by default, which means we've perfectly realized Alexandre's concer= n... > > > > We should be able to change the named cpu types that don't support = svadu > > > > to only have svade in their DTs, since that would actually be fixin= g those > > > > cpu types, but we'll need to discuss how to proceed with the generi= c cpu > > > > types like 'max'. > > > > > > Correct me please, since I think I am misunderstanding: At the moment > > > QEMU does A/D updating whether or not the SBI implantation asks for i= t, > > > with the max CPU. The SBI implementation doesn't understand Svadu and > > > won't strip it. The kernel will get a DT with Svadu in it, but Svadu = will > > > be enabled, so it is not a problem. > > > > Oh, of course you're right! I managed to reverse things some odd number= of > > times (more than once!) in my head and ended up backwards... > > I mean, I've been really confused about this whole thing the entire > time, so ye.. > > Speaking of QEMU, what happens if I try to turn on svade and svadu in > QEMU? It looks like there's some handling of it that does things > conditionally based !svade && svade, but I couldn't tell if it would do > what we are describing in this thread. When both Svadu and Svade are specified in QEMU, the reset value of menvcfg.ADUE is 0: env->menvcfg =3D (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | (!cpu->cfg.ext_svade && cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0); The runtime behavior depends on menvcfg.ADUE: bool svade =3D riscv_cpu_cfg(env)->ext_svade; bool svadu =3D riscv_cpu_cfg(env)->ext_svadu; bool adue =3D svadu ? env->menvcfg & MENVCFG_ADUE : !svade; Regardless of whether OpenSBI supports the Svadu enablement, Supervisor can assume that QEMU uses Svade when it doesn't explicitly turn on Svadu. Regards, Yong-Xuan