From: Zhangfei Gao <zhangfei.gao@gmail.com>
To: Seungwon Jeon <tgih.jun@samsung.com>
Cc: Zhangfei Gao <zhangfei.gao@linaro.org>,
Chris Ball <cjb@laptop.org>, Arnd Bergmann <arnd@arndb.de>,
Mike Turquette <mturquette@linaro.org>,
Jaehoon Chung <jh80.chung@samsung.com>,
Haojian Zhuang <haojian.zhuang@linaro.org>,
Zhigang Wang <brooke.wangzhigang@huawei.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
patches@linaro.org
Subject: Re: [PATCH 1/2] clk: hisilicon: add hi3620_mmc_clks
Date: Tue, 14 Jan 2014 18:04:55 +0800 [thread overview]
Message-ID: <CAMj5BkgCzg-Nqm-FX_36-1ShGsL9x1HALmtywm-0sHtp53wR5A@mail.gmail.com> (raw)
In-Reply-To: <002901cf110d$993b4880$cbb1d980$%jun@samsung.com>
>> +static long mmc_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
>> + unsigned long *best_parent_rate,
>> + struct clk **best_parent_p)
>> +{
>> + struct clk_mmc *mclk = to_mmc(hw);
>> + unsigned long best = 0;
>> +
>> + if ((rate <= 13000000) && (mclk->id == HI3620_MMC_CIUCLK1)) {
> No need to check HI3620_MMC_CIUCLK2 and HI3620_MMC_CIUCLK3?
Yes, only emmc, id=HI3620_MMC_CIUCLK1, using init clk 13M, while
others use init clock 25M.
Add this to handle init mmc init clk 400K and return source clock rate
13M, from your suggestion in fact.
>
>> + rate = 13000000;
>> + best = 26000000;
>> + } else if (rate <= 26000000) {
>> + rate = 25000000;
>> + best = 180000000;
>> + } else if (rate <= 52000000) {
>> + rate = 50000000;
>> + best = 360000000;
>> + } else if (rate <= 100000000) {
>> + rate = 100000000;
>> + best = 720000000;
>> + } else {
>> + /* max is 180M */
>> + rate = 180000000;
>> + best = 1440000000;
>> + }
>> + *best_parent_rate = best;
>> + return rate;
>> +}
>> +static int mmc_clk_prepare(struct clk_hw *hw)
>> +{
>> + struct clk_mmc *mclk = to_mmc(hw);
>> + unsigned long rate;
>> +
>> + if (mclk->id == HI3620_MMC_CIUCLK1)
> HI3620_SD_CIUCLK was used in previous version.
Yes, fixed, though it can work on the dev board.
> Is it fixed with HI3620_MMC_CIUCLK1?
> And, please clarify in case of HI3620_MMC_CIUCLK2 and HI3620_MMC_CIUCLK3 as well.
Only HI3620_MMC_CIUCLK1 use 13M for init, all others use 25M on hi3620.
>
> Thanks,
> Seungwon Jeon
>
>> + rate = 13000000;
>> + else
>> + rate = 25000000;
>> +
>> + return mmc_clk_set_timing(hw, rate);
>> +}
>> +
Thanks
next prev parent reply other threads:[~2014-01-14 10:04 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-13 9:14 [PATCH 0/2] mmc: dw_mmc: k3 remove clk_table Zhangfei Gao
2014-01-13 9:14 ` [PATCH 1/2] clk: hisilicon: add hi3620_mmc_clks Zhangfei Gao
2014-01-13 9:37 ` [PATCH] " Zhangfei Gao
2014-02-27 0:10 ` Mike Turquette
2014-01-14 9:47 ` [PATCH 1/2] " Seungwon Jeon
2014-01-14 10:04 ` Zhangfei Gao [this message]
2014-01-14 10:40 ` Seungwon Jeon
2014-01-14 11:52 ` zhangfei
[not found] ` <1389604469-8064-2-git-send-email-zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2014-01-14 20:17 ` Mike Turquette
2014-01-15 1:40 ` zhangfei
2014-01-15 3:53 ` Mike Turquette
2014-01-15 5:59 ` Haojian Zhuang
2014-01-15 8:29 ` Mike Turquette
2014-01-15 9:34 ` Haojian Zhuang
2014-01-15 16:14 ` Kevin Hilman
2014-01-13 9:14 ` [PATCH 2/2] mmc: dw_mmc: k3: remove clk_table Zhangfei Gao
2014-01-14 10:42 ` Seungwon Jeon
[not found] ` <002b01cf1115$4cdfe240$e69fa6c0$%jun-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2014-01-17 15:01 ` Chris Ball
2014-01-17 16:10 ` Seungwon Jeon
2014-01-17 22:56 ` Mike Turquette
2014-01-17 23:00 ` Chris Ball
2014-01-17 14:43 ` Seungwon Jeon
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