From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDF11C43603 for ; Thu, 19 Dec 2019 10:53:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A2498227BF for ; Thu, 19 Dec 2019 10:53:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="Qk2ztRNJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726808AbfLSKxT (ORCPT ); Thu, 19 Dec 2019 05:53:19 -0500 Received: from mail-qt1-f193.google.com ([209.85.160.193]:32937 "EHLO mail-qt1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726696AbfLSKxT (ORCPT ); Thu, 19 Dec 2019 05:53:19 -0500 Received: by mail-qt1-f193.google.com with SMTP id d5so4696500qto.0 for ; Thu, 19 Dec 2019 02:53:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=IIuROUmiihU5/B8NCkUBw/bfwJUgV5QA6aHceLRcSgo=; b=Qk2ztRNJiaZYe5KTp+VkB2+m9oL1jp1wW7zAjyoHaFVvlYN4jQ/Q8FTRopN99xMIzT yLpTyqX1NGepLy5dU2nsZkDtQ1JO1T6hj8OEk3OhpBSng97yDWt2qw5Iw6p1G/CG6HGo xh4hHeGyQDl2bGMNMz1ZnpW+MBVcw6S59XqWaAEe2dnS0vc6W+t+WdTyiwndoNPOigNZ SivAAoG6f/iTyDZ4D9kNRLSuZQ/4NWH94VKETaDOB4RVHSJUrU5gG4WD+OIvWzbVoBzy g97zxEnhRIMjm7pj0RgqU+Et31Po9s3iE89+qZ7m9Ovgh223tZnrKZJpJkDAvq9y48Oz cQhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=IIuROUmiihU5/B8NCkUBw/bfwJUgV5QA6aHceLRcSgo=; b=hcOaKSUo7xaStBZMfwU46sydcv2I2e289OtUSBkBIuSVuwoZPUYnTGvuaE0Ak9DBUq JAch6cOExrJHsN3aVOUykEaZzJOw0NZNDXgKOeKLOpooOkZUVRmgqEVObeG+5hSCNiVU Ie5rAhfO00WXUZSt3rk/oQ38IQO1ywn+ZuQ+G17Ni3yocta1cYKDbIrZm1lvh47Rlym+ yzBL95yLg9JzaQUSASoV1mnfxQDZ024K/rJX0ElaOmYBdX1d17e3Kj8yBQE+EQs6nB7L Wk71DbKmo7sJYYmAnQM6MKSWA/qZkxx7k3GDcNaCGW74WwpH2NQaa+0FOJNk9AfI8Idw OCuA== X-Gm-Message-State: APjAAAUZJOeLNq4wvrZISIFj9vNoh9n6AFSamR2svDIQ1TTvc/CYqlVg LytnOV5UJc48ZiZahigqpzoTfGYNYM5eYYLWvxP+QQ== X-Google-Smtp-Source: APXvYqwuOZ8jOwab1DPiMEfvgPdn8LVbmJvxmNOywr9VbwLO6NhzWQA0IvMtiPi6RS1ZunYqPuMm710wLMboY4QBOvk= X-Received: by 2002:ac8:704:: with SMTP id g4mr6314518qth.197.1576752798327; Thu, 19 Dec 2019 02:53:18 -0800 (PST) MIME-Version: 1.0 References: <20191210154157.21930-1-ktouil@baylibre.com> In-Reply-To: From: Bartosz Golaszewski Date: Thu, 19 Dec 2019 11:53:07 +0100 Message-ID: Subject: Re: [PATCH v2 0/4] at24: move write-protect pin handling to nvmem core To: Srinivas Kandagatla Cc: Khouloud Touil , Rob Herring , Mark Rutland , baylibre-upstreaming@groups.io, LKML , linux-devicetree , linux-i2c , Linus Walleij Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org czw., 19 gru 2019 o 11:51 Srinivas Kandagatla napisa=C5=82(a): > > > > On 10/12/2019 15:41, Khouloud Touil wrote: > > The write-protect pin handling looks like a standard property that > > could benefit other users if available in the core nvmem framework. > > > > Instead of modifying all the drivers to check this pin, make the > > nvmem subsystem check if the write-protect GPIO being passed > > through the nvmem_config or defined in the device tree and pull it > > low whenever writing to the memory. > > > > This patchset: > > > > - adds support for the write-protect pin split into two parts. > > The first patch modifies modifies the relevant binding document, > > while the second modifies the nvmem code to pull the write-protect > > GPIO low (if present) during write operations. > > > > - removes support for the write-protect pin split into two parts. > > The first patch modifies the relevant binding document to remove > > the wp-gpio, while the second removes the relevant code in the > > at24 driver. > > > > Changes since v1: > > -Add an explenation on how the wp-gpios works > > -keep reference to the wp-gpios in the at24 binding > > > > Khouloud Touil (4): > > dt-bindings: nvmem: new optional property write-protect-gpios > > nvmem: add support for the write-protect pin > > dt-bindings: at24: remove the optional property write-protect-gpios > > eeprom: at24: remove the write-protect pin support > > > > Thanks Khouloud for this patchset, > > I can take this via nvmem tree once we get an ack on dt bindings from DT > maintainers. > Hi Srinivas, this will conflict with my at24 tree for this release - can you put those patches (once they're fine) into an immutable branch for me to merge in? Bart > > --srini > > .../devicetree/bindings/eeprom/at24.yaml | 6 +----- > > .../devicetree/bindings/nvmem/nvmem.yaml | 9 +++++++++ > > drivers/misc/eeprom/at24.c | 9 --------- > > drivers/nvmem/core.c | 19 +++++++++++++++++-= - > > drivers/nvmem/nvmem.h | 2 ++ > > include/linux/nvmem-provider.h | 3 +++ > > 6 files changed, 32 insertions(+), 16 deletions(-) > >