From: joswang <joswang1221@gmail.com>
To: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Cc: "robh@kernel.org" <robh@kernel.org>,
"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"conor+dt@kernel.org" <conor+dt@kernel.org>,
"gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
"linux-usb@vger.kernel.org" <linux-usb@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"balbi@kernel.org" <balbi@kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
joswang <joswang@lenovo.com>
Subject: Re: [PATCH v2, 2/3] usb: dwc3: core: add p3p2tranok quirk
Date: Wed, 19 Jun 2024 19:56:13 +0800 [thread overview]
Message-ID: <CAMtoTm0S2WSO6VxK79DkTs+1aq5xBYBMRsPXWAFuWo4DoymUEw@mail.gmail.com> (raw)
In-Reply-To: <20240604000147.2xxkkp7efjsbr3i5@synopsys.com>
Hi Thinh
The workaround solution provided by your company for this issue is as follows:
Workaround：if the phy support direct P3 to P2 transition，program
GUSB3PIPECTL.P3P2Tranok=1
As the databook mentions:
This bit is used only for some non-Synopsys PHYs that cannot do LFPS in P3.
This bit is used by third-party SS PHY. It must be set to '0' for Synopsys PHY.
For Synopsys PHY, if this bit is set to "1", will it cause unknown problems?
Please help confirm this, thank you!
Thanks,
Jos Wang
next prev parent reply other threads:[~2024-06-19 11:56 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20240601092646.52139-1-joswang1221@gmail.com>
2024-06-03 13:00 ` [PATCH v2, 1/3] dt-bindings: usb: dwc3: Add snps,p2p3tranok quirk joswang
2024-06-04 6:33 ` Krzysztof Kozlowski
2024-06-12 14:28 ` joswang
2024-06-13 6:09 ` Krzysztof Kozlowski
2024-06-03 13:01 ` [PATCH v2, 2/3] usb: dwc3: core: add p3p2tranok quirk joswang
2024-06-04 0:02 ` Thinh Nguyen
2024-06-05 4:49 ` joswang
2024-06-07 14:24 ` joswang
2024-06-19 11:56 ` joswang [this message]
2024-06-22 0:05 ` Thinh Nguyen
2024-06-25 13:31 ` joswang
2024-06-26 1:29 ` Thinh Nguyen
2024-07-01 11:48 ` joswang
2024-06-03 13:02 ` [PATCH v2, 3/3] usb: dwc3: core: Workaround for CSR read timeout joswang
2024-06-04 0:07 ` Thinh Nguyen
2024-06-04 13:36 ` joswang
2024-06-04 23:13 ` Thinh Nguyen
2024-06-06 1:29 ` Thinh Nguyen
2024-06-07 14:07 ` joswang
2024-06-07 22:36 ` Thinh Nguyen
[not found] ` <CAMtoTm1roAvvWCu9LSfcbnozZnakMEexdUVxNyZ7N5KOG8tHcg@mail.gmail.com>
2024-06-07 22:49 ` Thinh Nguyen
2024-06-12 14:54 ` [PATCH v3, 1/3] dt-bindings: usb: dwc3: Add snps,p2p3tranok quirk joswang
2024-06-12 15:23 ` [PATCH v4, " joswang
2024-06-13 6:17 ` Krzysztof Kozlowski
2024-06-13 13:19 ` joswang
2024-06-13 14:03 ` Krzysztof Kozlowski
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAMtoTm0S2WSO6VxK79DkTs+1aq5xBYBMRsPXWAFuWo4DoymUEw@mail.gmail.com \
--to=joswang1221@gmail.com \
--cc=Thinh.Nguyen@synopsys.com \
--cc=balbi@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=gregkh@linuxfoundation.org \
--cc=joswang@lenovo.com \
--cc=krzk+dt@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-usb@vger.kernel.org \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).