[PATCH 00/17] clk: renesas: rzg2l: Add support for power domains

[PATCH 00/17] clk: renesas: rzg2l: Add support for power domains

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Hi,

Series adds support for power domains on rzg2l driver.

RZ/G2L kind of devices support a functionality called MSTOP (module
stop/standby). According to hardware manual the module could be switch
to standby after its clocks are disabled. The reverse order of operation
should be done when enabling a module (get the module out of standby,
enable its clocks etc).

In [1] the MSTOP settings were implemented by adding code in driver
to attach the MSTOP state to the IP clocks. But it has been proposed
to implement it as power domain. The result is this series.

Along with MSTOP functionality there is also module power down
functionality (which is currently available only on RZ/G3S). This has
been also implemented through power domains.

The DT bindings were updated with power domain IDs (plain integers
that matches the DT with driver data structures). The current DT
bindings were updated with module IDs for the modules listed in tables
with name "Registers for Module Standby Mode" (see HW manual) exception
being RZ/G3S where, due to the power down functionality, the DDR,
TZCDDR, OTFDE_DDR were also added, to avoid system being blocked due
to the following lines of code from patch 7/17.

+       /* Prepare for power down the BUSes in power down mode. */
+       if (info->pm_domain_pwrdn_mstop)
+               writel(CPG_PWRDN_MSTOP_ENABLE, priv->base + CPG_PWRDN_MSTOP);

Domain IDs were added to all SoC specific bindings to avoid breaking
dt schema validation failures.

If the proposed dt-binding update is good for you, please let me know
if you want me to also update the individual dt schemas to reflect
the newly introduced power domain IDs in schema examples, if any.

Thank you,
Claudiu Beznea 

[1] https://lore.kernel.org/all/20231120070024.4079344-4-claudiu.beznea.uj@bp.renesas.com/

Claudiu Beznea (17):
  dt-bindings: clock: r9a07g043-cpg: Add power domain IDs
  dt-bindings: clock: r9a07g044-cpg: Add power domain IDs
  dt-bindings: clock: r9a07g054-cpg: Add power domain IDs
  dt-bindings: clock: r9a08g045-cpg: Add power domain IDs
  dt-bindings: clock: r9a09g011-cpg: Add always-on power domain IDs
  dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells =
    <1>
  clk: renesas: rzg2l: Extend power domain support
  clk: renesas: r9a07g043: Add initial support for power domains
  clk: renesas: r9a07g044: Add initial support for power domains
  clk: renesas: r9a08g045: Add support for power domains
  clk: renesas: r9a09g011: Add initial support for power domains
  arm64: dts: renesas: rzg3s-smarc-som: Guard the ethernet IRQ GPIOs
    with proper flags
  arm64: dts: renesas: r9a07g043: Update #power-domain-cells = <1>
  arm64: dts: renesas: r9a07g044: Update #power-domain-cells = <1>
  arm64: dts: renesas: r9a07g054: Update #power-domain-cells = <1>
  arm64: dts: renesas: r9a08g045: Update #power-domain-cells = <1>
  arm64: dts: renesas: r9a09g011: Update #power-domain-cells = <1>

 .../bindings/clock/renesas,rzg2l-cpg.yaml     |   4 +-
 arch/arm64/boot/dts/renesas/r9a07g043.dtsi    |  84 +++----
 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi   |   6 +-
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi    | 100 ++++----
 arch/arm64/boot/dts/renesas/r9a07g054.dtsi    | 100 ++++----
 arch/arm64/boot/dts/renesas/r9a08g045.dtsi    |  20 +-
 arch/arm64/boot/dts/renesas/r9a09g011.dtsi    |  28 +--
 .../boot/dts/renesas/rzg3s-smarc-som.dtsi     |   4 +
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi   |   2 +-
 drivers/clk/renesas/r9a07g043-cpg.c           |   9 +
 drivers/clk/renesas/r9a07g044-cpg.c           |  13 +
 drivers/clk/renesas/r9a08g045-cpg.c           |  27 +++
 drivers/clk/renesas/r9a09g011-cpg.c           |   9 +
 drivers/clk/renesas/rzg2l-cpg.c               | 227 ++++++++++++++++--
 drivers/clk/renesas/rzg2l-cpg.h               |  68 ++++++
 include/dt-bindings/clock/r9a07g043-cpg.h     |  48 ++++
 include/dt-bindings/clock/r9a07g044-cpg.h     |  58 +++++
 include/dt-bindings/clock/r9a07g054-cpg.h     |  58 +++++
 include/dt-bindings/clock/r9a08g045-cpg.h     |  70 ++++++
 include/dt-bindings/clock/r9a09g011-cpg.h     |   3 +
 20 files changed, 752 insertions(+), 186 deletions(-)

-- 
2.39.2

[PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Add power domain IDs for RZ/G2UL (R9A07G043) SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 include/dt-bindings/clock/r9a07g043-cpg.h | 48 +++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h
index 77cde8effdc7..eabfeec7ac37 100644
--- a/include/dt-bindings/clock/r9a07g043-cpg.h
+++ b/include/dt-bindings/clock/r9a07g043-cpg.h
@@ -200,5 +200,53 @@
 #define R9A07G043_AX45MP_CORE0_RESETN	78	/* RZ/Five Only */
 #define R9A07G043_IAX45_RESETN		79	/* RZ/Five Only */
 
+/* Power domain IDs. */
+#define R9A07G043_PD_ALWAYS_ON		0
+#define R9A07G043_PD_GIC		1
+#define R9A07G043_PD_IA55		2
+#define R9A07G043_PD_MHU		3
+#define R9A07G043_PD_CORESIGHT		4
+#define R9A07G043_PD_SYC		5
+#define R9A07G043_PD_DMAC		6
+#define R9A07G043_PD_GTM0		7
+#define R9A07G043_PD_GTM1		8
+#define R9A07G043_PD_GTM2		9
+#define R9A07G043_PD_MTU		10
+#define R9A07G043_PD_POE3		11
+#define R9A07G043_PD_WDT0		12
+#define R9A07G043_PD_SPI		13
+#define R9A07G043_PD_SDHI0		14
+#define R9A07G043_PD_SDHI1		15
+#define R9A07G043_PD_ISU		16
+#define R9A07G043_PD_CRU		17
+#define R9A07G043_PD_LCDC		18
+#define R9A07G043_PD_SSI0		19
+#define R9A07G043_PD_SSI1		20
+#define R9A07G043_PD_SSI2		21
+#define R9A07G043_PD_SSI3		22
+#define R9A07G043_PD_SRC		23
+#define R9A07G043_PD_USB0		24
+#define R9A07G043_PD_USB1		25
+#define R9A07G043_PD_USB_PHY		26
+#define R9A07G043_PD_ETHER0		27
+#define R9A07G043_PD_ETHER1		28
+#define R9A07G043_PD_I2C0		29
+#define R9A07G043_PD_I2C1		30
+#define R9A07G043_PD_I2C2		31
+#define R9A07G043_PD_I2C3		32
+#define R9A07G043_PD_SCIF0		33
+#define R9A07G043_PD_SCIF1		34
+#define R9A07G043_PD_SCIF2		35
+#define R9A07G043_PD_SCIF3		36
+#define R9A07G043_PD_SCIF4		37
+#define R9A07G043_PD_SCI0		38
+#define R9A07G043_PD_SCI1		39
+#define R9A07G043_PD_IRDA		40
+#define R9A07G043_PD_RSPI0		41
+#define R9A07G043_PD_RSPI1		42
+#define R9A07G043_PD_RSPI2		43
+#define R9A07G043_PD_CANFD		44
+#define R9A07G043_PD_ADC		45
+#define R9A07G043_PD_TSU		46
 
 #endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */
-- 
2.39.2

RE: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs

[Biju Das]

Hi Claudiu,

Thanks for the patch.

> -----Original Message-----
> From: Claudiu <claudiu.beznea@tuxon.dev>
> Sent: Thursday, February 8, 2024 12:43 PM
> Subject: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain
> IDs
> 
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>  include/dt-bindings/clock/r9a07g043-cpg.h | 48 +++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-
> bindings/clock/r9a07g043-cpg.h
> index 77cde8effdc7..eabfeec7ac37 100644
> --- a/include/dt-bindings/clock/r9a07g043-cpg.h
> +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
> @@ -200,5 +200,53 @@
>  #define R9A07G043_AX45MP_CORE0_RESETN	78	/* RZ/Five Only */
>  #define R9A07G043_IAX45_RESETN		79	/* RZ/Five Only */
> 
> +/* Power domain IDs. */
> +#define R9A07G043_PD_ALWAYS_ON		0
> +#define R9A07G043_PD_GIC		1
> +#define R9A07G043_PD_IA55		2
> +#define R9A07G043_PD_MHU		3
> +#define R9A07G043_PD_CORESIGHT		4
> +#define R9A07G043_PD_SYC		5
> +#define R9A07G043_PD_DMAC		6
> +#define R9A07G043_PD_GTM0		7
> +#define R9A07G043_PD_GTM1		8
> +#define R9A07G043_PD_GTM2		9
> +#define R9A07G043_PD_MTU		10
> +#define R9A07G043_PD_POE3		11
> +#define R9A07G043_PD_WDT0		12
> +#define R9A07G043_PD_SPI		13
> +#define R9A07G043_PD_SDHI0		14
> +#define R9A07G043_PD_SDHI1		15
> +#define R9A07G043_PD_ISU		16
> +#define R9A07G043_PD_CRU		17
> +#define R9A07G043_PD_LCDC		18
> +#define R9A07G043_PD_SSI0		19
> +#define R9A07G043_PD_SSI1		20
> +#define R9A07G043_PD_SSI2		21
> +#define R9A07G043_PD_SSI3		22
> +#define R9A07G043_PD_SRC		23
> +#define R9A07G043_PD_USB0		24
> +#define R9A07G043_PD_USB1		25
> +#define R9A07G043_PD_USB_PHY		26
> +#define R9A07G043_PD_ETHER0		27
> +#define R9A07G043_PD_ETHER1		28
> +#define R9A07G043_PD_I2C0		29
> +#define R9A07G043_PD_I2C1		30
> +#define R9A07G043_PD_I2C2		31
> +#define R9A07G043_PD_I2C3		32
> +#define R9A07G043_PD_SCIF0		33
> +#define R9A07G043_PD_SCIF1		34
> +#define R9A07G043_PD_SCIF2		35
> +#define R9A07G043_PD_SCIF3		36
> +#define R9A07G043_PD_SCIF4		37
> +#define R9A07G043_PD_SCI0		38
> +#define R9A07G043_PD_SCI1		39
> +#define R9A07G043_PD_IRDA		40
> +#define R9A07G043_PD_RSPI0		41
> +#define R9A07G043_PD_RSPI1		42
> +#define R9A07G043_PD_RSPI2		43
> +#define R9A07G043_PD_CANFD		44
> +#define R9A07G043_PD_ADC		45
> +#define R9A07G043_PD_TSU		46

Not sure from "Table 42.3 Registers for Module Standby Mode"

Power domain ID has to be based on CPG_BUS_***_MSTOP or CPG_CLKON_***
As former reduces number of IDs??

Cheers,
Biju

 

Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs

[claudiu beznea]

Hi, Biju,

On 08.02.2024 16:30, Biju Das wrote:
> Hi Claudiu,
> 
> Thanks for the patch.
> 
>> -----Original Message-----
>> From: Claudiu <claudiu.beznea@tuxon.dev>
>> Sent: Thursday, February 8, 2024 12:43 PM
>> Subject: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain
>> IDs
>>
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>> ---
>>  include/dt-bindings/clock/r9a07g043-cpg.h | 48 +++++++++++++++++++++++
>>  1 file changed, 48 insertions(+)
>>
>> diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-
>> bindings/clock/r9a07g043-cpg.h
>> index 77cde8effdc7..eabfeec7ac37 100644
>> --- a/include/dt-bindings/clock/r9a07g043-cpg.h
>> +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
>> @@ -200,5 +200,53 @@
>>  #define R9A07G043_AX45MP_CORE0_RESETN	78	/* RZ/Five Only */
>>  #define R9A07G043_IAX45_RESETN		79	/* RZ/Five Only */
>>
>> +/* Power domain IDs. */
>> +#define R9A07G043_PD_ALWAYS_ON		0
>> +#define R9A07G043_PD_GIC		1
>> +#define R9A07G043_PD_IA55		2
>> +#define R9A07G043_PD_MHU		3
>> +#define R9A07G043_PD_CORESIGHT		4
>> +#define R9A07G043_PD_SYC		5
>> +#define R9A07G043_PD_DMAC		6
>> +#define R9A07G043_PD_GTM0		7
>> +#define R9A07G043_PD_GTM1		8
>> +#define R9A07G043_PD_GTM2		9
>> +#define R9A07G043_PD_MTU		10
>> +#define R9A07G043_PD_POE3		11
>> +#define R9A07G043_PD_WDT0		12
>> +#define R9A07G043_PD_SPI		13
>> +#define R9A07G043_PD_SDHI0		14
>> +#define R9A07G043_PD_SDHI1		15
>> +#define R9A07G043_PD_ISU		16
>> +#define R9A07G043_PD_CRU		17
>> +#define R9A07G043_PD_LCDC		18
>> +#define R9A07G043_PD_SSI0		19
>> +#define R9A07G043_PD_SSI1		20
>> +#define R9A07G043_PD_SSI2		21
>> +#define R9A07G043_PD_SSI3		22
>> +#define R9A07G043_PD_SRC		23
>> +#define R9A07G043_PD_USB0		24
>> +#define R9A07G043_PD_USB1		25
>> +#define R9A07G043_PD_USB_PHY		26
>> +#define R9A07G043_PD_ETHER0		27
>> +#define R9A07G043_PD_ETHER1		28
>> +#define R9A07G043_PD_I2C0		29
>> +#define R9A07G043_PD_I2C1		30
>> +#define R9A07G043_PD_I2C2		31
>> +#define R9A07G043_PD_I2C3		32
>> +#define R9A07G043_PD_SCIF0		33
>> +#define R9A07G043_PD_SCIF1		34
>> +#define R9A07G043_PD_SCIF2		35
>> +#define R9A07G043_PD_SCIF3		36
>> +#define R9A07G043_PD_SCIF4		37
>> +#define R9A07G043_PD_SCI0		38
>> +#define R9A07G043_PD_SCI1		39
>> +#define R9A07G043_PD_IRDA		40
>> +#define R9A07G043_PD_RSPI0		41
>> +#define R9A07G043_PD_RSPI1		42
>> +#define R9A07G043_PD_RSPI2		43
>> +#define R9A07G043_PD_CANFD		44
>> +#define R9A07G043_PD_ADC		45
>> +#define R9A07G043_PD_TSU		46
> 
> Not sure from "Table 42.3 Registers for Module Standby Mode"
> 
> Power domain ID has to be based on CPG_BUS_***_MSTOP or CPG_CLKON_***
> As former reduces number of IDs??

If I understand correctly your point here, you want me to describe PM
domain in DT with something like:

power-domains = <&cpg CPG_BUS_X_MSTOP>;

where X={ACPU, PERI_CPU, PERI_CPU2, REG0, REG1} ?

With this, I still see the necessity of a 3rd identifier that will be IP
specific to be able to uniquely match b/w DT description and registered
power domain. FMPOV, this will lead to a more complicated implementation.

We need a unique ID that the pm domain xlate will use to xlate the DT
binding to driver data structures.

Thank you,
Claudiu Beznea
> 
> Cheers,
> Biju
> 
>  
> 

RE: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs

[Biju Das]

> -----Original Message-----
> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> Sent: Thursday, February 8, 2024 3:46 PM
> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power
> domain IDs
> 
> Hi, Biju,
> 
> On 08.02.2024 16:30, Biju Das wrote:
> > Hi Claudiu,
> >
> > Thanks for the patch.
> >
> >> -----Original Message-----
> >> From: Claudiu <claudiu.beznea@tuxon.dev>
> >> Sent: Thursday, February 8, 2024 12:43 PM
> >> Subject: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power
> >> domain IDs
> >>
> >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>
> >> Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >> ---
> >>  include/dt-bindings/clock/r9a07g043-cpg.h | 48
> >> +++++++++++++++++++++++
> >>  1 file changed, 48 insertions(+)
> >>
> >> diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-
> >> bindings/clock/r9a07g043-cpg.h index 77cde8effdc7..eabfeec7ac37
> >> 100644
> >> --- a/include/dt-bindings/clock/r9a07g043-cpg.h
> >> +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
> >> @@ -200,5 +200,53 @@
> >>  #define R9A07G043_AX45MP_CORE0_RESETN	78	/* RZ/Five Only */
> >>  #define R9A07G043_IAX45_RESETN		79	/* RZ/Five Only */
> >>
> >> +/* Power domain IDs. */
> >> +#define R9A07G043_PD_ALWAYS_ON		0
> >> +#define R9A07G043_PD_GIC		1
> >> +#define R9A07G043_PD_IA55		2
> >> +#define R9A07G043_PD_MHU		3
> >> +#define R9A07G043_PD_CORESIGHT		4
> >> +#define R9A07G043_PD_SYC		5
> >> +#define R9A07G043_PD_DMAC		6
> >> +#define R9A07G043_PD_GTM0		7
> >> +#define R9A07G043_PD_GTM1		8
> >> +#define R9A07G043_PD_GTM2		9
> >> +#define R9A07G043_PD_MTU		10
> >> +#define R9A07G043_PD_POE3		11
> >> +#define R9A07G043_PD_WDT0		12
> >> +#define R9A07G043_PD_SPI		13
> >> +#define R9A07G043_PD_SDHI0		14
> >> +#define R9A07G043_PD_SDHI1		15
> >> +#define R9A07G043_PD_ISU		16
> >> +#define R9A07G043_PD_CRU		17
> >> +#define R9A07G043_PD_LCDC		18
> >> +#define R9A07G043_PD_SSI0		19
> >> +#define R9A07G043_PD_SSI1		20
> >> +#define R9A07G043_PD_SSI2		21
> >> +#define R9A07G043_PD_SSI3		22
> >> +#define R9A07G043_PD_SRC		23
> >> +#define R9A07G043_PD_USB0		24
> >> +#define R9A07G043_PD_USB1		25
> >> +#define R9A07G043_PD_USB_PHY		26
> >> +#define R9A07G043_PD_ETHER0		27
> >> +#define R9A07G043_PD_ETHER1		28
> >> +#define R9A07G043_PD_I2C0		29
> >> +#define R9A07G043_PD_I2C1		30
> >> +#define R9A07G043_PD_I2C2		31
> >> +#define R9A07G043_PD_I2C3		32
> >> +#define R9A07G043_PD_SCIF0		33
> >> +#define R9A07G043_PD_SCIF1		34
> >> +#define R9A07G043_PD_SCIF2		35
> >> +#define R9A07G043_PD_SCIF3		36
> >> +#define R9A07G043_PD_SCIF4		37
> >> +#define R9A07G043_PD_SCI0		38
> >> +#define R9A07G043_PD_SCI1		39
> >> +#define R9A07G043_PD_IRDA		40
> >> +#define R9A07G043_PD_RSPI0		41
> >> +#define R9A07G043_PD_RSPI1		42
> >> +#define R9A07G043_PD_RSPI2		43
> >> +#define R9A07G043_PD_CANFD		44
> >> +#define R9A07G043_PD_ADC		45
> >> +#define R9A07G043_PD_TSU		46
> >
> > Not sure from "Table 42.3 Registers for Module Standby Mode"
> >
> > Power domain ID has to be based on CPG_BUS_***_MSTOP or CPG_CLKON_***
> > As former reduces number of IDs??
> 
> If I understand correctly your point here, you want me to describe PM
> domain in DT with something like:
> 
> power-domains = <&cpg CPG_BUS_X_MSTOP>;

MSTOP bits are distinct for each IP.

<&cpg CPG_BUS_MCPU1_MSTOP x>; x =1..9

2=MTU IP

4= GPT

etc...

Is it something work??

> 
> where X={ACPU, PERI_CPU, PERI_CPU2, REG0, REG1} ?
> 
> With this, I still see the necessity of a 3rd identifier that will be IP
> specific to be able to uniquely match b/w DT description and registered
> power domain. FMPOV, this will lead to a more complicated implementation.
> 
> We need a unique ID that the pm domain xlate will use to xlate the DT
> binding to driver data structures.

Ok.

Cheers,
Biju

Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs

[claudiu beznea]

On 08.02.2024 18:28, Biju Das wrote:
> 
> 
>> -----Original Message-----
>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>> Sent: Thursday, February 8, 2024 3:46 PM
>> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power
>> domain IDs
>>
>> Hi, Biju,
>>
>> On 08.02.2024 16:30, Biju Das wrote:
>>> Hi Claudiu,
>>>
>>> Thanks for the patch.
>>>
>>>> -----Original Message-----
>>>> From: Claudiu <claudiu.beznea@tuxon.dev>
>>>> Sent: Thursday, February 8, 2024 12:43 PM
>>>> Subject: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power
>>>> domain IDs
>>>>
>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>
>>>> Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
>>>>
>>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>> ---
>>>>  include/dt-bindings/clock/r9a07g043-cpg.h | 48
>>>> +++++++++++++++++++++++
>>>>  1 file changed, 48 insertions(+)
>>>>
>>>> diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-
>>>> bindings/clock/r9a07g043-cpg.h index 77cde8effdc7..eabfeec7ac37
>>>> 100644
>>>> --- a/include/dt-bindings/clock/r9a07g043-cpg.h
>>>> +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
>>>> @@ -200,5 +200,53 @@
>>>>  #define R9A07G043_AX45MP_CORE0_RESETN	78	/* RZ/Five Only */
>>>>  #define R9A07G043_IAX45_RESETN		79	/* RZ/Five Only */
>>>>
>>>> +/* Power domain IDs. */
>>>> +#define R9A07G043_PD_ALWAYS_ON		0
>>>> +#define R9A07G043_PD_GIC		1
>>>> +#define R9A07G043_PD_IA55		2
>>>> +#define R9A07G043_PD_MHU		3
>>>> +#define R9A07G043_PD_CORESIGHT		4
>>>> +#define R9A07G043_PD_SYC		5
>>>> +#define R9A07G043_PD_DMAC		6
>>>> +#define R9A07G043_PD_GTM0		7
>>>> +#define R9A07G043_PD_GTM1		8
>>>> +#define R9A07G043_PD_GTM2		9
>>>> +#define R9A07G043_PD_MTU		10
>>>> +#define R9A07G043_PD_POE3		11
>>>> +#define R9A07G043_PD_WDT0		12
>>>> +#define R9A07G043_PD_SPI		13
>>>> +#define R9A07G043_PD_SDHI0		14
>>>> +#define R9A07G043_PD_SDHI1		15
>>>> +#define R9A07G043_PD_ISU		16
>>>> +#define R9A07G043_PD_CRU		17
>>>> +#define R9A07G043_PD_LCDC		18
>>>> +#define R9A07G043_PD_SSI0		19
>>>> +#define R9A07G043_PD_SSI1		20
>>>> +#define R9A07G043_PD_SSI2		21
>>>> +#define R9A07G043_PD_SSI3		22
>>>> +#define R9A07G043_PD_SRC		23
>>>> +#define R9A07G043_PD_USB0		24
>>>> +#define R9A07G043_PD_USB1		25
>>>> +#define R9A07G043_PD_USB_PHY		26
>>>> +#define R9A07G043_PD_ETHER0		27
>>>> +#define R9A07G043_PD_ETHER1		28
>>>> +#define R9A07G043_PD_I2C0		29
>>>> +#define R9A07G043_PD_I2C1		30
>>>> +#define R9A07G043_PD_I2C2		31
>>>> +#define R9A07G043_PD_I2C3		32
>>>> +#define R9A07G043_PD_SCIF0		33
>>>> +#define R9A07G043_PD_SCIF1		34
>>>> +#define R9A07G043_PD_SCIF2		35
>>>> +#define R9A07G043_PD_SCIF3		36
>>>> +#define R9A07G043_PD_SCIF4		37
>>>> +#define R9A07G043_PD_SCI0		38
>>>> +#define R9A07G043_PD_SCI1		39
>>>> +#define R9A07G043_PD_IRDA		40
>>>> +#define R9A07G043_PD_RSPI0		41
>>>> +#define R9A07G043_PD_RSPI1		42
>>>> +#define R9A07G043_PD_RSPI2		43
>>>> +#define R9A07G043_PD_CANFD		44
>>>> +#define R9A07G043_PD_ADC		45
>>>> +#define R9A07G043_PD_TSU		46
>>>
>>> Not sure from "Table 42.3 Registers for Module Standby Mode"
>>>
>>> Power domain ID has to be based on CPG_BUS_***_MSTOP or CPG_CLKON_***
>>> As former reduces number of IDs??
>>
>> If I understand correctly your point here, you want me to describe PM
>> domain in DT with something like:
>>
>> power-domains = <&cpg CPG_BUS_X_MSTOP>;
> 
> MSTOP bits are distinct for each IP.
> 
> <&cpg CPG_BUS_MCPU1_MSTOP x>; x =1..9
> 
> 2=MTU IP
> 
> 4= GPT
> 
> etc...
> 
> Is it something work??

It might work. But:

- you have to consider that some IPs have more than one MSTOP bit, thus, do
  we want to uniquely identify these with all MSTOP bits (thus the 2nd cell
  being a bitmask) or only one is enough?
- some HW blocks (e.g. OTFDE_DDR) have no MSTOP bits associated (as of my
  current research), so, only PWRDN
- some HW blocks have both MSTOP and PWRDN
- if future hardware implementation will spread the MSTOP bits for one IP
  to more than one register then this proposal will not work

Having a unique identified decoupled from MSTOP registers or PWRDN offers
support to use the same code base for future usage. This is what I can tell
at the moment.

> 
>>
>> where X={ACPU, PERI_CPU, PERI_CPU2, REG0, REG1} ?
>>
>> With this, I still see the necessity of a 3rd identifier that will be IP
>> specific to be able to uniquely match b/w DT description and registered
>> power domain. FMPOV, this will lead to a more complicated implementation.
>>
>> We need a unique ID that the pm domain xlate will use to xlate the DT
>> binding to driver data structures.
> 
> Ok.
> 
> Cheers,
> Biju
> 

RE: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs

[Biju Das]

> -----Original Message-----
> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> Sent: Thursday, February 8, 2024 4:53 PM
> To: Biju Das <biju.das.jz@bp.renesas.com>; geert+renesas@glider.be;
> mturquette@baylibre.com; sboyd@kernel.org; robh@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
> magnus.damm@gmail.com; paul.walmsley@sifive.com; palmer@dabbelt.com;
> aou@eecs.berkeley.edu
> Cc: linux-renesas-soc@vger.kernel.org; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
> riscv@lists.infradead.org; Claudiu Beznea
> <claudiu.beznea.uj@bp.renesas.com>
> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power
> domain IDs
> 
> 
> 
> On 08.02.2024 18:28, Biju Das wrote:
> >
> >
> >> -----Original Message-----
> >> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >> Sent: Thursday, February 8, 2024 3:46 PM
> >> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add
> >> power domain IDs
> >>
> >> Hi, Biju,
> >>
> >> On 08.02.2024 16:30, Biju Das wrote:
> >>> Hi Claudiu,
> >>>
> >>> Thanks for the patch.
> >>>
> >>>> -----Original Message-----
> >>>> From: Claudiu <claudiu.beznea@tuxon.dev>
> >>>> Sent: Thursday, February 8, 2024 12:43 PM
> >>>> Subject: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power
> >>>> domain IDs
> >>>>
> >>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>>
> >>>> Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
> >>>>
> >>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>> ---
> >>>>  include/dt-bindings/clock/r9a07g043-cpg.h | 48
> >>>> +++++++++++++++++++++++
> >>>>  1 file changed, 48 insertions(+)
> >>>>
> >>>> diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h
> >>>> b/include/dt- bindings/clock/r9a07g043-cpg.h index
> >>>> 77cde8effdc7..eabfeec7ac37
> >>>> 100644
> >>>> --- a/include/dt-bindings/clock/r9a07g043-cpg.h
> >>>> +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
> >>>> @@ -200,5 +200,53 @@
> >>>>  #define R9A07G043_AX45MP_CORE0_RESETN	78	/* RZ/Five Only */
> >>>>  #define R9A07G043_IAX45_RESETN		79	/* RZ/Five Only */
> >>>>
> >>>> +/* Power domain IDs. */
> >>>> +#define R9A07G043_PD_ALWAYS_ON		0
> >>>> +#define R9A07G043_PD_GIC		1
> >>>> +#define R9A07G043_PD_IA55		2
> >>>> +#define R9A07G043_PD_MHU		3
> >>>> +#define R9A07G043_PD_CORESIGHT		4
> >>>> +#define R9A07G043_PD_SYC		5
> >>>> +#define R9A07G043_PD_DMAC		6
> >>>> +#define R9A07G043_PD_GTM0		7
> >>>> +#define R9A07G043_PD_GTM1		8
> >>>> +#define R9A07G043_PD_GTM2		9
> >>>> +#define R9A07G043_PD_MTU		10
> >>>> +#define R9A07G043_PD_POE3		11
> >>>> +#define R9A07G043_PD_WDT0		12
> >>>> +#define R9A07G043_PD_SPI		13
> >>>> +#define R9A07G043_PD_SDHI0		14
> >>>> +#define R9A07G043_PD_SDHI1		15
> >>>> +#define R9A07G043_PD_ISU		16
> >>>> +#define R9A07G043_PD_CRU		17
> >>>> +#define R9A07G043_PD_LCDC		18
> >>>> +#define R9A07G043_PD_SSI0		19
> >>>> +#define R9A07G043_PD_SSI1		20
> >>>> +#define R9A07G043_PD_SSI2		21
> >>>> +#define R9A07G043_PD_SSI3		22
> >>>> +#define R9A07G043_PD_SRC		23
> >>>> +#define R9A07G043_PD_USB0		24
> >>>> +#define R9A07G043_PD_USB1		25
> >>>> +#define R9A07G043_PD_USB_PHY		26
> >>>> +#define R9A07G043_PD_ETHER0		27
> >>>> +#define R9A07G043_PD_ETHER1		28
> >>>> +#define R9A07G043_PD_I2C0		29
> >>>> +#define R9A07G043_PD_I2C1		30
> >>>> +#define R9A07G043_PD_I2C2		31
> >>>> +#define R9A07G043_PD_I2C3		32
> >>>> +#define R9A07G043_PD_SCIF0		33
> >>>> +#define R9A07G043_PD_SCIF1		34
> >>>> +#define R9A07G043_PD_SCIF2		35
> >>>> +#define R9A07G043_PD_SCIF3		36
> >>>> +#define R9A07G043_PD_SCIF4		37
> >>>> +#define R9A07G043_PD_SCI0		38
> >>>> +#define R9A07G043_PD_SCI1		39
> >>>> +#define R9A07G043_PD_IRDA		40
> >>>> +#define R9A07G043_PD_RSPI0		41
> >>>> +#define R9A07G043_PD_RSPI1		42
> >>>> +#define R9A07G043_PD_RSPI2		43
> >>>> +#define R9A07G043_PD_CANFD		44
> >>>> +#define R9A07G043_PD_ADC		45
> >>>> +#define R9A07G043_PD_TSU		46
> >>>
> >>> Not sure from "Table 42.3 Registers for Module Standby Mode"
> >>>
> >>> Power domain ID has to be based on CPG_BUS_***_MSTOP or
> >>> CPG_CLKON_*** As former reduces number of IDs??
> >>
> >> If I understand correctly your point here, you want me to describe PM
> >> domain in DT with something like:
> >>
> >> power-domains = <&cpg CPG_BUS_X_MSTOP>;
> >
> > MSTOP bits are distinct for each IP.
> >
> > <&cpg CPG_BUS_MCPU1_MSTOP x>; x =1..9
> >
> > 2=MTU IP
> >
> > 4= GPT
> >
> > etc...
> >
> > Is it something work??
> 
> It might work. But:
> 
> - you have to consider that some IPs have more than one MSTOP bit, thus,
> do
>   we want to uniquely identify these with all MSTOP bits (thus the 2nd
> cell
>   being a bitmask) or only one is enough?

We can have an encoding in that case 8:16 24 bit entries

> - some HW blocks (e.g. OTFDE_DDR) have no MSTOP bits associated (as of my
>   current research), so, only PWRDN

Why do we want to add power domain support for DDR?

> - some HW blocks have both MSTOP and PWRDN

That will be an array right?

> - if future hardware implementation will spread the MSTOP bits for one IP
>   to more than one register then this proposal will not work

That will be an array right?

Cheers,
Biju

Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs

[claudiu beznea]

Hi, Biju,

On 08.02.2024 21:20, Biju Das wrote:
> 
> 
>> -----Original Message-----
>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>> Sent: Thursday, February 8, 2024 4:53 PM
>> To: Biju Das <biju.das.jz@bp.renesas.com>; geert+renesas@glider.be;
>> mturquette@baylibre.com; sboyd@kernel.org; robh@kernel.org;
>> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
>> magnus.damm@gmail.com; paul.walmsley@sifive.com; palmer@dabbelt.com;
>> aou@eecs.berkeley.edu
>> Cc: linux-renesas-soc@vger.kernel.org; linux-clk@vger.kernel.org;
>> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
>> riscv@lists.infradead.org; Claudiu Beznea
>> <claudiu.beznea.uj@bp.renesas.com>
>> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power
>> domain IDs
>>
>>
>>
>> On 08.02.2024 18:28, Biju Das wrote:
>>>
>>>
>>>> -----Original Message-----
>>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>>>> Sent: Thursday, February 8, 2024 3:46 PM
>>>> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add
>>>> power domain IDs
>>>>
>>>> Hi, Biju,
>>>>
>>>> On 08.02.2024 16:30, Biju Das wrote:
>>>>> Hi Claudiu,
>>>>>
>>>>> Thanks for the patch.
>>>>>
>>>>>> -----Original Message-----
>>>>>> From: Claudiu <claudiu.beznea@tuxon.dev>
>>>>>> Sent: Thursday, February 8, 2024 12:43 PM
>>>>>> Subject: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power
>>>>>> domain IDs
>>>>>>
>>>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>>>
>>>>>> Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
>>>>>>
>>>>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>>> ---
>>>>>>  include/dt-bindings/clock/r9a07g043-cpg.h | 48
>>>>>> +++++++++++++++++++++++
>>>>>>  1 file changed, 48 insertions(+)
>>>>>>
>>>>>> diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h
>>>>>> b/include/dt- bindings/clock/r9a07g043-cpg.h index
>>>>>> 77cde8effdc7..eabfeec7ac37
>>>>>> 100644
>>>>>> --- a/include/dt-bindings/clock/r9a07g043-cpg.h
>>>>>> +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
>>>>>> @@ -200,5 +200,53 @@
>>>>>>  #define R9A07G043_AX45MP_CORE0_RESETN	78	/* RZ/Five Only */
>>>>>>  #define R9A07G043_IAX45_RESETN		79	/* RZ/Five Only */
>>>>>>
>>>>>> +/* Power domain IDs. */
>>>>>> +#define R9A07G043_PD_ALWAYS_ON		0
>>>>>> +#define R9A07G043_PD_GIC		1
>>>>>> +#define R9A07G043_PD_IA55		2
>>>>>> +#define R9A07G043_PD_MHU		3
>>>>>> +#define R9A07G043_PD_CORESIGHT		4
>>>>>> +#define R9A07G043_PD_SYC		5
>>>>>> +#define R9A07G043_PD_DMAC		6
>>>>>> +#define R9A07G043_PD_GTM0		7
>>>>>> +#define R9A07G043_PD_GTM1		8
>>>>>> +#define R9A07G043_PD_GTM2		9
>>>>>> +#define R9A07G043_PD_MTU		10
>>>>>> +#define R9A07G043_PD_POE3		11
>>>>>> +#define R9A07G043_PD_WDT0		12
>>>>>> +#define R9A07G043_PD_SPI		13
>>>>>> +#define R9A07G043_PD_SDHI0		14
>>>>>> +#define R9A07G043_PD_SDHI1		15
>>>>>> +#define R9A07G043_PD_ISU		16
>>>>>> +#define R9A07G043_PD_CRU		17
>>>>>> +#define R9A07G043_PD_LCDC		18
>>>>>> +#define R9A07G043_PD_SSI0		19
>>>>>> +#define R9A07G043_PD_SSI1		20
>>>>>> +#define R9A07G043_PD_SSI2		21
>>>>>> +#define R9A07G043_PD_SSI3		22
>>>>>> +#define R9A07G043_PD_SRC		23
>>>>>> +#define R9A07G043_PD_USB0		24
>>>>>> +#define R9A07G043_PD_USB1		25
>>>>>> +#define R9A07G043_PD_USB_PHY		26
>>>>>> +#define R9A07G043_PD_ETHER0		27
>>>>>> +#define R9A07G043_PD_ETHER1		28
>>>>>> +#define R9A07G043_PD_I2C0		29
>>>>>> +#define R9A07G043_PD_I2C1		30
>>>>>> +#define R9A07G043_PD_I2C2		31
>>>>>> +#define R9A07G043_PD_I2C3		32
>>>>>> +#define R9A07G043_PD_SCIF0		33
>>>>>> +#define R9A07G043_PD_SCIF1		34
>>>>>> +#define R9A07G043_PD_SCIF2		35
>>>>>> +#define R9A07G043_PD_SCIF3		36
>>>>>> +#define R9A07G043_PD_SCIF4		37
>>>>>> +#define R9A07G043_PD_SCI0		38
>>>>>> +#define R9A07G043_PD_SCI1		39
>>>>>> +#define R9A07G043_PD_IRDA		40
>>>>>> +#define R9A07G043_PD_RSPI0		41
>>>>>> +#define R9A07G043_PD_RSPI1		42
>>>>>> +#define R9A07G043_PD_RSPI2		43
>>>>>> +#define R9A07G043_PD_CANFD		44
>>>>>> +#define R9A07G043_PD_ADC		45
>>>>>> +#define R9A07G043_PD_TSU		46
>>>>>
>>>>> Not sure from "Table 42.3 Registers for Module Standby Mode"
>>>>>
>>>>> Power domain ID has to be based on CPG_BUS_***_MSTOP or
>>>>> CPG_CLKON_*** As former reduces number of IDs??
>>>>
>>>> If I understand correctly your point here, you want me to describe PM
>>>> domain in DT with something like:
>>>>
>>>> power-domains = <&cpg CPG_BUS_X_MSTOP>;
>>>
>>> MSTOP bits are distinct for each IP.
>>>
>>> <&cpg CPG_BUS_MCPU1_MSTOP x>; x =1..9
>>>
>>> 2=MTU IP
>>>
>>> 4= GPT
>>>
>>> etc...
>>>
>>> Is it something work??
>>
>> It might work. But:
>>
>> - you have to consider that some IPs have more than one MSTOP bit, thus,
>> do
>>   we want to uniquely identify these with all MSTOP bits (thus the 2nd
>> cell
>>   being a bitmask) or only one is enough?
> 
> We can have an encoding in that case 8:16 24 bit entries

I consider this complicates the bindings. I don't consider this is the way
going forward. But I may be wrong. I'll let Geert to give his opinion on it
and change it afterwards, if any.

> 
>> - some HW blocks (e.g. OTFDE_DDR) have no MSTOP bits associated (as of my
>>   current research), so, only PWRDN
> 
> Why do we want to add power domain support for DDR?

To power it up (in case bootloader does any settings in this area) such
that the system will not block while booting.

It is explained in cover letter:

The current DT
bindings were updated with module IDs for the modules listed in tables
with name "Registers for Module Standby Mode" (see HW manual) exception
being RZ/G3S where, *due to the power down functionality*, the DDR,
TZCDDR, OTFDE_DDR were also added, to avoid system being blocked due
to the following lines of code from patch 7/17.

+       /* Prepare for power down the BUSes in power down mode. */
+       if (info->pm_domain_pwrdn_mstop)
+               writel(CPG_PWRDN_MSTOP_ENABLE, priv->base + CPG_PWRDN_MSTOP);

> 
>> - some HW blocks have both MSTOP and PWRDN
> 
> That will be an array right?

I'm not sure what you want to say here.

> 
>> - if future hardware implementation will spread the MSTOP bits for one IP
>>   to more than one register then this proposal will not work
> 
> That will be an array right?

Same here.

Thank you,
Claudiu Beznea

> 
> Cheers,
> Biju

RE: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs

[Biju Das]

Hi Claudiu,

> -----Original Message-----
> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> Sent: Monday, February 12, 2024 8:02 AM
> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power
> domain IDs
> 
> Hi, Biju,
> 
> On 08.02.2024 21:20, Biju Das wrote:
> >
> >
> >> -----Original Message-----
> >> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >> Sent: Thursday, February 8, 2024 4:53 PM
> >> To: Biju Das <biju.das.jz@bp.renesas.com>; geert+renesas@glider.be;
> >> mturquette@baylibre.com; sboyd@kernel.org; robh@kernel.org;
> >> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
> >> magnus.damm@gmail.com; paul.walmsley@sifive.com; palmer@dabbelt.com;
> >> aou@eecs.berkeley.edu
> >> Cc: linux-renesas-soc@vger.kernel.org; linux-clk@vger.kernel.org;
> >> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
> >> riscv@lists.infradead.org; Claudiu Beznea
> >> <claudiu.beznea.uj@bp.renesas.com>
> >> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add
> >> power domain IDs
> >>
> >>
> >>
> >> On 08.02.2024 18:28, Biju Das wrote:
> >>>
> >>>
> >>>> -----Original Message-----
> >>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >>>> Sent: Thursday, February 8, 2024 3:46 PM
> >>>> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add
> >>>> power domain IDs
> >>>>
> >>>> Hi, Biju,
> >>>>
> >>>> On 08.02.2024 16:30, Biju Das wrote:
> >>>>> Hi Claudiu,
> >>>>>
> >>>>> Thanks for the patch.
> >>>>>
> >>>>>> -----Original Message-----
> >>>>>> From: Claudiu <claudiu.beznea@tuxon.dev>
> >>>>>> Sent: Thursday, February 8, 2024 12:43 PM
> >>>>>> Subject: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add
> >>>>>> power domain IDs
> >>>>>>
> >>>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>>>>
> >>>>>> Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
> >>>>>>
> >>>>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>>>> ---
> >>>>>>  include/dt-bindings/clock/r9a07g043-cpg.h | 48
> >>>>>> +++++++++++++++++++++++
> >>>>>>  1 file changed, 48 insertions(+)
> >>>>>>
> >>>>>> diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h
> >>>>>> b/include/dt- bindings/clock/r9a07g043-cpg.h index
> >>>>>> 77cde8effdc7..eabfeec7ac37
> >>>>>> 100644
> >>>>>> --- a/include/dt-bindings/clock/r9a07g043-cpg.h
> >>>>>> +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
> >>>>>> @@ -200,5 +200,53 @@
> >>>>>>  #define R9A07G043_AX45MP_CORE0_RESETN	78	/* RZ/Five Only */
> >>>>>>  #define R9A07G043_IAX45_RESETN		79	/* RZ/Five Only */
> >>>>>>
> >>>>>> +/* Power domain IDs. */
> >>>>>> +#define R9A07G043_PD_ALWAYS_ON		0
> >>>>>> +#define R9A07G043_PD_GIC		1
> >>>>>> +#define R9A07G043_PD_IA55		2
> >>>>>> +#define R9A07G043_PD_MHU		3
> >>>>>> +#define R9A07G043_PD_CORESIGHT		4
> >>>>>> +#define R9A07G043_PD_SYC		5
> >>>>>> +#define R9A07G043_PD_DMAC		6
> >>>>>> +#define R9A07G043_PD_GTM0		7
> >>>>>> +#define R9A07G043_PD_GTM1		8
> >>>>>> +#define R9A07G043_PD_GTM2		9
> >>>>>> +#define R9A07G043_PD_MTU		10
> >>>>>> +#define R9A07G043_PD_POE3		11
> >>>>>> +#define R9A07G043_PD_WDT0		12
> >>>>>> +#define R9A07G043_PD_SPI		13
> >>>>>> +#define R9A07G043_PD_SDHI0		14
> >>>>>> +#define R9A07G043_PD_SDHI1		15
> >>>>>> +#define R9A07G043_PD_ISU		16
> >>>>>> +#define R9A07G043_PD_CRU		17
> >>>>>> +#define R9A07G043_PD_LCDC		18
> >>>>>> +#define R9A07G043_PD_SSI0		19
> >>>>>> +#define R9A07G043_PD_SSI1		20
> >>>>>> +#define R9A07G043_PD_SSI2		21
> >>>>>> +#define R9A07G043_PD_SSI3		22
> >>>>>> +#define R9A07G043_PD_SRC		23
> >>>>>> +#define R9A07G043_PD_USB0		24
> >>>>>> +#define R9A07G043_PD_USB1		25
> >>>>>> +#define R9A07G043_PD_USB_PHY		26
> >>>>>> +#define R9A07G043_PD_ETHER0		27
> >>>>>> +#define R9A07G043_PD_ETHER1		28
> >>>>>> +#define R9A07G043_PD_I2C0		29
> >>>>>> +#define R9A07G043_PD_I2C1		30
> >>>>>> +#define R9A07G043_PD_I2C2		31
> >>>>>> +#define R9A07G043_PD_I2C3		32
> >>>>>> +#define R9A07G043_PD_SCIF0		33
> >>>>>> +#define R9A07G043_PD_SCIF1		34
> >>>>>> +#define R9A07G043_PD_SCIF2		35
> >>>>>> +#define R9A07G043_PD_SCIF3		36
> >>>>>> +#define R9A07G043_PD_SCIF4		37
> >>>>>> +#define R9A07G043_PD_SCI0		38
> >>>>>> +#define R9A07G043_PD_SCI1		39
> >>>>>> +#define R9A07G043_PD_IRDA		40
> >>>>>> +#define R9A07G043_PD_RSPI0		41
> >>>>>> +#define R9A07G043_PD_RSPI1		42
> >>>>>> +#define R9A07G043_PD_RSPI2		43
> >>>>>> +#define R9A07G043_PD_CANFD		44
> >>>>>> +#define R9A07G043_PD_ADC		45
> >>>>>> +#define R9A07G043_PD_TSU		46
> >>>>>
> >>>>> Not sure from "Table 42.3 Registers for Module Standby Mode"
> >>>>>
> >>>>> Power domain ID has to be based on CPG_BUS_***_MSTOP or
> >>>>> CPG_CLKON_*** As former reduces number of IDs??
> >>>>
> >>>> If I understand correctly your point here, you want me to describe
> >>>> PM domain in DT with something like:
> >>>>
> >>>> power-domains = <&cpg CPG_BUS_X_MSTOP>;
> >>>
> >>> MSTOP bits are distinct for each IP.
> >>>
> >>> <&cpg CPG_BUS_MCPU1_MSTOP x>; x =1..9
> >>>
> >>> 2=MTU IP
> >>>
> >>> 4= GPT
> >>>
> >>> etc...
> >>>
> >>> Is it something work??
> >>
> >> It might work. But:
> >>
> >> - you have to consider that some IPs have more than one MSTOP bit,
> >> thus, do
> >>   we want to uniquely identify these with all MSTOP bits (thus the
> >> 2nd cell
> >>   being a bitmask) or only one is enough?
> >
> > We can have an encoding in that case 8:16 24 bit entries
> 
> I consider this complicates the bindings. I don't consider this is the way
> going forward. But I may be wrong. I'll let Geert to give his opinion on
> it and change it afterwards, if any.
> 
> >
> >> - some HW blocks (e.g. OTFDE_DDR) have no MSTOP bits associated (as of
> my
> >>   current research), so, only PWRDN
> >
> > Why do we want to add power domain support for DDR?
> 
> To power it up (in case bootloader does any settings in this area) such
> that the system will not block while booting.

DDR is enabled by TF_A and is not touched by linux, so why are we adding
Power domain at all in first place. TZC DDR is not accessible in normal world.

So if you don't add DDR power domains, linux doesn't know about any thing about
and it should work like current case.

> 
> It is explained in cover letter:
> 
> The current DT
> bindings were updated with module IDs for the modules listed in tables
> with name "Registers for Module Standby Mode" (see HW manual) exception
> being RZ/G3S where, *due to the power down functionality*, the DDR,
> TZCDDR, OTFDE_DDR were also added, to avoid system being blocked due to
> the following lines of code from patch 7/17.
> 
> +       /* Prepare for power down the BUSes in power down mode. */
> +       if (info->pm_domain_pwrdn_mstop)
> +               writel(CPG_PWRDN_MSTOP_ENABLE, priv->base +
> + CPG_PWRDN_MSTOP);
> 
> >
> >> - some HW blocks have both MSTOP and PWRDN
> >
> > That will be an array right?
> 
> I'm not sure what you want to say here.

This has to be an array PM domains(multi PM domain) like clocks?

Or 

It can be  handled as sibliling power domain like sibling clocks in RZ/G2L Gbether.

Cheers,
Biju

Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs

[claudiu beznea]

On 12.02.2024 10:59, Biju Das wrote:
> Hi Claudiu,
> 
>> -----Original Message-----
>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>> Sent: Monday, February 12, 2024 8:02 AM
>> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power
>> domain IDs
>>
>> Hi, Biju,
>>
>> On 08.02.2024 21:20, Biju Das wrote:
>>>
>>>
>>>> -----Original Message-----
>>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>>>> Sent: Thursday, February 8, 2024 4:53 PM
>>>> To: Biju Das <biju.das.jz@bp.renesas.com>; geert+renesas@glider.be;
>>>> mturquette@baylibre.com; sboyd@kernel.org; robh@kernel.org;
>>>> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
>>>> magnus.damm@gmail.com; paul.walmsley@sifive.com; palmer@dabbelt.com;
>>>> aou@eecs.berkeley.edu
>>>> Cc: linux-renesas-soc@vger.kernel.org; linux-clk@vger.kernel.org;
>>>> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
>>>> riscv@lists.infradead.org; Claudiu Beznea
>>>> <claudiu.beznea.uj@bp.renesas.com>
>>>> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add
>>>> power domain IDs
>>>>
>>>>
>>>>
>>>> On 08.02.2024 18:28, Biju Das wrote:
>>>>>
>>>>>
>>>>>> -----Original Message-----
>>>>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>>>>>> Sent: Thursday, February 8, 2024 3:46 PM
>>>>>> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add
>>>>>> power domain IDs
>>>>>>
>>>>>> Hi, Biju,
>>>>>>
>>>>>> On 08.02.2024 16:30, Biju Das wrote:
>>>>>>> Hi Claudiu,
>>>>>>>
>>>>>>> Thanks for the patch.
>>>>>>>
>>>>>>>> -----Original Message-----
>>>>>>>> From: Claudiu <claudiu.beznea@tuxon.dev>
>>>>>>>> Sent: Thursday, February 8, 2024 12:43 PM
>>>>>>>> Subject: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add
>>>>>>>> power domain IDs
>>>>>>>>
>>>>>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>>>>>
>>>>>>>> Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
>>>>>>>>
>>>>>>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>>>>> ---
>>>>>>>>  include/dt-bindings/clock/r9a07g043-cpg.h | 48
>>>>>>>> +++++++++++++++++++++++
>>>>>>>>  1 file changed, 48 insertions(+)
[ ... ]

>>>>>>>> +#define R9A07G043_PD_TSU		46
>>>>>>>
>>>>>>> Not sure from "Table 42.3 Registers for Module Standby Mode"
>>>>>>>
>>>>>>> Power domain ID has to be based on CPG_BUS_***_MSTOP or
>>>>>>> CPG_CLKON_*** As former reduces number of IDs??
>>>>>>
>>>>>> If I understand correctly your point here, you want me to describe
>>>>>> PM domain in DT with something like:
>>>>>>
>>>>>> power-domains = <&cpg CPG_BUS_X_MSTOP>;
>>>>>
>>>>> MSTOP bits are distinct for each IP.
>>>>>
>>>>> <&cpg CPG_BUS_MCPU1_MSTOP x>; x =1..9
>>>>>
>>>>> 2=MTU IP
>>>>>
>>>>> 4= GPT
>>>>>
>>>>> etc...
>>>>>
>>>>> Is it something work??
>>>>
>>>> It might work. But:
>>>>
>>>> - you have to consider that some IPs have more than one MSTOP bit,
>>>> thus, do
>>>>   we want to uniquely identify these with all MSTOP bits (thus the
>>>> 2nd cell
>>>>   being a bitmask) or only one is enough?
>>>
>>> We can have an encoding in that case 8:16 24 bit entries
>>
>> I consider this complicates the bindings. I don't consider this is the way
>> going forward. But I may be wrong. I'll let Geert to give his opinion on
>> it and change it afterwards, if any.
>>
>>>
>>>> - some HW blocks (e.g. OTFDE_DDR) have no MSTOP bits associated (as of
>> my
>>>>   current research), so, only PWRDN
>>>
>>> Why do we want to add power domain support for DDR?
>>
>> To power it up (in case bootloader does any settings in this area) such
>> that the system will not block while booting.
> 
> DDR is enabled by TF_A and is not touched by linux, so why are we adding
> Power domain at all in first place. TZC DDR is not accessible in normal world.
> 
> So if you don't add DDR power domains, linux doesn't know about any thing about
> and it should work like current case.

It is related to the way MSTOP and PWRDN hardware features works together.
PWRDN allows you to save more power by setting IP specific bits in this
registers after you set the MSTOP.

OFTDE_DDR and TZCDDR have PWRDN bits dedicated as well as other IPs (e.g.
serial, ethernet, etc) in CPG_PWRDN_IP2. Setting CPG_PWRDN_MSTOP_ENABLE to
CPG_PWRDN_MSTOP applies the power down for the IPs specified in
CPG_PWRDN_{IP1, IP2}.

It may happen (as in my case) to have a bootloader that sets all the bits
in CPG_PWRD_{IP1,IP2}.

If you want to save power for the other IPs listed in CPG_PWRD_{IP1,IP2}
you have to instantiate power domains for the blocks that you don't want to
be powered down due to setting CPG_PWRDN_MSTOP_ENABLE to CPG_PWRDN_MSTOP,
to power them up. Otherwise the system will block when setting
CPG_PWRDN_MSTOP_ENABLE to CPG_PWRDN_MSTOP (if bootloaders previously did
some settings in the above specified registers).

Hope it was clear.

Thank you,
Claudiu Beznea

> 
>>
>> It is explained in cover letter:
>>
>> The current DT
>> bindings were updated with module IDs for the modules listed in tables
>> with name "Registers for Module Standby Mode" (see HW manual) exception
>> being RZ/G3S where, *due to the power down functionality*, the DDR,
>> TZCDDR, OTFDE_DDR were also added, to avoid system being blocked due to
>> the following lines of code from patch 7/17.
>>
>> +       /* Prepare for power down the BUSes in power down mode. */
>> +       if (info->pm_domain_pwrdn_mstop)
>> +               writel(CPG_PWRDN_MSTOP_ENABLE, priv->base +
>> + CPG_PWRDN_MSTOP);
>>
>>>
>>>> - some HW blocks have both MSTOP and PWRDN
>>>
>>> That will be an array right?
>>
>> I'm not sure what you want to say here.
> 
> This has to be an array PM domains(multi PM domain) like clocks?
> 
> Or 
> 
> It can be  handled as sibliling power domain like sibling clocks in RZ/G2L Gbether.
> 
> Cheers,
> Biju

RE: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs

[Biju Das]

Hi Claudiu,

> -----Original Message-----
> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> Sent: Monday, February 12, 2024 10:17 AM
> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power
> domain IDs
> 
> 
> 
> On 12.02.2024 10:59, Biju Das wrote:
> > Hi Claudiu,
> >
> >> -----Original Message-----
> >> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >> Sent: Monday, February 12, 2024 8:02 AM
> >> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add
> >> power domain IDs
> >>
> >> Hi, Biju,
> >>
> >> On 08.02.2024 21:20, Biju Das wrote:
> >>>
> >>>
> >>>> -----Original Message-----
> >>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >>>> Sent: Thursday, February 8, 2024 4:53 PM
> >>>> To: Biju Das <biju.das.jz@bp.renesas.com>; geert+renesas@glider.be;
> >>>> mturquette@baylibre.com; sboyd@kernel.org; robh@kernel.org;
> >>>> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
> >>>> magnus.damm@gmail.com; paul.walmsley@sifive.com;
> >>>> palmer@dabbelt.com; aou@eecs.berkeley.edu
> >>>> Cc: linux-renesas-soc@vger.kernel.org; linux-clk@vger.kernel.org;
> >>>> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
> >>>> riscv@lists.infradead.org; Claudiu Beznea
> >>>> <claudiu.beznea.uj@bp.renesas.com>
> >>>> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add
> >>>> power domain IDs
> >>>>
> >>>>
> >>>>
> >>>> On 08.02.2024 18:28, Biju Das wrote:
> >>>>>
> >>>>>
> >>>>>> -----Original Message-----
> >>>>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >>>>>> Sent: Thursday, February 8, 2024 3:46 PM
> >>>>>> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add
> >>>>>> power domain IDs
> >>>>>>
> >>>>>> Hi, Biju,
> >>>>>>
> >>>>>> On 08.02.2024 16:30, Biju Das wrote:
> >>>>>>> Hi Claudiu,
> >>>>>>>
> >>>>>>> Thanks for the patch.
> >>>>>>>
> >>>>>>>> -----Original Message-----
> >>>>>>>> From: Claudiu <claudiu.beznea@tuxon.dev>
> >>>>>>>> Sent: Thursday, February 8, 2024 12:43 PM
> >>>>>>>> Subject: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add
> >>>>>>>> power domain IDs
> >>>>>>>>
> >>>>>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>>>>>>
> >>>>>>>> Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
> >>>>>>>>
> >>>>>>>> Signed-off-by: Claudiu Beznea
> >>>>>>>> <claudiu.beznea.uj@bp.renesas.com>
> >>>>>>>> ---
> >>>>>>>>  include/dt-bindings/clock/r9a07g043-cpg.h | 48
> >>>>>>>> +++++++++++++++++++++++
> >>>>>>>>  1 file changed, 48 insertions(+)
> [ ... ]
> 
> >>>>>>>> +#define R9A07G043_PD_TSU		46
> >>>>>>>
> >>>>>>> Not sure from "Table 42.3 Registers for Module Standby Mode"
> >>>>>>>
> >>>>>>> Power domain ID has to be based on CPG_BUS_***_MSTOP or
> >>>>>>> CPG_CLKON_*** As former reduces number of IDs??
> >>>>>>
> >>>>>> If I understand correctly your point here, you want me to
> >>>>>> describe PM domain in DT with something like:
> >>>>>>
> >>>>>> power-domains = <&cpg CPG_BUS_X_MSTOP>;
> >>>>>
> >>>>> MSTOP bits are distinct for each IP.
> >>>>>
> >>>>> <&cpg CPG_BUS_MCPU1_MSTOP x>; x =1..9
> >>>>>
> >>>>> 2=MTU IP
> >>>>>
> >>>>> 4= GPT
> >>>>>
> >>>>> etc...
> >>>>>
> >>>>> Is it something work??
> >>>>
> >>>> It might work. But:
> >>>>
> >>>> - you have to consider that some IPs have more than one MSTOP bit,
> >>>> thus, do
> >>>>   we want to uniquely identify these with all MSTOP bits (thus the
> >>>> 2nd cell
> >>>>   being a bitmask) or only one is enough?
> >>>
> >>> We can have an encoding in that case 8:16 24 bit entries
> >>
> >> I consider this complicates the bindings. I don't consider this is
> >> the way going forward. But I may be wrong. I'll let Geert to give his
> >> opinion on it and change it afterwards, if any.
> >>
> >>>
> >>>> - some HW blocks (e.g. OTFDE_DDR) have no MSTOP bits associated (as
> >>>> of
> >> my
> >>>>   current research), so, only PWRDN
> >>>
> >>> Why do we want to add power domain support for DDR?
> >>
> >> To power it up (in case bootloader does any settings in this area)
> >> such that the system will not block while booting.
> >
> > DDR is enabled by TF_A and is not touched by linux, so why are we
> > adding Power domain at all in first place. TZC DDR is not accessible in
> normal world.
> >
> > So if you don't add DDR power domains, linux doesn't know about any
> > thing about and it should work like current case.
> 
> It is related to the way MSTOP and PWRDN hardware features works together.
> PWRDN allows you to save more power by setting IP specific bits in this
> registers after you set the MSTOP.
> 
> OFTDE_DDR and TZCDDR have PWRDN bits dedicated as well as other IPs (e.g.
> serial, ethernet, etc) in CPG_PWRDN_IP2. Setting CPG_PWRDN_MSTOP_ENABLE to
> CPG_PWRDN_MSTOP applies the power down for the IPs specified in
> CPG_PWRDN_{IP1, IP2}.
> 
> It may happen (as in my case) to have a bootloader that sets all the bits
> in CPG_PWRD_{IP1,IP2}.
> 
> If you want to save power for the other IPs listed in CPG_PWRD_{IP1,IP2}
> you have to instantiate power domains for the blocks that you don't want
> to be powered down due to setting CPG_PWRDN_MSTOP_ENABLE to
> CPG_PWRDN_MSTOP, to power them up. Otherwise the system will block when
> setting CPG_PWRDN_MSTOP_ENABLE to CPG_PWRDN_MSTOP (if bootloaders
> previously did some settings in the above specified registers).
> 
> Hope it was clear.

OK got it, Basically you are saying linux PM messes up the CPG_PWRDN_IP2 bits({0,1}
set by TF_A for DDR/TZC DDR and leading to boot failure.

Cheers,
Biju

Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs

[claudiu beznea]

On 12.02.2024 10:59, Biju Das wrote:
> Hi Claudiu,
> 
>> -----Original Message-----
>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>> Sent: Monday, February 12, 2024 8:02 AM
>> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power
>> domain IDs
>>
>> Hi, Biju,
>>
>> On 08.02.2024 21:20, Biju Das wrote:
>>>
>>>
>>>> -----Original Message-----
>>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>>>> Sent: Thursday, February 8, 2024 4:53 PM
>>>> To: Biju Das <biju.das.jz@bp.renesas.com>; geert+renesas@glider.be;
>>>> mturquette@baylibre.com; sboyd@kernel.org; robh@kernel.org;
>>>> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
>>>> magnus.damm@gmail.com; paul.walmsley@sifive.com; palmer@dabbelt.com;
>>>> aou@eecs.berkeley.edu
>>>> Cc: linux-renesas-soc@vger.kernel.org; linux-clk@vger.kernel.org;
>>>> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
>>>> riscv@lists.infradead.org; Claudiu Beznea
>>>> <claudiu.beznea.uj@bp.renesas.com>
>>>> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add
>>>> power domain IDs
>>>>
>>>>
>>>>
>>>> On 08.02.2024 18:28, Biju Das wrote:
>>>>>
>>>>>
>>>>>> -----Original Message-----
>>>>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>>>>>> Sent: Thursday, February 8, 2024 3:46 PM
>>>>>> Subject: Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add
>>>>>> power domain IDs
>>>>>>
>>>>>> Hi, Biju,
>>>>>>
>>>>>> On 08.02.2024 16:30, Biju Das wrote:
>>>>>>> Hi Claudiu,
>>>>>>>
>>>>>>> Thanks for the patch.
>>>>>>>
>>>>>>>> -----Original Message-----
>>>>>>>> From: Claudiu <claudiu.beznea@tuxon.dev>
>>>>>>>> Sent: Thursday, February 8, 2024 12:43 PM
>>>>>>>> Subject: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add
>>>>>>>> power domain IDs
>>>>>>>>
>>>>>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>>>>>
>>>>>>>> Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
>>>>>>>>
>>>>>>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>>>>> ---
>>>>>>>>  include/dt-bindings/clock/r9a07g043-cpg.h | 48
>>>>>>>> +++++++++++++++++++++++
>>>>>>>>  1 file changed, 48 insertions(+)
>>>>>>>>
>>>>>>>> diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h
>>>>>>>> b/include/dt- bindings/clock/r9a07g043-cpg.h index
>>>>>>>> 77cde8effdc7..eabfeec7ac37
>>>>>>>> 100644
>>>>>>>> --- a/include/dt-bindings/clock/r9a07g043-cpg.h
>>>>>>>> +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
>>>>>>>> @@ -200,5 +200,53 @@
>>>>>>>>  #define R9A07G043_AX45MP_CORE0_RESETN	78	/* RZ/Five Only */
>>>>>>>>  #define R9A07G043_IAX45_RESETN		79	/* RZ/Five Only */
>>>>>>>>
>>>>>>>> +/* Power domain IDs. */
>>>>>>>> +#define R9A07G043_PD_ALWAYS_ON		0
>>>>>>>> +#define R9A07G043_PD_GIC		1
>>>>>>>> +#define R9A07G043_PD_IA55		2
>>>>>>>> +#define R9A07G043_PD_MHU		3
>>>>>>>> +#define R9A07G043_PD_CORESIGHT		4
>>>>>>>> +#define R9A07G043_PD_SYC		5
>>>>>>>> +#define R9A07G043_PD_DMAC		6
>>>>>>>> +#define R9A07G043_PD_GTM0		7
>>>>>>>> +#define R9A07G043_PD_GTM1		8
>>>>>>>> +#define R9A07G043_PD_GTM2		9
>>>>>>>> +#define R9A07G043_PD_MTU		10
>>>>>>>> +#define R9A07G043_PD_POE3		11
>>>>>>>> +#define R9A07G043_PD_WDT0		12
>>>>>>>> +#define R9A07G043_PD_SPI		13
>>>>>>>> +#define R9A07G043_PD_SDHI0		14
>>>>>>>> +#define R9A07G043_PD_SDHI1		15
>>>>>>>> +#define R9A07G043_PD_ISU		16
>>>>>>>> +#define R9A07G043_PD_CRU		17
>>>>>>>> +#define R9A07G043_PD_LCDC		18
>>>>>>>> +#define R9A07G043_PD_SSI0		19
>>>>>>>> +#define R9A07G043_PD_SSI1		20
>>>>>>>> +#define R9A07G043_PD_SSI2		21
>>>>>>>> +#define R9A07G043_PD_SSI3		22
>>>>>>>> +#define R9A07G043_PD_SRC		23
>>>>>>>> +#define R9A07G043_PD_USB0		24
>>>>>>>> +#define R9A07G043_PD_USB1		25
>>>>>>>> +#define R9A07G043_PD_USB_PHY		26
>>>>>>>> +#define R9A07G043_PD_ETHER0		27
>>>>>>>> +#define R9A07G043_PD_ETHER1		28
>>>>>>>> +#define R9A07G043_PD_I2C0		29
>>>>>>>> +#define R9A07G043_PD_I2C1		30
>>>>>>>> +#define R9A07G043_PD_I2C2		31
>>>>>>>> +#define R9A07G043_PD_I2C3		32
>>>>>>>> +#define R9A07G043_PD_SCIF0		33
>>>>>>>> +#define R9A07G043_PD_SCIF1		34
>>>>>>>> +#define R9A07G043_PD_SCIF2		35
>>>>>>>> +#define R9A07G043_PD_SCIF3		36
>>>>>>>> +#define R9A07G043_PD_SCIF4		37
>>>>>>>> +#define R9A07G043_PD_SCI0		38
>>>>>>>> +#define R9A07G043_PD_SCI1		39
>>>>>>>> +#define R9A07G043_PD_IRDA		40
>>>>>>>> +#define R9A07G043_PD_RSPI0		41
>>>>>>>> +#define R9A07G043_PD_RSPI1		42
>>>>>>>> +#define R9A07G043_PD_RSPI2		43
>>>>>>>> +#define R9A07G043_PD_CANFD		44
>>>>>>>> +#define R9A07G043_PD_ADC		45
>>>>>>>> +#define R9A07G043_PD_TSU		46
>>>>>>>
>>>>>>> Not sure from "Table 42.3 Registers for Module Standby Mode"
>>>>>>>
>>>>>>> Power domain ID has to be based on CPG_BUS_***_MSTOP or
>>>>>>> CPG_CLKON_*** As former reduces number of IDs??
>>>>>>
>>>>>> If I understand correctly your point here, you want me to describe
>>>>>> PM domain in DT with something like:
>>>>>>
>>>>>> power-domains = <&cpg CPG_BUS_X_MSTOP>;
>>>>>
>>>>> MSTOP bits are distinct for each IP.
>>>>>
>>>>> <&cpg CPG_BUS_MCPU1_MSTOP x>; x =1..9
>>>>>
>>>>> 2=MTU IP
>>>>>
>>>>> 4= GPT
>>>>>
>>>>> etc...
>>>>>
>>>>> Is it something work??
>>>>
>>>> It might work. But:
>>>>
>>>> - you have to consider that some IPs have more than one MSTOP bit,
>>>> thus, do
>>>>   we want to uniquely identify these with all MSTOP bits (thus the
>>>> 2nd cell
>>>>   being a bitmask) or only one is enough?
>>>
>>> We can have an encoding in that case 8:16 24 bit entries
>>
>> I consider this complicates the bindings. I don't consider this is the way
>> going forward. But I may be wrong. I'll let Geert to give his opinion on
>> it and change it afterwards, if any.
>>
>>>
>>>> - some HW blocks (e.g. OTFDE_DDR) have no MSTOP bits associated (as of
>> my
>>>>   current research), so, only PWRDN
>>>
>>> Why do we want to add power domain support for DDR?
>>
>> To power it up (in case bootloader does any settings in this area) such
>> that the system will not block while booting.
> 
> DDR is enabled by TF_A and is not touched by linux, so why are we adding
> Power domain at all in first place. TZC DDR is not accessible in normal world.
> 
> So if you don't add DDR power domains, linux doesn't know about any thing about
> and it should work like current case.
> 
>>
>> It is explained in cover letter:
>>
>> The current DT
>> bindings were updated with module IDs for the modules listed in tables
>> with name "Registers for Module Standby Mode" (see HW manual) exception
>> being RZ/G3S where, *due to the power down functionality*, the DDR,
>> TZCDDR, OTFDE_DDR were also added, to avoid system being blocked due to
>> the following lines of code from patch 7/17.
>>
>> +       /* Prepare for power down the BUSes in power down mode. */
>> +       if (info->pm_domain_pwrdn_mstop)
>> +               writel(CPG_PWRDN_MSTOP_ENABLE, priv->base +
>> + CPG_PWRDN_MSTOP);
>>
>>>
>>>> - some HW blocks have both MSTOP and PWRDN
>>>
>>> That will be an array right?
>>
>> I'm not sure what you want to say here.
> 
> This has to be an array PM domains(multi PM domain) like clocks?

Forgot to reply to this...

Yes, this should work for IPs having both MSTOP and PWRDN. It is an
alternative to the current implementation. I kept both MSTOP and PWRDN
under the control of the same PM domain in the current implementation.

But if future hardware implementation will spread the MSTOP bits for one IP
to more than one register (I don't know if this is likely to happen but it
may worth considering) then multiple MSTOP bits for the same power domain
cannot be handled by this approach and describing the domain with register
offset and bitmask.

> 
> Or 
> 
> It can be  handled as sibliling power domain like sibling clocks in RZ/G2L Gbether.

Kind of this implementation was proposed initially (linking the MSTOP to
the IP clocks inside the clock driver).

Thank you,
Claudiu Beznea

> 
> Cheers,
> Biju

Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs

[Geert Uytterhoeven]

Hi Claudiu,

On Thu, Feb 8, 2024 at 1:43 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Thanks for your patch!

> --- a/include/dt-bindings/clock/r9a07g043-cpg.h
> +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
> @@ -200,5 +200,53 @@
>  #define R9A07G043_AX45MP_CORE0_RESETN  78      /* RZ/Five Only */
>  #define R9A07G043_IAX45_RESETN         79      /* RZ/Five Only */
>
> +/* Power domain IDs. */
> +#define R9A07G043_PD_ALWAYS_ON         0
> +#define R9A07G043_PD_GIC               1

As this file is shared between RZ/G2UL and RZ/Five, R9A07G043_PD_GIC
needs an "/* RZ/G2UL Only */" comment

> +#define R9A07G043_PD_IA55              2
> +#define R9A07G043_PD_MHU               3
> +#define R9A07G043_PD_CORESIGHT         4
> +#define R9A07G043_PD_SYC               5

Likewise for the four above.

> +#define R9A07G043_PD_DMAC              6
> +#define R9A07G043_PD_GTM0              7
> +#define R9A07G043_PD_GTM1              8
> +#define R9A07G043_PD_GTM2              9
> +#define R9A07G043_PD_MTU               10
> +#define R9A07G043_PD_POE3              11
> +#define R9A07G043_PD_WDT0              12
> +#define R9A07G043_PD_SPI               13
> +#define R9A07G043_PD_SDHI0             14
> +#define R9A07G043_PD_SDHI1             15
> +#define R9A07G043_PD_ISU               16
> +#define R9A07G043_PD_CRU               17
> +#define R9A07G043_PD_LCDC              18

Likewise for the three above.

> +#define R9A07G043_PD_SSI0              19
> +#define R9A07G043_PD_SSI1              20
> +#define R9A07G043_PD_SSI2              21
> +#define R9A07G043_PD_SSI3              22
> +#define R9A07G043_PD_SRC               23
> +#define R9A07G043_PD_USB0              24
> +#define R9A07G043_PD_USB1              25
> +#define R9A07G043_PD_USB_PHY           26
> +#define R9A07G043_PD_ETHER0            27
> +#define R9A07G043_PD_ETHER1            28
> +#define R9A07G043_PD_I2C0              29
> +#define R9A07G043_PD_I2C1              30
> +#define R9A07G043_PD_I2C2              31
> +#define R9A07G043_PD_I2C3              32
> +#define R9A07G043_PD_SCIF0             33
> +#define R9A07G043_PD_SCIF1             34
> +#define R9A07G043_PD_SCIF2             35
> +#define R9A07G043_PD_SCIF3             36
> +#define R9A07G043_PD_SCIF4             37
> +#define R9A07G043_PD_SCI0              38
> +#define R9A07G043_PD_SCI1              39
> +#define R9A07G043_PD_IRDA              40
> +#define R9A07G043_PD_RSPI0             41
> +#define R9A07G043_PD_RSPI1             42
> +#define R9A07G043_PD_RSPI2             43
> +#define R9A07G043_PD_CANFD             44
> +#define R9A07G043_PD_ADC               45
> +#define R9A07G043_PD_TSU               46
>
>  #endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */

In addition, you need definitions for the modules that are only
present on RZ/Five, e.g.

    #define R9A07G043_PD_PLIC               47    /* RZ/Five Only */

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs

[claudiu beznea]

Hi, Geert,

On 16.02.2024 16:01, Geert Uytterhoeven wrote:
> Hi Claudiu,
> 
> On Thu, Feb 8, 2024 at 1:43 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Thanks for your patch!
> 
>> --- a/include/dt-bindings/clock/r9a07g043-cpg.h
>> +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
>> @@ -200,5 +200,53 @@
>>  #define R9A07G043_AX45MP_CORE0_RESETN  78      /* RZ/Five Only */
>>  #define R9A07G043_IAX45_RESETN         79      /* RZ/Five Only */
>>
>> +/* Power domain IDs. */
>> +#define R9A07G043_PD_ALWAYS_ON         0
>> +#define R9A07G043_PD_GIC               1
> 
> As this file is shared between RZ/G2UL and RZ/Five, R9A07G043_PD_GIC
> needs an "/* RZ/G2UL Only */" comment

Ok. I'll re-checked it and update. Likewise for the rest of your below points.

> 
>> +#define R9A07G043_PD_IA55              2
>> +#define R9A07G043_PD_MHU               3
>> +#define R9A07G043_PD_CORESIGHT         4
>> +#define R9A07G043_PD_SYC               5
> 
> Likewise for the four above.
> 
>> +#define R9A07G043_PD_DMAC              6
>> +#define R9A07G043_PD_GTM0              7
>> +#define R9A07G043_PD_GTM1              8
>> +#define R9A07G043_PD_GTM2              9
>> +#define R9A07G043_PD_MTU               10
>> +#define R9A07G043_PD_POE3              11
>> +#define R9A07G043_PD_WDT0              12
>> +#define R9A07G043_PD_SPI               13
>> +#define R9A07G043_PD_SDHI0             14
>> +#define R9A07G043_PD_SDHI1             15
>> +#define R9A07G043_PD_ISU               16
>> +#define R9A07G043_PD_CRU               17
>> +#define R9A07G043_PD_LCDC              18
> 
> Likewise for the three above.
> 
>> +#define R9A07G043_PD_SSI0              19
>> +#define R9A07G043_PD_SSI1              20
>> +#define R9A07G043_PD_SSI2              21
>> +#define R9A07G043_PD_SSI3              22
>> +#define R9A07G043_PD_SRC               23
>> +#define R9A07G043_PD_USB0              24
>> +#define R9A07G043_PD_USB1              25
>> +#define R9A07G043_PD_USB_PHY           26
>> +#define R9A07G043_PD_ETHER0            27
>> +#define R9A07G043_PD_ETHER1            28
>> +#define R9A07G043_PD_I2C0              29
>> +#define R9A07G043_PD_I2C1              30
>> +#define R9A07G043_PD_I2C2              31
>> +#define R9A07G043_PD_I2C3              32
>> +#define R9A07G043_PD_SCIF0             33
>> +#define R9A07G043_PD_SCIF1             34
>> +#define R9A07G043_PD_SCIF2             35
>> +#define R9A07G043_PD_SCIF3             36
>> +#define R9A07G043_PD_SCIF4             37
>> +#define R9A07G043_PD_SCI0              38
>> +#define R9A07G043_PD_SCI1              39
>> +#define R9A07G043_PD_IRDA              40
>> +#define R9A07G043_PD_RSPI0             41
>> +#define R9A07G043_PD_RSPI1             42
>> +#define R9A07G043_PD_RSPI2             43
>> +#define R9A07G043_PD_CANFD             44
>> +#define R9A07G043_PD_ADC               45
>> +#define R9A07G043_PD_TSU               46
>>
>>  #endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */
> 
> In addition, you need definitions for the modules that are only
> present on RZ/Five, e.g.
> 
>     #define R9A07G043_PD_PLIC               47    /* RZ/Five Only */
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

[PATCH 02/17] dt-bindings: clock: r9a07g044-cpg: Add power domain IDs

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Add power domain IDs for RZ/G2L (R9A07G044) SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 include/dt-bindings/clock/r9a07g044-cpg.h | 58 +++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h
index 0bb17ff1a01a..e209f96f92b7 100644
--- a/include/dt-bindings/clock/r9a07g044-cpg.h
+++ b/include/dt-bindings/clock/r9a07g044-cpg.h
@@ -217,4 +217,62 @@
 #define R9A07G044_ADC_ADRST_N		82
 #define R9A07G044_TSU_PRESETN		83
 
+/* Power domain IDs. */
+#define R9A07G044_PD_ALWAYS_ON		0
+#define R9A07G044_PD_GIC		1
+#define R9A07G044_PD_IA55		2
+#define R9A07G044_PD_MHU		3
+#define R9A07G044_PD_CORESIGHT		4
+#define R9A07G044_PD_SYC		5
+#define R9A07G044_PD_DMAC		6
+#define R9A07G044_PD_GTM0		7
+#define R9A07G044_PD_GTM1		8
+#define R9A07G044_PD_GTM2		9
+#define R9A07G044_PD_MTU		10
+#define R9A07G044_PD_POE3		11
+#define R9A07G044_PD_GPT		12
+#define R9A07G044_PD_POEGA		13
+#define R9A07G044_PD_POEGB		14
+#define R9A07G044_PD_POEGC		15
+#define R9A07G044_PD_POEGD		16
+#define R9A07G044_PD_WDT0		17
+#define R9A07G044_PD_WDT1		18
+#define R9A07G044_PD_SPI		19
+#define R9A07G044_PD_SDHI0		20
+#define R9A07G044_PD_SDHI1		21
+#define R9A07G044_PD_3DGE		22
+#define R9A07G044_PD_ISU		23
+#define R9A07G044_PD_VCPL4		24
+#define R9A07G044_PD_CRU		25
+#define R9A07G044_PD_MIPI_DSI		26
+#define R9A07G044_PD_LCDC		27
+#define R9A07G044_PD_SSI0		28
+#define R9A07G044_PD_SSI1		29
+#define R9A07G044_PD_SSI2		30
+#define R9A07G044_PD_SSI3		31
+#define R9A07G044_PD_SRC		32
+#define R9A07G044_PD_USB0		33
+#define R9A07G044_PD_USB1		34
+#define R9A07G044_PD_USB_PHY		35
+#define R9A07G044_PD_ETHER0		36
+#define R9A07G044_PD_ETHER1		37
+#define R9A07G044_PD_I2C0		38
+#define R9A07G044_PD_I2C1		39
+#define R9A07G044_PD_I2C2		40
+#define R9A07G044_PD_I2C3		41
+#define R9A07G044_PD_SCIF0		42
+#define R9A07G044_PD_SCIF1		43
+#define R9A07G044_PD_SCIF2		44
+#define R9A07G044_PD_SCIF3		45
+#define R9A07G044_PD_SCIF4		46
+#define R9A07G044_PD_SCI0		47
+#define R9A07G044_PD_SCI1		48
+#define R9A07G044_PD_IRDA		49
+#define R9A07G044_PD_RSPI0		50
+#define R9A07G044_PD_RSPI1		51
+#define R9A07G044_PD_RSPI2		52
+#define R9A07G044_PD_CANFD		53
+#define R9A07G044_PD_ADC		54
+#define R9A07G044_PD_TSU		55
+
 #endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
-- 
2.39.2

RE: [PATCH 02/17] dt-bindings: clock: r9a07g044-cpg: Add power domain IDs

[Biju Das]

Hi Claudiu,

> -----Original Message-----
> From: Claudiu <claudiu.beznea@tuxon.dev>
> Sent: Thursday, February 8, 2024 12:43 PM
> Subject: [PATCH 02/17] dt-bindings: clock: r9a07g044-cpg: Add power domain
> IDs
> 
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Add power domain IDs for RZ/G2L (R9A07G044) SoC.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>  include/dt-bindings/clock/r9a07g044-cpg.h | 58 +++++++++++++++++++++++
>  1 file changed, 58 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-
> bindings/clock/r9a07g044-cpg.h
> index 0bb17ff1a01a..e209f96f92b7 100644
> --- a/include/dt-bindings/clock/r9a07g044-cpg.h
> +++ b/include/dt-bindings/clock/r9a07g044-cpg.h
> @@ -217,4 +217,62 @@
>  #define R9A07G044_ADC_ADRST_N		82
>  #define R9A07G044_TSU_PRESETN		83
> 
> +/* Power domain IDs. */
> +#define R9A07G044_PD_ALWAYS_ON		0
> +#define R9A07G044_PD_GIC		1
> +#define R9A07G044_PD_IA55		2
> +#define R9A07G044_PD_MHU		3
> +#define R9A07G044_PD_CORESIGHT		4
> +#define R9A07G044_PD_SYC		5
> +#define R9A07G044_PD_DMAC		6
> +#define R9A07G044_PD_GTM0		7
> +#define R9A07G044_PD_GTM1		8
> +#define R9A07G044_PD_GTM2		9
> +#define R9A07G044_PD_MTU		10
> +#define R9A07G044_PD_POE3		11
> +#define R9A07G044_PD_GPT		12
> +#define R9A07G044_PD_POEGA		13
> +#define R9A07G044_PD_POEGB		14
> +#define R9A07G044_PD_POEGC		15
> +#define R9A07G044_PD_POEGD		16
> +#define R9A07G044_PD_WDT0		17
> +#define R9A07G044_PD_WDT1		18
> +#define R9A07G044_PD_SPI		19
> +#define R9A07G044_PD_SDHI0		20
> +#define R9A07G044_PD_SDHI1		21
> +#define R9A07G044_PD_3DGE		22
> +#define R9A07G044_PD_ISU		23
> +#define R9A07G044_PD_VCPL4		24
> +#define R9A07G044_PD_CRU		25
> +#define R9A07G044_PD_MIPI_DSI		26
> +#define R9A07G044_PD_LCDC		27
> +#define R9A07G044_PD_SSI0		28
> +#define R9A07G044_PD_SSI1		29
> +#define R9A07G044_PD_SSI2		30
> +#define R9A07G044_PD_SSI3		31
> +#define R9A07G044_PD_SRC		32
> +#define R9A07G044_PD_USB0		33
> +#define R9A07G044_PD_USB1		34
> +#define R9A07G044_PD_USB_PHY		35
> +#define R9A07G044_PD_ETHER0		36
> +#define R9A07G044_PD_ETHER1		37
> +#define R9A07G044_PD_I2C0		38
> +#define R9A07G044_PD_I2C1		39
> +#define R9A07G044_PD_I2C2		40
> +#define R9A07G044_PD_I2C3		41
> +#define R9A07G044_PD_SCIF0		42
> +#define R9A07G044_PD_SCIF1		43
> +#define R9A07G044_PD_SCIF2		44
> +#define R9A07G044_PD_SCIF3		45
> +#define R9A07G044_PD_SCIF4		46
> +#define R9A07G044_PD_SCI0		47
> +#define R9A07G044_PD_SCI1		48
> +#define R9A07G044_PD_IRDA		49
> +#define R9A07G044_PD_RSPI0		50
> +#define R9A07G044_PD_RSPI1		51
> +#define R9A07G044_PD_RSPI2		52
> +#define R9A07G044_PD_CANFD		53
> +#define R9A07G044_PD_ADC		54
> +#define R9A07G044_PD_TSU		55

Not sure these PD id's can be generic and used across all RZ/G2L family
devices and RZ/V2M?

Cheers,
Biju

> +
>  #endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
> --
> 2.39.2
> 

Re: [PATCH 02/17] dt-bindings: clock: r9a07g044-cpg: Add power domain IDs

[claudiu beznea]

Hi, Biju,

On 08.02.2024 16:39, Biju Das wrote:
> Hi Claudiu,
> 
>> -----Original Message-----
>> From: Claudiu <claudiu.beznea@tuxon.dev>
>> Sent: Thursday, February 8, 2024 12:43 PM
>> Subject: [PATCH 02/17] dt-bindings: clock: r9a07g044-cpg: Add power domain
>> IDs
>>
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Add power domain IDs for RZ/G2L (R9A07G044) SoC.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>> ---
>>  include/dt-bindings/clock/r9a07g044-cpg.h | 58 +++++++++++++++++++++++
>>  1 file changed, 58 insertions(+)
>>
>> diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-
>> bindings/clock/r9a07g044-cpg.h
>> index 0bb17ff1a01a..e209f96f92b7 100644
>> --- a/include/dt-bindings/clock/r9a07g044-cpg.h
>> +++ b/include/dt-bindings/clock/r9a07g044-cpg.h
>> @@ -217,4 +217,62 @@
>>  #define R9A07G044_ADC_ADRST_N		82
>>  #define R9A07G044_TSU_PRESETN		83
>>
>> +/* Power domain IDs. */
>> +#define R9A07G044_PD_ALWAYS_ON		0
>> +#define R9A07G044_PD_GIC		1
>> +#define R9A07G044_PD_IA55		2
>> +#define R9A07G044_PD_MHU		3
>> +#define R9A07G044_PD_CORESIGHT		4
>> +#define R9A07G044_PD_SYC		5
>> +#define R9A07G044_PD_DMAC		6
>> +#define R9A07G044_PD_GTM0		7
>> +#define R9A07G044_PD_GTM1		8
>> +#define R9A07G044_PD_GTM2		9
>> +#define R9A07G044_PD_MTU		10
>> +#define R9A07G044_PD_POE3		11
>> +#define R9A07G044_PD_GPT		12
>> +#define R9A07G044_PD_POEGA		13
>> +#define R9A07G044_PD_POEGB		14
>> +#define R9A07G044_PD_POEGC		15
>> +#define R9A07G044_PD_POEGD		16
>> +#define R9A07G044_PD_WDT0		17
>> +#define R9A07G044_PD_WDT1		18
>> +#define R9A07G044_PD_SPI		19
>> +#define R9A07G044_PD_SDHI0		20
>> +#define R9A07G044_PD_SDHI1		21
>> +#define R9A07G044_PD_3DGE		22
>> +#define R9A07G044_PD_ISU		23
>> +#define R9A07G044_PD_VCPL4		24
>> +#define R9A07G044_PD_CRU		25
>> +#define R9A07G044_PD_MIPI_DSI		26
>> +#define R9A07G044_PD_LCDC		27
>> +#define R9A07G044_PD_SSI0		28
>> +#define R9A07G044_PD_SSI1		29
>> +#define R9A07G044_PD_SSI2		30
>> +#define R9A07G044_PD_SSI3		31
>> +#define R9A07G044_PD_SRC		32
>> +#define R9A07G044_PD_USB0		33
>> +#define R9A07G044_PD_USB1		34
>> +#define R9A07G044_PD_USB_PHY		35
>> +#define R9A07G044_PD_ETHER0		36
>> +#define R9A07G044_PD_ETHER1		37
>> +#define R9A07G044_PD_I2C0		38
>> +#define R9A07G044_PD_I2C1		39
>> +#define R9A07G044_PD_I2C2		40
>> +#define R9A07G044_PD_I2C3		41
>> +#define R9A07G044_PD_SCIF0		42
>> +#define R9A07G044_PD_SCIF1		43
>> +#define R9A07G044_PD_SCIF2		44
>> +#define R9A07G044_PD_SCIF3		45
>> +#define R9A07G044_PD_SCIF4		46
>> +#define R9A07G044_PD_SCI0		47
>> +#define R9A07G044_PD_SCI1		48
>> +#define R9A07G044_PD_IRDA		49
>> +#define R9A07G044_PD_RSPI0		50
>> +#define R9A07G044_PD_RSPI1		51
>> +#define R9A07G044_PD_RSPI2		52
>> +#define R9A07G044_PD_CANFD		53
>> +#define R9A07G044_PD_ADC		54
>> +#define R9A07G044_PD_TSU		55
> 
> Not sure these PD id's can be generic and used across all RZ/G2L family
> devices and RZ/V2M?

That may be another approach. I chose this one to have everything SoC
specific in a single place. With this, e.g., we can have all the SCIF
related IDs grouped together (as we know from the beginning how many SCIF
blocks a SoC has):

+#define R9A07G044_PD_SCIF0		42
+#define R9A07G044_PD_SCIF1		43
+#define R9A07G044_PD_SCIF2		44
+#define R9A07G044_PD_SCIF3		45
+#define R9A07G044_PD_SCIF4		46

If a single file with all the IDs for all the SoC will be used then, as
every SoC will have a different number of SCIFs, I2Cs, RSPIs, to keep the
DT binding backward compatibility, we will end up with these IDs not being
grouped on functionality, e.g., we may end up with something like:

+#define R9A07G044_PD_I2C0		38
+#define R9A07G044_PD_I2C1		39
+#define R9A07G044_PD_I2C2		40
+#define R9A07G044_PD_I2C3		41
+#define R9A07G044_PD_SCIF0		42
+#define R9A07G044_PD_SCIF1		43
+#define R9A07G044_PD_SCIF2		44
+#define R9A07G044_PD_SCIF3		45
+#define R9A07G044_PD_SCIF4		46
+#define R9A07G044_PD_SCI0		47
+#define R9A07G044_PD_SCI1		48
+#define R9A07G044_PD_IRDA		49
+#define R9A07G044_PD_RSPI0		50
+#define R9A07G044_PD_RSPI1		51
+#define R9A07G044_PD_RSPI2		52
+#define R9A07G044_PD_CANFD		53
+#define R9A07G044_PD_ADC		54
+#define R9A07G044_PD_TSU		55

+#define R9A07G044_PD_SCIF5		56
+#define R9A07G044_PD_SCIF6		57
+#define R9A07G044_PD_I2C4		58
+#define R9A07G044_PD_RSPI3		58
+#define R9A07G044_PD_RSPI4		59

Of course, I can adjust it if Geert wants it differently.

Thank you,
Claudiu Beznea

> 
> Cheers,
> Biju
> 
>> +
>>  #endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
>> --
>> 2.39.2
>>
> 

Re: [PATCH 02/17] dt-bindings: clock: r9a07g044-cpg: Add power domain IDs

[Geert Uytterhoeven]

On Thu, Feb 8, 2024 at 1:43 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add power domain IDs for RZ/G2L (R9A07G044) SoC.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 03/17] dt-bindings: clock: r9a07g054-cpg: Add power domain IDs

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Add power domain IDs for RZ/V2L (R9A07G054) SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 include/dt-bindings/clock/r9a07g054-cpg.h | 58 +++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/include/dt-bindings/clock/r9a07g054-cpg.h b/include/dt-bindings/clock/r9a07g054-cpg.h
index 43f4dbda872c..2c99f89397c4 100644
--- a/include/dt-bindings/clock/r9a07g054-cpg.h
+++ b/include/dt-bindings/clock/r9a07g054-cpg.h
@@ -226,4 +226,62 @@
 #define R9A07G054_TSU_PRESETN		83
 #define R9A07G054_STPAI_ARESETN		84
 
+/* Power domain IDs. */
+#define R9A07G054_PD_ALWAYS_ON		0
+#define R9A07G054_PD_GIC		1
+#define R9A07G054_PD_IA55		2
+#define R9A07G054_PD_MHU		3
+#define R9A07G054_PD_CORESIGHT		4
+#define R9A07G054_PD_SYC		5
+#define R9A07G054_PD_DMAC		6
+#define R9A07G054_PD_GTM0		7
+#define R9A07G054_PD_GTM1		8
+#define R9A07G054_PD_GTM2		9
+#define R9A07G054_PD_MTU		10
+#define R9A07G054_PD_POE3		11
+#define R9A07G054_PD_GPT		12
+#define R9A07G054_PD_POEGA		13
+#define R9A07G054_PD_POEGB		14
+#define R9A07G054_PD_POEGC		15
+#define R9A07G054_PD_POEGD		16
+#define R9A07G054_PD_WDT0		17
+#define R9A07G054_PD_WDT1		18
+#define R9A07G054_PD_SPI		19
+#define R9A07G054_PD_SDHI0		20
+#define R9A07G054_PD_SDHI1		21
+#define R9A07G054_PD_3DGE		22
+#define R9A07G054_PD_ISU		23
+#define R9A07G054_PD_VCPL4		24
+#define R9A07G054_PD_CRU		25
+#define R9A07G054_PD_MIPI_DSI		26
+#define R9A07G054_PD_LCDC		27
+#define R9A07G054_PD_SSI0		28
+#define R9A07G054_PD_SSI1		29
+#define R9A07G054_PD_SSI2		30
+#define R9A07G054_PD_SSI3		31
+#define R9A07G054_PD_SRC		32
+#define R9A07G054_PD_USB0		33
+#define R9A07G054_PD_USB1		34
+#define R9A07G054_PD_USB_PHY		35
+#define R9A07G054_PD_ETHER0		36
+#define R9A07G054_PD_ETHER1		37
+#define R9A07G054_PD_I2C0		38
+#define R9A07G054_PD_I2C1		39
+#define R9A07G054_PD_I2C2		40
+#define R9A07G054_PD_I2C3		41
+#define R9A07G054_PD_SCIF0		42
+#define R9A07G054_PD_SCIF1		43
+#define R9A07G054_PD_SCIF2		44
+#define R9A07G054_PD_SCIF3		45
+#define R9A07G054_PD_SCIF4		46
+#define R9A07G054_PD_SCI0		47
+#define R9A07G054_PD_SCI1		48
+#define R9A07G054_PD_IRDA		49
+#define R9A07G054_PD_RSPI0		50
+#define R9A07G054_PD_RSPI1		51
+#define R9A07G054_PD_RSPI2		52
+#define R9A07G054_PD_CANFD		53
+#define R9A07G054_PD_ADC		54
+#define R9A07G054_PD_TSU		55
+
 #endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */
-- 
2.39.2

Re: [PATCH 03/17] dt-bindings: clock: r9a07g054-cpg: Add power domain IDs

[Geert Uytterhoeven]

Hi Claudiu,

On Thu, Feb 8, 2024 at 1:43 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add power domain IDs for RZ/V2L (R9A07G054) SoC.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Thanks for your patch!

I was a bit surprised to see no new definitions for the RZ/V2L blocks
that are not present on RZ/G2L (e.g. DRP), but the documentation agrees.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 04/17] dt-bindings: clock: r9a08g045-cpg: Add power domain IDs

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Add power domain IDs for RZ/G3S (R9A08G045) SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 include/dt-bindings/clock/r9a08g045-cpg.h | 70 +++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/include/dt-bindings/clock/r9a08g045-cpg.h b/include/dt-bindings/clock/r9a08g045-cpg.h
index 410725b778a8..8281e9caf3a9 100644
--- a/include/dt-bindings/clock/r9a08g045-cpg.h
+++ b/include/dt-bindings/clock/r9a08g045-cpg.h
@@ -239,4 +239,74 @@
 #define R9A08G045_I3C_PRESETN		92
 #define R9A08G045_VBAT_BRESETN		93
 
+/* Power domain IDs. */
+#define R9A08G045_PD_ALWAYS_ON		0
+#define R9A08G045_PD_GIC		1
+#define R9A08G045_PD_IA55		2
+#define R9A08G045_PD_MHU		3
+#define R9A08G045_PD_CORESIGHT		4
+#define R9A08G045_PD_SYC		5
+#define R9A08G045_PD_DMAC		6
+#define R9A08G045_PD_GTM0		7
+#define R9A08G045_PD_GTM1		8
+#define R9A08G045_PD_GTM2		9
+#define R9A08G045_PD_GTM3		10
+#define R9A08G045_PD_GTM4		11
+#define R9A08G045_PD_GTM5		12
+#define R9A08G045_PD_GTM6		13
+#define R9A08G045_PD_GTM7		14
+#define R9A08G045_PD_MTU		15
+#define R9A08G045_PD_POE3		16
+#define R9A08G045_PD_GPT		17
+#define R9A08G045_PD_POEGA		18
+#define R9A08G045_PD_POEGB		19
+#define R9A08G045_PD_POEGC		20
+#define R9A08G045_PD_POEGD		21
+#define R9A08G045_PD_WDT0		22
+#define R9A08G045_PD_XSPI		23
+#define R9A08G045_PD_SDHI0		24
+#define R9A08G045_PD_SDHI1		25
+#define R9A08G045_PD_SDHI2		26
+#define R9A08G045_PD_SSI0		27
+#define R9A08G045_PD_SSI1		28
+#define R9A08G045_PD_SSI2		29
+#define R9A08G045_PD_SSI3		30
+#define R9A08G045_PD_SRC		31
+#define R9A08G045_PD_USB0		32
+#define R9A08G045_PD_USB1		33
+#define R9A08G045_PD_USB_PHY		34
+#define R9A08G045_PD_ETHER0		35
+#define R9A08G045_PD_ETHER1		36
+#define R9A08G045_PD_I2C0		37
+#define R9A08G045_PD_I2C1		38
+#define R9A08G045_PD_I2C2		39
+#define R9A08G045_PD_I2C3		40
+#define R9A08G045_PD_SCIF0		41
+#define R9A08G045_PD_SCIF1		42
+#define R9A08G045_PD_SCIF2		43
+#define R9A08G045_PD_SCIF3		44
+#define R9A08G045_PD_SCIF4		45
+#define R9A08G045_PD_SCIF5		46
+#define R9A08G045_PD_SCI0		47
+#define R9A08G045_PD_SCI1		48
+#define R9A08G045_PD_IRDA		49
+#define R9A08G045_PD_RSPI0		50
+#define R9A08G045_PD_RSPI1		51
+#define R9A08G045_PD_RSPI2		52
+#define R9A08G045_PD_RSPI3		53
+#define R9A08G045_PD_RSPI4		54
+#define R9A08G045_PD_CANFD		55
+#define R9A08G045_PD_ADC		56
+#define R9A08G045_PD_TSU		57
+#define R9A08G045_PD_OCTA		58
+#define R9A08G045_PD_PDM		59
+#define R9A08G045_PD_PCI		60
+#define R9A08G045_PD_SPDIF		61
+#define R9A08G045_PD_I3C		62
+#define R9A08G045_PD_VBAT		63
+
+#define R9A08G045_PD_DDR		64
+#define R9A08G045_PD_TZCDDR		65
+#define R9A08G045_PD_OTFDE_DDR		66
+
 #endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */
-- 
2.39.2

Re: [PATCH 04/17] dt-bindings: clock: r9a08g045-cpg: Add power domain IDs

[Geert Uytterhoeven]

On Thu, Feb 8, 2024 at 1:43 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add power domain IDs for RZ/G3S (R9A08G045) SoC.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 05/17] dt-bindings: clock: r9a09g011-cpg: Add always-on power domain IDs

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Add always-on power domain ID for RZ/V2M (R9A09G011) SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 include/dt-bindings/clock/r9a09g011-cpg.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/dt-bindings/clock/r9a09g011-cpg.h b/include/dt-bindings/clock/r9a09g011-cpg.h
index 41dd585d7115..250499faf049 100644
--- a/include/dt-bindings/clock/r9a09g011-cpg.h
+++ b/include/dt-bindings/clock/r9a09g011-cpg.h
@@ -349,4 +349,7 @@
 #define R9A09G011_DDI_RESET		93
 #define R9A09G011_DDI_RESETN_APB	94
 
+/* Power domain IDs. */
+#define R9A09G011_PD_ALWAYS_ON		0
+
 #endif /* __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ */
-- 
2.39.2

Re: [PATCH 05/17] dt-bindings: clock: r9a09g011-cpg: Add always-on power domain IDs

[Geert Uytterhoeven]

Hi Claudiu,

On Thu, Feb 8, 2024 at 1:43 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add always-on power domain ID for RZ/V2M (R9A09G011) SoC.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Thanks for your patch!

> --- a/include/dt-bindings/clock/r9a09g011-cpg.h
> +++ b/include/dt-bindings/clock/r9a09g011-cpg.h
> @@ -349,4 +349,7 @@
>  #define R9A09G011_DDI_RESET            93
>  #define R9A09G011_DDI_RESETN_APB       94
>
> +/* Power domain IDs. */
> +#define R9A09G011_PD_ALWAYS_ON         0

RZ/V2M has many more power domains, but they are not controlled through
CPG_BUS_*_MSTOP registers, but by the Internal Power Domain Controller
(PMC).

> +
>  #endif /* __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ */

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 05/17] dt-bindings: clock: r9a09g011-cpg: Add always-on power domain IDs

[claudiu beznea]

On 16.02.2024 16:03, Geert Uytterhoeven wrote:
> Hi Claudiu,
> 
> On Thu, Feb 8, 2024 at 1:43 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Add always-on power domain ID for RZ/V2M (R9A09G011) SoC.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Thanks for your patch!
> 
>> --- a/include/dt-bindings/clock/r9a09g011-cpg.h
>> +++ b/include/dt-bindings/clock/r9a09g011-cpg.h
>> @@ -349,4 +349,7 @@
>>  #define R9A09G011_DDI_RESET            93
>>  #define R9A09G011_DDI_RESETN_APB       94
>>
>> +/* Power domain IDs. */
>> +#define R9A09G011_PD_ALWAYS_ON         0
> 
> RZ/V2M has many more power domains, but they are not controlled through
> CPG_BUS_*_MSTOP registers, but by the Internal Power Domain Controller
> (PMC).

I wasn't aware of that. I'll be checking it.

> 
>> +
>>  #endif /* __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ */
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

[PATCH 06/17] dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1>

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

The driver will be modified (in the next commits) to be able to specify
individual power domain ID for each IP. Update the documentation to cope
with this.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 .../devicetree/bindings/clock/renesas,rzg2l-cpg.yaml          | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
index 80a8c7114c31..d7de3ddbc613 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
@@ -57,7 +57,7 @@ properties:
       can be power-managed through Module Standby should refer to the CPG device
       node in their "power-domains" property, as documented by the generic PM
       Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
-    const: 0
+    const: 1
 
   '#reset-cells':
     description:
@@ -84,6 +84,6 @@ examples:
             clocks = <&extal_clk>;
             clock-names = "extal";
             #clock-cells = <2>;
-            #power-domain-cells = <0>;
+            #power-domain-cells = <1>;
             #reset-cells = <1>;
     };
-- 
2.39.2

Re: [PATCH 06/17] dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1>

[Krzysztof Kozlowski]

On 08/02/2024 13:42, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> The driver will be modified (in the next commits) to be able to specify
> individual power domain ID for each IP. Update the documentation to cope
> with this.

You are affecting existing users, so you should explain that you keep
ABI intact or if you break it, why it is fine to do so.



Best regards,
Krzysztof

Re: [PATCH 06/17] dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1>

[claudiu beznea]

On 09.02.2024 09:56, Krzysztof Kozlowski wrote:
> On 08/02/2024 13:42, Claudiu wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> The driver will be modified (in the next commits) to be able to specify
>> individual power domain ID for each IP. Update the documentation to cope
>> with this.
> 
> You are affecting existing users, so you should explain that you keep
> ABI intact or if you break it, why it is fine to do so.
> 

OK, I'll improve the description. The ABI will not be broken with the
changes in this series.

Thank you,
Claudiu Beznea

> 
> 
> Best regards,
> Krzysztof
> 

Re: [PATCH 06/17] dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1>

[Geert Uytterhoeven]

Hi Claudiu,

On Thu, Feb 8, 2024 at 1:43 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> The driver will be modified (in the next commits) to be able to specify
> individual power domain ID for each IP. Update the documentation to cope
> with this.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Thanks for your patch!

> --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> @@ -57,7 +57,7 @@ properties:
>        can be power-managed through Module Standby should refer to the CPG device
>        node in their "power-domains" property, as documented by the generic PM
>        Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
> -    const: 0
> +    const: 1

While the driver will soon support both 0 and 1, we may need to keep 0
for RZ/V2M for now?  RZ/V2M does not have CPG_BUS_*_MSTOP registers,
but uses the Internal Power Domain Controller (PMC).

Please add a link to the power domain numbers in
<dt-bindings/clock/r9a0*-cpg.h>,
like is done for #clock-cells.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 06/17] dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1>

[claudiu beznea]

On 16.02.2024 16:04, Geert Uytterhoeven wrote:
> Hi Claudiu,
> 
> On Thu, Feb 8, 2024 at 1:43 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> The driver will be modified (in the next commits) to be able to specify
>> individual power domain ID for each IP. Update the documentation to cope
>> with this.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Thanks for your patch!
> 
>> --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
>> +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
>> @@ -57,7 +57,7 @@ properties:
>>        can be power-managed through Module Standby should refer to the CPG device
>>        node in their "power-domains" property, as documented by the generic PM
>>        Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
>> -    const: 0
>> +    const: 1
> 
> While the driver will soon support both 0 and 1, we may need to keep 0
> for RZ/V2M for now?  RZ/V2M does not have CPG_BUS_*_MSTOP registers,
> but uses the Internal Power Domain Controller (PMC).

ok

> 
> Please add a link to the power domain numbers in
> <dt-bindings/clock/r9a0*-cpg.h>,
> like is done for #clock-cells.

ok

> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

[PATCH 07/17] clk: renesas: rzg2l: Extend power domain support

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra
power when clocks are disabled by activating module standby. This is done
through MSTOP-specific registers that are part of CPG. Each individual
module has one or more bits associated with one MSTOP register (see table
"Registers for Module Standby Mode" from HW manuals). Hardware manual
associates modules' clocks with one or more MSTOP bits. There are 3 mappings
available (identified by researching RZ/G2L, RZ/G3S, RZ/V2L HW manuals):

case 1: N clocks mapped to N MSTOP bits (with N={0, ..., X})
case 2: N clocks mapped to 1 MSTOP bit  (with N={0, ..., X})
case 3: N clocks mapped to M MSTOP bits (with N={0, ..., X}, M={0, ..., Y})

Case 3 has been currently identified on RZ/V2L for the VCPL4 module.

To cover all three cases, the individual platform drivers will provide to
clock driver MSTOP register offset and associated bits in this register
as a bitmask and the clock driver will apply this bitmask to proper
MSTOP register.

Apart from MSTOP support, RZ/G3S can save more power by powering down the
individual IPs (after MSTOP has been set) if proper bits in
CPG_PWRDN_IP{1,2} registers are set.

The MSTOP and IP power down support were implemented through power
domains. Platform-specific clock drivers will register an array of
type struct rzg2l_cpg_pm_domain_init_data, which will be used to
instantiate properly the power domains.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/clk/renesas/rzg2l-cpg.c | 227 ++++++++++++++++++++++++++++++--
 drivers/clk/renesas/rzg2l-cpg.h |  68 ++++++++++
 2 files changed, 281 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 3d2daa4ba2a4..3a7168c314c2 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -139,7 +139,6 @@ struct rzg2l_pll5_mux_dsi_div_param {
  * @num_resets: Number of Module Resets in info->resets[]
  * @last_dt_core_clk: ID of the last Core Clock exported to DT
  * @info: Pointer to platform data
- * @genpd: PM domain
  * @mux_dsi_div_params: pll5 mux and dsi div parameters
  */
 struct rzg2l_cpg_priv {
@@ -156,8 +155,6 @@ struct rzg2l_cpg_priv {
 
 	const struct rzg2l_cpg_info *info;
 
-	struct generic_pm_domain genpd;
-
 	struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
 };
 
@@ -1559,9 +1556,34 @@ static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
 	return true;
 }
 
+/**
+ * struct rzg2l_cpg_pm_domain - RZ/G2L PM domains data structure
+ * @domains: generic PM domains
+ * @onecell_data: cell data
+ */
+struct rzg2l_cpg_pm_domain {
+	struct generic_pm_domain **domains;
+	struct genpd_onecell_data onecell_data;
+};
+
+/**
+ * struct rzg2l_cpg_pd - RZ/G2L power domain data structure
+ * @priv: pointer to CPG private data structure
+ * @genpd: generic PM domain
+ * @conf: CPG PM domain configuration info
+ * @id: RZ/G2L power domain ID
+ */
+struct rzg2l_cpg_pd {
+	struct rzg2l_cpg_priv *priv;
+	struct generic_pm_domain genpd;
+	struct rzg2l_cpg_pm_domain_conf conf;
+	u16 id;
+};
+
 static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
 {
-	struct rzg2l_cpg_priv *priv = container_of(domain, struct rzg2l_cpg_priv, genpd);
+	struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
+	struct rzg2l_cpg_priv *priv = pd->priv;
 	struct device_node *np = dev->of_node;
 	struct of_phandle_args clkspec;
 	bool once = true;
@@ -1617,31 +1639,208 @@ static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device
 }
 
 static void rzg2l_cpg_genpd_remove(void *data)
+{
+	struct genpd_onecell_data *celldata = data;
+
+	for (unsigned int i = 0; i < celldata->num_domains; i++)
+		pm_genpd_remove(celldata->domains[i]);
+}
+
+static void rzg2l_cpg_genpd_remove_simple(void *data)
 {
 	pm_genpd_remove(data);
 }
 
+static int rzg2l_cpg_power_on(struct generic_pm_domain *domain)
+{
+	struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
+	struct rzg2l_cpg_priv *priv = pd->priv;
+	u32 off, mask;
+
+	/* Set PWRDN. */
+	if (pd->conf.pwrdn) {
+		off = PWRDN_OFF(pd->conf.pwrdn);
+		mask = PWRDN_MASK(pd->conf.pwrdn) << 16;
+		writel(mask, priv->base + off);
+	}
+
+	/* Set MSTOP. */
+	if (pd->conf.mstop) {
+		off = MSTOP_OFF(pd->conf.mstop);
+		mask = MSTOP_MASK(pd->conf.mstop) << 16;
+		writel(mask, priv->base + off);
+	}
+
+	return 0;
+}
+
+static int rzg2l_cpg_power_off(struct generic_pm_domain *domain)
+{
+	struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
+	struct rzg2l_cpg_priv *priv = pd->priv;
+	u32 off, mask;
+
+	/* Set MSTOP. */
+	if (pd->conf.mstop) {
+		off = MSTOP_OFF(pd->conf.mstop);
+		mask = MSTOP_MASK(pd->conf.mstop);
+		writel(mask | (mask << 16), priv->base + off);
+	}
+
+	/* Set PWRDN. */
+	if (pd->conf.pwrdn) {
+		off = PWRDN_OFF(pd->conf.pwrdn);
+		mask = PWRDN_MASK(pd->conf.pwrdn);
+		writel(mask | (mask << 16), priv->base + off);
+	}
+
+	return 0;
+}
+
+static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on)
+{
+	struct dev_power_governor *governor;
+
+	pd->genpd.flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
+	pd->genpd.attach_dev = rzg2l_cpg_attach_dev;
+	pd->genpd.detach_dev = rzg2l_cpg_detach_dev;
+	if (always_on) {
+		pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON;
+		governor = &pm_domain_always_on_gov;
+	} else {
+		pd->genpd.power_on = rzg2l_cpg_power_on;
+		pd->genpd.power_off = rzg2l_cpg_power_off;
+		governor = &simple_qos_governor;
+	}
+
+	return pm_genpd_init(&pd->genpd, governor, false);
+}
+
 static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv)
 {
 	struct device *dev = priv->dev;
 	struct device_node *np = dev->of_node;
-	struct generic_pm_domain *genpd = &priv->genpd;
+	struct rzg2l_cpg_pd *pd;
 	int ret;
 
-	genpd->name = np->name;
-	genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
-		       GENPD_FLAG_ACTIVE_WAKEUP;
-	genpd->attach_dev = rzg2l_cpg_attach_dev;
-	genpd->detach_dev = rzg2l_cpg_detach_dev;
-	ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
+	pd = devm_kzalloc(priv->dev, sizeof(*pd), GFP_KERNEL);
+	if (!pd)
+		return -ENOMEM;
+
+	pd->genpd.name = np->name;
+	pd->priv = priv;
+	ret = rzg2l_cpg_pd_setup(pd, true);
 	if (ret)
 		return ret;
 
-	ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, genpd);
+	ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove_simple, &pd->genpd);
 	if (ret)
 		return ret;
 
-	return of_genpd_add_provider_simple(np, genpd);
+	return of_genpd_add_provider_simple(np, &pd->genpd);
+}
+
+static struct generic_pm_domain *
+rzg2l_cpg_pm_domain_xlate(struct of_phandle_args *spec, void *data)
+{
+	struct generic_pm_domain *domain = ERR_PTR(-ENOENT);
+	struct genpd_onecell_data *genpd = data;
+
+	if (spec->args_count != 1)
+		return ERR_PTR(-EINVAL);
+
+	for (unsigned int i = 0; i < genpd->num_domains; i++) {
+		struct rzg2l_cpg_pd *pd = container_of(genpd->domains[i], struct rzg2l_cpg_pd,
+						       genpd);
+
+		if (pd->id == spec->args[0]) {
+			domain = &pd->genpd;
+			break;
+		}
+	}
+
+	return domain;
+}
+
+static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv)
+{
+	const struct rzg2l_cpg_info *info = priv->info;
+	struct device *dev = priv->dev;
+	struct device_node *np = dev->of_node;
+	struct rzg2l_cpg_pm_domain *domains;
+	struct generic_pm_domain *parent;
+	u32 ncells;
+	int ret;
+
+	ret = of_property_read_u32(np, "#power-domain-cells", &ncells);
+	if (ret)
+		return ret;
+
+	/* For backward compatibility. */
+	if (!ncells)
+		return rzg2l_cpg_add_clk_domain(priv);
+
+	domains = devm_kzalloc(priv->dev, sizeof(*domains), GFP_KERNEL);
+	if (!domains)
+		return -ENOMEM;
+
+	domains->domains = devm_kcalloc(priv->dev, info->num_pm_domains,
+					sizeof(struct generic_pm_domain *), GFP_KERNEL);
+	if (!domains->domains)
+		return -ENOMEM;
+
+	domains->onecell_data.domains = domains->domains;
+	domains->onecell_data.num_domains = info->num_pm_domains;
+	domains->onecell_data.xlate = rzg2l_cpg_pm_domain_xlate;
+
+	ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, &domains->onecell_data);
+	if (ret)
+		return ret;
+
+	for (unsigned int i = 0; i < info->num_pm_domains; i++) {
+		bool always_on = !!(info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON);
+		struct rzg2l_cpg_pd *pd;
+
+		pd = devm_kzalloc(priv->dev, sizeof(*pd), GFP_KERNEL);
+		if (!pd)
+			return -ENOMEM;
+
+		pd->genpd.name = info->pm_domains[i].name;
+		pd->conf = info->pm_domains[i].conf;
+		pd->id = info->pm_domains[i].id;
+		pd->priv = priv;
+
+		ret = rzg2l_cpg_pd_setup(pd, always_on);
+		if (ret)
+			return ret;
+
+		if (always_on) {
+			ret = rzg2l_cpg_power_on(&pd->genpd);
+			if (ret)
+				return ret;
+		}
+
+		domains->domains[i] = &pd->genpd;
+		/* Parent should be on the very first entry of info->pm_domains[]. */
+		if (info->pm_domains[i].flags & RZG2L_PD_F_PARENT) {
+			parent = &pd->genpd;
+			continue;
+		}
+
+		ret = pm_genpd_add_subdomain(parent, &pd->genpd);
+		if (ret)
+			return ret;
+	}
+
+	ret = of_genpd_add_provider_onecell(np, &domains->onecell_data);
+	if (ret)
+		return ret;
+
+	/* Prepare for power down the BUSes in power down mode. */
+	if (info->pm_domain_pwrdn_mstop)
+		writel(CPG_PWRDN_MSTOP_ENABLE, priv->base + CPG_PWRDN_MSTOP);
+
+	return 0;
 }
 
 static int __init rzg2l_cpg_probe(struct platform_device *pdev)
@@ -1697,7 +1896,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
 	if (error)
 		return error;
 
-	error = rzg2l_cpg_add_clk_domain(priv);
+	error = rzg2l_cpg_add_pm_domains(priv);
 	if (error)
 		return error;
 
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 6e38c8fc888c..00d12b04ba2f 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -27,6 +27,16 @@
 #define CPG_PL6_ETH_SSEL	(0x418)
 #define CPG_PL5_SDIV		(0x420)
 #define CPG_RST_MON		(0x680)
+#define CPG_ACPU_MSTOP		(0xB60)
+#define CPG_MCPU2_MSTOP		(0xB68)
+#define CPG_PERI_COM_MSTOP	(0xB6C)
+#define CPG_PERI_CPU_MSTOP	(0xB70)
+#define CPG_PERI_DDR_MSTOP	(0xB74)
+#define CPG_REG1_MSTOP		(0xB80)
+#define CPG_TZCDDR_MSTOP	(0xB84)
+#define CPG_PWRDN_IP1		(0xBB0)
+#define CPG_PWRDN_IP2		(0xBB4)
+#define CPG_PWRDN_MSTOP		(0xBC0)
 #define CPG_OTHERFUNC1_REG	(0xBE8)
 
 #define CPG_SIPLL5_STBY_RESETB		BIT(0)
@@ -70,6 +80,8 @@
 
 #define EXTAL_FREQ_IN_MEGA_HZ	(24)
 
+#define CPG_PWRDN_MSTOP_ENABLE		(BIT(16) | BIT(0))
+
 /**
  * Definitions of CPG Core Clocks
  *
@@ -234,6 +246,54 @@ struct rzg2l_reset {
 #define DEF_RST(_id, _off, _bit)	\
 	DEF_RST_MON(_id, _off, _bit, -1)
 
+/**
+ * struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure
+ * @mstop: MSTOP configuration (MSB = register offset, LSB = bitmask)
+ * @pwrdn: PWRDN configuration (MSB = register offset, LSB = register bit)
+ */
+struct rzg2l_cpg_pm_domain_conf {
+	u32 mstop;
+	u32 pwrdn;
+};
+
+/**
+ * struct rzg2l_cpg_pm_domain_init_data - PM domain init data
+ * @name: PM domain name
+ * @conf: PM domain configuration
+ * @flags: RZG2L PM domain flags (see RZG2L_PD_F_*)
+ * @id: PM domain ID (similar to the ones defined in
+ *      include/dt-bindings/clock/<soc-id>-cpg.h)
+ */
+struct rzg2l_cpg_pm_domain_init_data {
+	const char * const name;
+	struct rzg2l_cpg_pm_domain_conf conf;
+	u32 flags;
+	u16 id;
+};
+
+#define DEF_PD(_name, _id, _mstop_conf, _pwrdn_conf, _flags) \
+	{ \
+		.name = (_name), \
+		.id = (_id), \
+		.conf = { \
+			.mstop = (_mstop_conf), \
+			.pwrdn = (_pwrdn_conf), \
+		}, \
+		.flags = (_flags), \
+	}
+
+#define MSTOP(name, bitmask)	((CPG_##name##_MSTOP) << 16 | (bitmask))
+#define MSTOP_OFF(conf)		((conf) >> 16)
+#define MSTOP_MASK(conf)	((conf) & GENMASK(15, 0))
+
+#define PWRDN(name, bit)	((CPG_PWRDN_##name) << 16 | BIT(bit))
+#define PWRDN_OFF(conf)		((conf) >> 16)
+#define PWRDN_MASK(conf)	((conf) & GENMASK(15, 0))
+
+/* Power domain flags. */
+#define RZG2L_PD_F_PARENT	BIT(0)
+#define RZG2L_PD_F_ALWAYS_ON	BIT(1)
+
 /**
  * struct rzg2l_cpg_info - SoC-specific CPG Description
  *
@@ -252,6 +312,9 @@ struct rzg2l_reset {
  * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
  *                 should not be disabled without a knowledgeable driver
  * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
+ * @pm_domains: PM domains init data array
+ * @num_pm_domains: Number of PM domains
+ * @pm_domain_pwrdn_mstop: Specifies if PWRDN MSTOP is supported
  * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
  */
 struct rzg2l_cpg_info {
@@ -278,6 +341,11 @@ struct rzg2l_cpg_info {
 	const unsigned int *crit_mod_clks;
 	unsigned int num_crit_mod_clks;
 
+	/* Power domain. */
+	const struct rzg2l_cpg_pm_domain_init_data *pm_domains;
+	unsigned int num_pm_domains;
+	bool pm_domain_pwrdn_mstop;
+
 	bool has_clk_mon_regs;
 };
 
-- 
2.39.2

Re: [PATCH 07/17] clk: renesas: rzg2l: Extend power domain support

[Geert Uytterhoeven]

Hi Claudiu,

On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra
> power when clocks are disabled by activating module standby. This is done
> through MSTOP-specific registers that are part of CPG. Each individual
> module has one or more bits associated with one MSTOP register (see table
> "Registers for Module Standby Mode" from HW manuals). Hardware manual
> associates modules' clocks with one or more MSTOP bits. There are 3 mappings
> available (identified by researching RZ/G2L, RZ/G3S, RZ/V2L HW manuals):
>
> case 1: N clocks mapped to N MSTOP bits (with N={0, ..., X})
> case 2: N clocks mapped to 1 MSTOP bit  (with N={0, ..., X})
> case 3: N clocks mapped to M MSTOP bits (with N={0, ..., X}, M={0, ..., Y})
>
> Case 3 has been currently identified on RZ/V2L for the VCPL4 module.
>
> To cover all three cases, the individual platform drivers will provide to
> clock driver MSTOP register offset and associated bits in this register
> as a bitmask and the clock driver will apply this bitmask to proper
> MSTOP register.
>
> Apart from MSTOP support, RZ/G3S can save more power by powering down the
> individual IPs (after MSTOP has been set) if proper bits in
> CPG_PWRDN_IP{1,2} registers are set.
>
> The MSTOP and IP power down support were implemented through power
> domains. Platform-specific clock drivers will register an array of
> type struct rzg2l_cpg_pm_domain_init_data, which will be used to
> instantiate properly the power domains.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -1559,9 +1556,34 @@ static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
>         return true;
>  }
>
> +/**
> + * struct rzg2l_cpg_pm_domain - RZ/G2L PM domains data structure
> + * @domains: generic PM domains
> + * @onecell_data: cell data
> + */
> +struct rzg2l_cpg_pm_domain {

rzg2l_cpg_pm_domains (plural)?

> +       struct generic_pm_domain **domains;
> +       struct genpd_onecell_data onecell_data;
> +};

Using a flexible array like

    struct rzg2l_cpg_pm_domains {
            struct genpd_onecell_data onecell_data;
            struct generic_pm_domain *domains[];
    };

would let you allocate the structure and the array in a single step,
using devm_kzalloc(..., struct_size(...), ...).

> +
> +/**
> + * struct rzg2l_cpg_pd - RZ/G2L power domain data structure
> + * @priv: pointer to CPG private data structure
> + * @genpd: generic PM domain
> + * @conf: CPG PM domain configuration info
> + * @id: RZ/G2L power domain ID
> + */
> +struct rzg2l_cpg_pd {
> +       struct rzg2l_cpg_priv *priv;
> +       struct generic_pm_domain genpd;

Please make genpd the first member, for simpler conversion between
rzg2l_cpg_pd and generic_pm_domain pointers.

> +       struct rzg2l_cpg_pm_domain_conf conf;
> +       u16 id;
> +};

> +static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv)
> +{
> +       const struct rzg2l_cpg_info *info = priv->info;
> +       struct device *dev = priv->dev;
> +       struct device_node *np = dev->of_node;
> +       struct rzg2l_cpg_pm_domain *domains;
> +       struct generic_pm_domain *parent;

Missing initialization parent = NULL;

> +       u32 ncells;
> +       int ret;
> +
> +       ret = of_property_read_u32(np, "#power-domain-cells", &ncells);
> +       if (ret)
> +               return ret;
> +
> +       /* For backward compatibility. */
> +       if (!ncells)
> +               return rzg2l_cpg_add_clk_domain(priv);
> +
> +       domains = devm_kzalloc(priv->dev, sizeof(*domains), GFP_KERNEL);
> +       if (!domains)
> +               return -ENOMEM;
> +
> +       domains->domains = devm_kcalloc(priv->dev, info->num_pm_domains,
> +                                       sizeof(struct generic_pm_domain *), GFP_KERNEL);
> +       if (!domains->domains)
> +               return -ENOMEM;
> +
> +       domains->onecell_data.domains = domains->domains;
> +       domains->onecell_data.num_domains = info->num_pm_domains;
> +       domains->onecell_data.xlate = rzg2l_cpg_pm_domain_xlate;
> +
> +       ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, &domains->onecell_data);
> +       if (ret)
> +               return ret;
> +
> +       for (unsigned int i = 0; i < info->num_pm_domains; i++) {
> +               bool always_on = !!(info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON);
> +               struct rzg2l_cpg_pd *pd;
> +
> +               pd = devm_kzalloc(priv->dev, sizeof(*pd), GFP_KERNEL);
> +               if (!pd)
> +                       return -ENOMEM;
> +
> +               pd->genpd.name = info->pm_domains[i].name;
> +               pd->conf = info->pm_domains[i].conf;
> +               pd->id = info->pm_domains[i].id;
> +               pd->priv = priv;
> +
> +               ret = rzg2l_cpg_pd_setup(pd, always_on);
> +               if (ret)
> +                       return ret;
> +
> +               if (always_on) {
> +                       ret = rzg2l_cpg_power_on(&pd->genpd);
> +                       if (ret)
> +                               return ret;
> +               }
> +
> +               domains->domains[i] = &pd->genpd;
> +               /* Parent should be on the very first entry of info->pm_domains[]. */
> +               if (info->pm_domains[i].flags & RZG2L_PD_F_PARENT) {
> +                       parent = &pd->genpd;
> +                       continue;
> +               }
> +
> +               ret = pm_genpd_add_subdomain(parent, &pd->genpd);
> +               if (ret)
> +                       return ret;

I think you can simplify/generalize the above logic without needing
the RZG2L_PD_F_PARENT flag:

    if (i) {
            ret = pm_genpd_add_subdomain(domains->domains[0], &pd->genpd);
            if (ret)
                    return ret;
    }

> +       }
> +
> +       ret = of_genpd_add_provider_onecell(np, &domains->onecell_data);
> +       if (ret)
> +               return ret;
> +
> +       /* Prepare for power down the BUSes in power down mode. */
> +       if (info->pm_domain_pwrdn_mstop)
> +               writel(CPG_PWRDN_MSTOP_ENABLE, priv->base + CPG_PWRDN_MSTOP);
> +
> +       return 0;
>  }
>
>  static int __init rzg2l_cpg_probe(struct platform_device *pdev)

> --- a/drivers/clk/renesas/rzg2l-cpg.h
> +++ b/drivers/clk/renesas/rzg2l-cpg.h
> @@ -27,6 +27,16 @@
>  #define CPG_PL6_ETH_SSEL       (0x418)
>  #define CPG_PL5_SDIV           (0x420)
>  #define CPG_RST_MON            (0x680)
> +#define CPG_ACPU_MSTOP         (0xB60)
> +#define CPG_MCPU2_MSTOP                (0xB68)
> +#define CPG_PERI_COM_MSTOP     (0xB6C)
> +#define CPG_PERI_CPU_MSTOP     (0xB70)
> +#define CPG_PERI_DDR_MSTOP     (0xB74)
> +#define CPG_REG1_MSTOP         (0xB80)
> +#define CPG_TZCDDR_MSTOP       (0xB84)
> +#define CPG_PWRDN_IP1          (0xBB0)
> +#define CPG_PWRDN_IP2          (0xBB4)
> +#define CPG_PWRDN_MSTOP                (0xBC0)

Please name these CPG_BUS_*, to match the documentation.

>  #define CPG_OTHERFUNC1_REG     (0xBE8)
>
>  #define CPG_SIPLL5_STBY_RESETB         BIT(0)

> @@ -234,6 +246,54 @@ struct rzg2l_reset {
>  #define DEF_RST(_id, _off, _bit)       \
>         DEF_RST_MON(_id, _off, _bit, -1)
>
> +/**
> + * struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure
> + * @mstop: MSTOP configuration (MSB = register offset, LSB = bitmask)
> + * @pwrdn: PWRDN configuration (MSB = register offset, LSB = register bit)
> + */
> +struct rzg2l_cpg_pm_domain_conf {
> +       u32 mstop;
> +       u32 pwrdn;

Why not

    u16 mstop_off;
    u16 mstop_mask;
    u16 pwrdn_off;
    u16 pwrdn_mask;

so you can drop the MSTOP*() and PWRDN*() macros below?

> +};
> +
> +/**
> + * struct rzg2l_cpg_pm_domain_init_data - PM domain init data
> + * @name: PM domain name
> + * @conf: PM domain configuration
> + * @flags: RZG2L PM domain flags (see RZG2L_PD_F_*)
> + * @id: PM domain ID (similar to the ones defined in
> + *      include/dt-bindings/clock/<soc-id>-cpg.h)
> + */
> +struct rzg2l_cpg_pm_domain_init_data {
> +       const char * const name;
> +       struct rzg2l_cpg_pm_domain_conf conf;
> +       u32 flags;

With a single flag left, this can become "bool always_on"
(and be moved after "id" to improve packing).

> +       u16 id;
> +};
> +
> +#define DEF_PD(_name, _id, _mstop_conf, _pwrdn_conf, _flags) \
> +       { \
> +               .name = (_name), \
> +               .id = (_id), \
> +               .conf = { \
> +                       .mstop = (_mstop_conf), \
> +                       .pwrdn = (_pwrdn_conf), \
> +               }, \
> +               .flags = (_flags), \
> +       }
> +
> +#define MSTOP(name, bitmask)   ((CPG_##name##_MSTOP) << 16 | (bitmask))
> +#define MSTOP_OFF(conf)                ((conf) >> 16)
> +#define MSTOP_MASK(conf)       ((conf) & GENMASK(15, 0))
> +
> +#define PWRDN(name, bit)       ((CPG_PWRDN_##name) << 16 | BIT(bit))
> +#define PWRDN_OFF(conf)                ((conf) >> 16)
> +#define PWRDN_MASK(conf)       ((conf) & GENMASK(15, 0))
> +
> +/* Power domain flags. */
> +#define RZG2L_PD_F_PARENT      BIT(0)
> +#define RZG2L_PD_F_ALWAYS_ON   BIT(1)
> +
>  /**
>   * struct rzg2l_cpg_info - SoC-specific CPG Description
>   *

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 07/17] clk: renesas: rzg2l: Extend power domain support

[claudiu beznea]

On 16.02.2024 16:08, Geert Uytterhoeven wrote:
> Hi Claudiu,
> 
> On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra
>> power when clocks are disabled by activating module standby. This is done
>> through MSTOP-specific registers that are part of CPG. Each individual
>> module has one or more bits associated with one MSTOP register (see table
>> "Registers for Module Standby Mode" from HW manuals). Hardware manual
>> associates modules' clocks with one or more MSTOP bits. There are 3 mappings
>> available (identified by researching RZ/G2L, RZ/G3S, RZ/V2L HW manuals):
>>
>> case 1: N clocks mapped to N MSTOP bits (with N={0, ..., X})
>> case 2: N clocks mapped to 1 MSTOP bit  (with N={0, ..., X})
>> case 3: N clocks mapped to M MSTOP bits (with N={0, ..., X}, M={0, ..., Y})
>>
>> Case 3 has been currently identified on RZ/V2L for the VCPL4 module.
>>
>> To cover all three cases, the individual platform drivers will provide to
>> clock driver MSTOP register offset and associated bits in this register
>> as a bitmask and the clock driver will apply this bitmask to proper
>> MSTOP register.
>>
>> Apart from MSTOP support, RZ/G3S can save more power by powering down the
>> individual IPs (after MSTOP has been set) if proper bits in
>> CPG_PWRDN_IP{1,2} registers are set.
>>
>> The MSTOP and IP power down support were implemented through power
>> domains. Platform-specific clock drivers will register an array of
>> type struct rzg2l_cpg_pm_domain_init_data, which will be used to
>> instantiate properly the power domains.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Thanks for your patch!
> 
>> --- a/drivers/clk/renesas/rzg2l-cpg.c
>> +++ b/drivers/clk/renesas/rzg2l-cpg.c
>> @@ -1559,9 +1556,34 @@ static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
>>         return true;
>>  }
[ ... ]

> 
>> @@ -234,6 +246,54 @@ struct rzg2l_reset {
>>  #define DEF_RST(_id, _off, _bit)       \
>>         DEF_RST_MON(_id, _off, _bit, -1)
>>
>> +/**
>> + * struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure
>> + * @mstop: MSTOP configuration (MSB = register offset, LSB = bitmask)
>> + * @pwrdn: PWRDN configuration (MSB = register offset, LSB = register bit)
>> + */
>> +struct rzg2l_cpg_pm_domain_conf {
>> +       u32 mstop;
>> +       u32 pwrdn;
> 
> Why not
> 
>     u16 mstop_off;
>     u16 mstop_mask;
>     u16 pwrdn_off;
>     u16 pwrdn_mask;
> 
> so you can drop the MSTOP*() and PWRDN*() macros below?

I did it like this to align with the already existing approach for this
kind of things available in this driver. I can do it as you proposed.

For the rest of your comments on this patch: I agree and will adjust the
patch in the next version.

Thank you,
Claudiu Beznea

Re: [PATCH 07/17] clk: renesas: rzg2l: Extend power domain support

[Geert Uytterhoeven]

Hi Claudiu,

On Mon, Feb 19, 2024 at 9:24 AM claudiu beznea <claudiu.beznea@tuxon.dev> wrote:
> On 16.02.2024 16:08, Geert Uytterhoeven wrote:
> > On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>
> >> RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra
> >> power when clocks are disabled by activating module standby. This is done
> >> through MSTOP-specific registers that are part of CPG. Each individual
> >> module has one or more bits associated with one MSTOP register (see table
> >> "Registers for Module Standby Mode" from HW manuals). Hardware manual
> >> associates modules' clocks with one or more MSTOP bits. There are 3 mappings
> >> available (identified by researching RZ/G2L, RZ/G3S, RZ/V2L HW manuals):
> >>
> >> case 1: N clocks mapped to N MSTOP bits (with N={0, ..., X})
> >> case 2: N clocks mapped to 1 MSTOP bit  (with N={0, ..., X})
> >> case 3: N clocks mapped to M MSTOP bits (with N={0, ..., X}, M={0, ..., Y})
> >>
> >> Case 3 has been currently identified on RZ/V2L for the VCPL4 module.
> >>
> >> To cover all three cases, the individual platform drivers will provide to
> >> clock driver MSTOP register offset and associated bits in this register
> >> as a bitmask and the clock driver will apply this bitmask to proper
> >> MSTOP register.
> >>
> >> Apart from MSTOP support, RZ/G3S can save more power by powering down the
> >> individual IPs (after MSTOP has been set) if proper bits in
> >> CPG_PWRDN_IP{1,2} registers are set.
> >>
> >> The MSTOP and IP power down support were implemented through power
> >> domains. Platform-specific clock drivers will register an array of
> >> type struct rzg2l_cpg_pm_domain_init_data, which will be used to
> >> instantiate properly the power domains.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> >> --- a/drivers/clk/renesas/rzg2l-cpg.c
> >> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> >> @@ -1559,9 +1556,34 @@ static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
> >>         return true;
> >>  }
> [ ... ]
>
> >
> >> @@ -234,6 +246,54 @@ struct rzg2l_reset {
> >>  #define DEF_RST(_id, _off, _bit)       \
> >>         DEF_RST_MON(_id, _off, _bit, -1)
> >>
> >> +/**
> >> + * struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure
> >> + * @mstop: MSTOP configuration (MSB = register offset, LSB = bitmask)
> >> + * @pwrdn: PWRDN configuration (MSB = register offset, LSB = register bit)
> >> + */
> >> +struct rzg2l_cpg_pm_domain_conf {
> >> +       u32 mstop;
> >> +       u32 pwrdn;
> >
> > Why not
> >
> >     u16 mstop_off;
> >     u16 mstop_mask;
> >     u16 pwrdn_off;
> >     u16 pwrdn_mask;
> >
> > so you can drop the MSTOP*() and PWRDN*() macros below?
>
> I did it like this to align with the already existing approach for this
> kind of things available in this driver. I can do it as you proposed.

The other fields do not align nicely with byte or word boundaries.

I can see the value of the MSTOP(name, bitmask) and
PWRDN(name, bitmask) macros, but I'd rather get rid of the *_MASK()
and *_OFF() variants.

> For the rest of your comments on this patch: I agree and will adjust the
> patch in the next version.

Thanks!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 07/17] clk: renesas: rzg2l: Extend power domain support

[claudiu beznea]

Hi, Geert,

On 19.02.2024 10:48, Geert Uytterhoeven wrote:
> Hi Claudiu,
> 
> On Mon, Feb 19, 2024 at 9:24 AM claudiu beznea <claudiu.beznea@tuxon.dev> wrote:
>> On 16.02.2024 16:08, Geert Uytterhoeven wrote:
>>> On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>
>>>> RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra
>>>> power when clocks are disabled by activating module standby. This is done
>>>> through MSTOP-specific registers that are part of CPG. Each individual
>>>> module has one or more bits associated with one MSTOP register (see table
>>>> "Registers for Module Standby Mode" from HW manuals). Hardware manual
>>>> associates modules' clocks with one or more MSTOP bits. There are 3 mappings
>>>> available (identified by researching RZ/G2L, RZ/G3S, RZ/V2L HW manuals):
>>>>
>>>> case 1: N clocks mapped to N MSTOP bits (with N={0, ..., X})
>>>> case 2: N clocks mapped to 1 MSTOP bit  (with N={0, ..., X})
>>>> case 3: N clocks mapped to M MSTOP bits (with N={0, ..., X}, M={0, ..., Y})
>>>>
>>>> Case 3 has been currently identified on RZ/V2L for the VCPL4 module.
>>>>
>>>> To cover all three cases, the individual platform drivers will provide to
>>>> clock driver MSTOP register offset and associated bits in this register
>>>> as a bitmask and the clock driver will apply this bitmask to proper
>>>> MSTOP register.
>>>>
>>>> Apart from MSTOP support, RZ/G3S can save more power by powering down the
>>>> individual IPs (after MSTOP has been set) if proper bits in
>>>> CPG_PWRDN_IP{1,2} registers are set.
>>>>
>>>> The MSTOP and IP power down support were implemented through power
>>>> domains. Platform-specific clock drivers will register an array of
>>>> type struct rzg2l_cpg_pm_domain_init_data, which will be used to
>>>> instantiate properly the power domains.
>>>>
>>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>
>>> Thanks for your patch!
>>>
>>>> --- a/drivers/clk/renesas/rzg2l-cpg.c
>>>> +++ b/drivers/clk/renesas/rzg2l-cpg.c
>>>> @@ -1559,9 +1556,34 @@ static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
>>>>         return true;
>>>>  }
>> [ ... ]
>>
>>>
>>>> @@ -234,6 +246,54 @@ struct rzg2l_reset {
>>>>  #define DEF_RST(_id, _off, _bit)       \
>>>>         DEF_RST_MON(_id, _off, _bit, -1)
>>>>
>>>> +/**
>>>> + * struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure
>>>> + * @mstop: MSTOP configuration (MSB = register offset, LSB = bitmask)
>>>> + * @pwrdn: PWRDN configuration (MSB = register offset, LSB = register bit)
>>>> + */
>>>> +struct rzg2l_cpg_pm_domain_conf {
>>>> +       u32 mstop;
>>>> +       u32 pwrdn;
>>>
>>> Why not
>>>
>>>     u16 mstop_off;
>>>     u16 mstop_mask;
>>>     u16 pwrdn_off;
>>>     u16 pwrdn_mask;
>>>
>>> so you can drop the MSTOP*() and PWRDN*() macros below?
>>
>> I did it like this to align with the already existing approach for this
>> kind of things available in this driver. I can do it as you proposed.
> 
> The other fields do not align nicely with byte or word boundaries.
> 
> I can see the value of the MSTOP(name, bitmask) and
> PWRDN(name, bitmask) macros, but I'd rather get rid of the *_MASK()
> and *_OFF() variants.

Sure, I'll do proper adjustments in the next version.

Thank you,
Claudiu Beznea

> 
>> For the rest of your comments on this patch: I agree and will adjust the
>> patch in the next version.
> 
> Thanks!
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 

Re: [PATCH 07/17] clk: renesas: rzg2l: Extend power domain support

[Geert Uytterhoeven]

Hi Claudiu,

On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c

> +static struct generic_pm_domain *
> +rzg2l_cpg_pm_domain_xlate(struct of_phandle_args *spec, void *data)

As of commit 4d0824608a636b64 ("pmdomain: core: constify of_phandle_args
in xlate") in next-20240215 and later the first parameter needs to
be const.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 07/17] clk: renesas: rzg2l: Extend power domain support

[claudiu beznea]

Hi, Geert,

On 20.02.2024 21:32, Geert Uytterhoeven wrote:
> Hi Claudiu,
> 
> On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
>> --- a/drivers/clk/renesas/rzg2l-cpg.c
>> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> 
>> +static struct generic_pm_domain *
>> +rzg2l_cpg_pm_domain_xlate(struct of_phandle_args *spec, void *data)
> 
> As of commit 4d0824608a636b64 ("pmdomain: core: constify of_phandle_args
> in xlate") in next-20240215 and later the first parameter needs to
> be const.

Indeed, I noticed that. Thank you for pointing it.


> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 

[PATCH 08/17] clk: renesas: r9a07g043: Add initial support for power domains

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Instantiate always-on power domain for R9A07G043 SoC. At the moment, all
the IPs are part of this domain.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/clk/renesas/r9a07g043-cpg.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index acfb06cad441..3a7fddd1fa61 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -358,6 +358,11 @@ static const unsigned int r9a07g043_no_pm_mod_clks[] = {
 };
 #endif
 
+static const struct rzg2l_cpg_pm_domain_init_data r9a07g043_pm_domains[] = {
+	DEF_PD("always-on",	R9A07G043_PD_ALWAYS_ON, 0, 0,
+				RZG2L_PD_F_PARENT | RZG2L_PD_F_ALWAYS_ON),
+};
+
 const struct rzg2l_cpg_info r9a07g043_cpg_info = {
 	/* Core Clocks */
 	.core_clks = r9a07g043_core_clks,
@@ -392,5 +397,9 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info = {
 	.num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */
 #endif
 
+	/* Power domains. */
+	.pm_domains = r9a07g043_pm_domains,
+	.num_pm_domains = ARRAY_SIZE(r9a07g043_pm_domains),
+
 	.has_clk_mon_regs = true,
 };
-- 
2.39.2

Re: [PATCH 08/17] clk: renesas: r9a07g043: Add initial support for power domains

[Geert Uytterhoeven]

Hi Claudiu,

On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Instantiate always-on power domain for R9A07G043 SoC. At the moment, all
> the IPs are part of this domain.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Thanks for your patch!

As not all IPs are part of the always-on domain, I'd rather defer this
until all domains are handled in the driver.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 08/17] clk: renesas: r9a07g043: Add initial support for power domains

[claudiu beznea]

On 16.02.2024 16:09, Geert Uytterhoeven wrote:
> Hi Claudiu,
> 
> On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Instantiate always-on power domain for R9A07G043 SoC. At the moment, all
>> the IPs are part of this domain.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Thanks for your patch!
> 
> As not all IPs are part of the always-on domain, I'd rather defer this
> until all domains are handled in the driver.

ok

> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

[PATCH 09/17] clk: renesas: r9a07g044: Add initial support for power domains

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Instantiate always-on power domain for R9A07G044 SoC. At the moment, all
the IPs are part of this domain.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/clk/renesas/r9a07g044-cpg.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 1047278c9079..3755e506fc65 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -443,6 +443,11 @@ static const unsigned int r9a07g044_no_pm_mod_clks[] = {
 	MOD_CLK_BASE + R9A07G044_CRU_VCLK,
 };
 
+static const struct rzg2l_cpg_pm_domain_init_data r9a07g044_pm_domains[] = {
+	DEF_PD("always-on",	R9A07G044_PD_ALWAYS_ON, 0, 0,
+				RZG2L_PD_F_PARENT | RZG2L_PD_F_ALWAYS_ON),
+};
+
 #ifdef CONFIG_CLK_R9A07G044
 const struct rzg2l_cpg_info r9a07g044_cpg_info = {
 	/* Core Clocks */
@@ -468,6 +473,10 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = {
 	.resets = r9a07g044_resets,
 	.num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
 
+	/* PM domains */
+	.pm_domains = r9a07g044_pm_domains,
+	.num_pm_domains = ARRAY_SIZE(r9a07g044_pm_domains),
+
 	.has_clk_mon_regs = true,
 };
 #endif
@@ -497,6 +506,10 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info = {
 	.resets = r9a07g044_resets,
 	.num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */
 
+	/* PM domains */
+	.pm_domains = r9a07g044_pm_domains,
+	.num_pm_domains = ARRAY_SIZE(r9a07g044_pm_domains),
+
 	.has_clk_mon_regs = true,
 };
 #endif
-- 
2.39.2

Re: [PATCH 09/17] clk: renesas: r9a07g044: Add initial support for power domains

[Geert Uytterhoeven]

Hi Claudiu,

On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Instantiate always-on power domain for R9A07G044 SoC. At the moment, all
> the IPs are part of this domain.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

As not all IPs are part of the always-on domain, I'd rather defer this
until all domains are handled in the driver.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 10/17] clk: renesas: r9a08g045: Add support for power domains

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Instantiate power domains for the currently enabled IPs of R9A08G045 SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/clk/renesas/r9a08g045-cpg.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index c3e6da2de197..b06d8e93707f 100644
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -240,6 +240,28 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
 	MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
 };
 
+static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
+	DEF_PD("always-on",	R9A08G045_PD_ALWAYS_ON, 0, 0,
+				RZG2L_PD_F_PARENT | RZG2L_PD_F_ALWAYS_ON),
+	DEF_PD("gic",		R9A08G045_PD_GIC, MSTOP(ACPU, BIT(3)), PWRDN(IP1, 2),
+				RZG2L_PD_F_ALWAYS_ON),
+	DEF_PD("ia55",		R9A08G045_PD_IA55, MSTOP(PERI_CPU, BIT(13)), PWRDN(IP1, 3),
+				RZG2L_PD_F_ALWAYS_ON),
+	DEF_PD("dmac",		R9A08G045_PD_DMAC, MSTOP(REG1, GENMASK(3, 0)), 0,
+				RZG2L_PD_F_ALWAYS_ON),
+	DEF_PD("ddr",		R9A08G045_PD_DDR, MSTOP(PERI_DDR, BIT(1)), PWRDN(IP2, 0),
+				RZG2L_PD_F_ALWAYS_ON),
+	DEF_PD("tzcddr",	R9A08G045_PD_TZCDDR, MSTOP(TZCDDR, GENMASK(2, 0)),
+				PWRDN(IP2, 1), RZG2L_PD_F_ALWAYS_ON),
+	DEF_PD("otfde_ddr",	R9A08G045_PD_OTFDE_DDR, 0, PWRDN(IP2, 2), RZG2L_PD_F_ALWAYS_ON),
+	DEF_PD("sdhi0",		R9A08G045_PD_SDHI0, MSTOP(PERI_COM, BIT(0)), PWRDN(IP1, 13), 0),
+	DEF_PD("sdhi1",		R9A08G045_PD_SDHI1, MSTOP(PERI_COM, BIT(1)), PWRDN(IP1, 14), 0),
+	DEF_PD("sdhi2",		R9A08G045_PD_SDHI2, MSTOP(PERI_COM, BIT(11)), PWRDN(IP1, 15), 0),
+	DEF_PD("eth0",		R9A08G045_PD_ETHER0, MSTOP(PERI_COM, BIT(2)), PWRDN(IP1, 11), 0),
+	DEF_PD("eth1",		R9A08G045_PD_ETHER1, MSTOP(PERI_COM, BIT(3)), PWRDN(IP1, 12), 0),
+	DEF_PD("scif0",		R9A08G045_PD_SCIF0, MSTOP(MCPU2, BIT(1)), 0, 0),
+};
+
 const struct rzg2l_cpg_info r9a08g045_cpg_info = {
 	/* Core Clocks */
 	.core_clks = r9a08g045_core_clks,
@@ -260,5 +282,10 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info = {
 	.resets = r9a08g045_resets,
 	.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
 
+	/* Power domains */
+	.pm_domains = r9a08g045_pm_domains,
+	.num_pm_domains = ARRAY_SIZE(r9a08g045_pm_domains),
+	.pm_domain_pwrdn_mstop = true,
+
 	.has_clk_mon_regs = true,
 };
-- 
2.39.2

Re: [PATCH 10/17] clk: renesas: r9a08g045: Add support for power domains

[Geert Uytterhoeven]

Hi Claudiu,

On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Instantiate power domains for the currently enabled IPs of R9A08G045 SoC.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/r9a08g045-cpg.c
> +++ b/drivers/clk/renesas/r9a08g045-cpg.c
> @@ -240,6 +240,28 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
>         MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
>  };
>
> +static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
> +       DEF_PD("always-on",     R9A08G045_PD_ALWAYS_ON, 0, 0,
> +                               RZG2L_PD_F_PARENT | RZG2L_PD_F_ALWAYS_ON),
> +       DEF_PD("gic",           R9A08G045_PD_GIC, MSTOP(ACPU, BIT(3)), PWRDN(IP1, 2),

My docs document only bit 0 of the CPG_BUS_ACPU_MSTOP register.

> +                               RZG2L_PD_F_ALWAYS_ON),
> +       DEF_PD("ia55",          R9A08G045_PD_IA55, MSTOP(PERI_CPU, BIT(13)), PWRDN(IP1, 3),
> +                               RZG2L_PD_F_ALWAYS_ON),
> +       DEF_PD("dmac",          R9A08G045_PD_DMAC, MSTOP(REG1, GENMASK(3, 0)), 0,
> +                               RZG2L_PD_F_ALWAYS_ON),
> +       DEF_PD("ddr",           R9A08G045_PD_DDR, MSTOP(PERI_DDR, BIT(1)), PWRDN(IP2, 0),

Only BIT(1)? My docs suggest GENMASK(1, 0).

> +                               RZG2L_PD_F_ALWAYS_ON),
> +       DEF_PD("tzcddr",        R9A08G045_PD_TZCDDR, MSTOP(TZCDDR, GENMASK(2, 0)),
> +                               PWRDN(IP2, 1), RZG2L_PD_F_ALWAYS_ON),
> +       DEF_PD("otfde_ddr",     R9A08G045_PD_OTFDE_DDR, 0, PWRDN(IP2, 2), RZG2L_PD_F_ALWAYS_ON),

MSTOP(PERI_CPU2, BIT(2))?

> +       DEF_PD("sdhi0",         R9A08G045_PD_SDHI0, MSTOP(PERI_COM, BIT(0)), PWRDN(IP1, 13), 0),
> +       DEF_PD("sdhi1",         R9A08G045_PD_SDHI1, MSTOP(PERI_COM, BIT(1)), PWRDN(IP1, 14), 0),
> +       DEF_PD("sdhi2",         R9A08G045_PD_SDHI2, MSTOP(PERI_COM, BIT(11)), PWRDN(IP1, 15), 0),
> +       DEF_PD("eth0",          R9A08G045_PD_ETHER0, MSTOP(PERI_COM, BIT(2)), PWRDN(IP1, 11), 0),
> +       DEF_PD("eth1",          R9A08G045_PD_ETHER1, MSTOP(PERI_COM, BIT(3)), PWRDN(IP1, 12), 0),
> +       DEF_PD("scif0",         R9A08G045_PD_SCIF0, MSTOP(MCPU2, BIT(1)), 0, 0),
> +};
> +

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 10/17] clk: renesas: r9a08g045: Add support for power domains

[claudiu beznea]

Hi, Geert,

On 16.02.2024 16:10, Geert Uytterhoeven wrote:
> Hi Claudiu,
> 
> On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Instantiate power domains for the currently enabled IPs of R9A08G045 SoC.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Thanks for your patch!
> 
>> --- a/drivers/clk/renesas/r9a08g045-cpg.c
>> +++ b/drivers/clk/renesas/r9a08g045-cpg.c
>> @@ -240,6 +240,28 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
>>         MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
>>  };
>>
>> +static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
>> +       DEF_PD("always-on",     R9A08G045_PD_ALWAYS_ON, 0, 0,
>> +                               RZG2L_PD_F_PARENT | RZG2L_PD_F_ALWAYS_ON),
>> +       DEF_PD("gic",           R9A08G045_PD_GIC, MSTOP(ACPU, BIT(3)), PWRDN(IP1, 2),
> 
> My docs document only bit 0 of the CPG_BUS_ACPU_MSTOP register.

Indeed, mine, too. I took as reference the table "Registers for Module
Standby Mode". I asked for clarifications. The TF-A software also uses
BIT(3) for setting this.

> 
>> +                               RZG2L_PD_F_ALWAYS_ON),
>> +       DEF_PD("ia55",          R9A08G045_PD_IA55, MSTOP(PERI_CPU, BIT(13)), PWRDN(IP1, 3),
>> +                               RZG2L_PD_F_ALWAYS_ON),
>> +       DEF_PD("dmac",          R9A08G045_PD_DMAC, MSTOP(REG1, GENMASK(3, 0)), 0,
>> +                               RZG2L_PD_F_ALWAYS_ON),
>> +       DEF_PD("ddr",           R9A08G045_PD_DDR, MSTOP(PERI_DDR, BIT(1)), PWRDN(IP2, 0),
> 
> Only BIT(1)? My docs suggest GENMASK(1, 0).

I wanted to keep PHY separated but there's no reason for doing that,
AFAICT. I'll update it.

> 
>> +                               RZG2L_PD_F_ALWAYS_ON),
>> +       DEF_PD("tzcddr",        R9A08G045_PD_TZCDDR, MSTOP(TZCDDR, GENMASK(2, 0)),
>> +                               PWRDN(IP2, 1), RZG2L_PD_F_ALWAYS_ON),
>> +       DEF_PD("otfde_ddr",     R9A08G045_PD_OTFDE_DDR, 0, PWRDN(IP2, 2), RZG2L_PD_F_ALWAYS_ON),
> 
> MSTOP(PERI_CPU2, BIT(2))?

OK.

Thank you,
Claudiu Beznea

> 
>> +       DEF_PD("sdhi0",         R9A08G045_PD_SDHI0, MSTOP(PERI_COM, BIT(0)), PWRDN(IP1, 13), 0),
>> +       DEF_PD("sdhi1",         R9A08G045_PD_SDHI1, MSTOP(PERI_COM, BIT(1)), PWRDN(IP1, 14), 0),
>> +       DEF_PD("sdhi2",         R9A08G045_PD_SDHI2, MSTOP(PERI_COM, BIT(11)), PWRDN(IP1, 15), 0),
>> +       DEF_PD("eth0",          R9A08G045_PD_ETHER0, MSTOP(PERI_COM, BIT(2)), PWRDN(IP1, 11), 0),
>> +       DEF_PD("eth1",          R9A08G045_PD_ETHER1, MSTOP(PERI_COM, BIT(3)), PWRDN(IP1, 12), 0),
>> +       DEF_PD("scif0",         R9A08G045_PD_SCIF0, MSTOP(MCPU2, BIT(1)), 0, 0),
>> +};
>> +
> 
> The rest LGTM.
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

[PATCH 11/17] clk: renesas: r9a09g011: Add initial support for power domains

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Instantiate always-on power domain for R9A09G011 SoC. At the moment, all
the IPs are part of this domain.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/clk/renesas/r9a09g011-cpg.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c
index dda9f29dff33..9d090075f3be 100644
--- a/drivers/clk/renesas/r9a09g011-cpg.c
+++ b/drivers/clk/renesas/r9a09g011-cpg.c
@@ -245,6 +245,11 @@ static const unsigned int r9a09g011_crit_mod_clks[] __initconst = {
 	MOD_CLK_BASE + R9A09G011_URT_PCLK,
 };
 
+static const struct rzg2l_cpg_pm_domain_init_data r9a09g011_pm_domains[] = {
+	DEF_PD("always-on",	R9A09G011_PD_ALWAYS_ON, 0, 0,
+				RZG2L_PD_F_PARENT | RZG2L_PD_F_ALWAYS_ON),
+};
+
 const struct rzg2l_cpg_info r9a09g011_cpg_info = {
 	/* Core Clocks */
 	.core_clks = r9a09g011_core_clks,
@@ -265,5 +270,9 @@ const struct rzg2l_cpg_info r9a09g011_cpg_info = {
 	.resets = r9a09g011_resets,
 	.num_resets = ARRAY_SIZE(r9a09g011_resets),
 
+	/* PM domains */
+	.pm_domains = r9a09g011_pm_domains,
+	.num_pm_domains = ARRAY_SIZE(r9a09g011_pm_domains),
+
 	.has_clk_mon_regs = false,
 };
-- 
2.39.2

Re: [PATCH 11/17] clk: renesas: r9a09g011: Add initial support for power domains

[Geert Uytterhoeven]

Hi Claudiu,

On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Instantiate always-on power domain for R9A09G011 SoC. At the moment, all
> the IPs are part of this domain.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

As not all IPs are part of the always-on domain, I'd rather defer this
until all domains are handled in the driver.
Note that RZ/V2M does not have CPG_BUS_*_MSTOP registers,
but uses the Internal Power Domain Controller (PMC).

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 12/17] arm64: dts: renesas: rzg3s-smarc-som: Guard the ethernet IRQ GPIOs with proper flags

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Ethernet IRQ GPIOs are marked as gpio-hog. Thus, these GPIOs are requested
at probe w/o considering if there are other peripherals that needs them.
The Ethernet IRQ GPIOs are shared w/ SDHI2. Selection b/w Ethernet and
SDHI2 is done through a hardware switch. To avoid scenarios where one wants
to boot with SDHI2 support and some SDHI pins are not propertly configured
because of gpio-hog guard Ethernet IRQ GPIO with proper build flag.

Fixes: 932ff0c802c6 ("arm64: dts: renesas: rzg3s-smarc-som: Enable the Ethernet interfaces")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index 2b7fa5817d58..acac4666ae59 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -193,12 +193,14 @@ &sdhi2 {
 #endif
 
 &pinctrl {
+#if SW_CONFIG3 == SW_ON
 	eth0-phy-irq-hog {
 		gpio-hog;
 		gpios = <RZG2L_GPIO(12, 0) GPIO_ACTIVE_LOW>;
 		input;
 		line-name = "eth0-phy-irq";
 	};
+#endif
 
 	eth0_pins: eth0 {
 		txc {
@@ -234,12 +236,14 @@ mux {
 		};
 	};
 
+#if SW_CONFIG3 == SW_ON
 	eth1-phy-irq-hog {
 		gpio-hog;
 		gpios = <RZG2L_GPIO(12, 1) GPIO_ACTIVE_LOW>;
 		input;
 		line-name = "eth1-phy-irq";
 	};
+#endif
 
 	eth1_pins: eth1 {
 		txc {
-- 
2.39.2

Re: [PATCH 12/17] arm64: dts: renesas: rzg3s-smarc-som: Guard the ethernet IRQ GPIOs with proper flags

[Geert Uytterhoeven]

Hi Claudiu,

On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Ethernet IRQ GPIOs are marked as gpio-hog. Thus, these GPIOs are requested
> at probe w/o considering if there are other peripherals that needs them.
> The Ethernet IRQ GPIOs are shared w/ SDHI2. Selection b/w Ethernet and
> SDHI2 is done through a hardware switch. To avoid scenarios where one wants
> to boot with SDHI2 support and some SDHI pins are not propertly configured
> because of gpio-hog guard Ethernet IRQ GPIO with proper build flag.
>
> Fixes: 932ff0c802c6 ("arm64: dts: renesas: rzg3s-smarc-som: Enable the Ethernet interfaces")
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Thanks for your patch! (which was well-hidden between non-fixes ;-)

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.9.

As Ethernet is enabled by default, I think there is no need to fast-track
this for v6.8.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 12/17] arm64: dts: renesas: rzg3s-smarc-som: Guard the ethernet IRQ GPIOs with proper flags

[claudiu beznea]

On 16.02.2024 16:17, Geert Uytterhoeven wrote:
> Hi Claudiu,
> 
> On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Ethernet IRQ GPIOs are marked as gpio-hog. Thus, these GPIOs are requested
>> at probe w/o considering if there are other peripherals that needs them.
>> The Ethernet IRQ GPIOs are shared w/ SDHI2. Selection b/w Ethernet and
>> SDHI2 is done through a hardware switch. To avoid scenarios where one wants
>> to boot with SDHI2 support and some SDHI pins are not propertly configured
>> because of gpio-hog guard Ethernet IRQ GPIO with proper build flag.
>>
>> Fixes: 932ff0c802c6 ("arm64: dts: renesas: rzg3s-smarc-som: Enable the Ethernet interfaces")
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Thanks for your patch! (which was well-hidden between non-fixes ;-)

Sorry about that.

> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> i.e. will queue in renesas-devel for v6.9.
> 
> As Ethernet is enabled by default, I think there is no need to fast-track
> this for v6.8.

Right!

Thank you,
Claudiu Beznea

> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 

[PATCH 13/17] arm64: dts: renesas: r9a07g043: Update #power-domain-cells = <1>

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Update CPG #power-domain-cells = <1> and move all the IPs to be part of the
always on power domain as the driver has been modified to support multiple
power domains.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g043.dtsi  | 84 ++++++++++-----------
 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi |  6 +-
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi |  2 +-
 3 files changed, 46 insertions(+), 46 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 8721f4c9fa0f..3e12f9dd3c6a 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -138,7 +138,7 @@ mtu3: timer@10001200 {
 					  "tgia8", "tgib8", "tgic8", "tgid8",
 					  "tciv8", "tciu8";
 			clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>;
 			#pwm-cells = <2>;
 			status = "disabled";
@@ -159,7 +159,7 @@ ssi0: ssi@10049c00 {
 			resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
 			dmas = <&dmac 0x2655>, <&dmac 0x2656>;
 			dma-names = "tx", "rx";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			#sound-dai-cells = <0>;
 			status = "disabled";
 		};
@@ -179,7 +179,7 @@ ssi1: ssi@1004a000 {
 			resets = <&cpg R9A07G043_SSI1_RST_M2_REG>;
 			dmas = <&dmac 0x2659>, <&dmac 0x265a>;
 			dma-names = "tx", "rx";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			#sound-dai-cells = <0>;
 			status = "disabled";
 		};
@@ -198,7 +198,7 @@ ssi2: ssi@1004a400 {
 			resets = <&cpg R9A07G043_SSI2_RST_M2_REG>;
 			dmas = <&dmac 0x265f>;
 			dma-names = "rt";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			#sound-dai-cells = <0>;
 			status = "disabled";
 		};
@@ -218,7 +218,7 @@ ssi3: ssi@1004a800 {
 			resets = <&cpg R9A07G043_SSI3_RST_M2_REG>;
 			dmas = <&dmac 0x2661>, <&dmac 0x2662>;
 			dma-names = "tx", "rx";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			#sound-dai-cells = <0>;
 			status = "disabled";
 		};
@@ -234,7 +234,7 @@ spi0: spi@1004ac00 {
 			resets = <&cpg R9A07G043_RSPI0_RST>;
 			dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
 			dma-names = "tx", "rx";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			num-cs = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -252,7 +252,7 @@ spi1: spi@1004b000 {
 			resets = <&cpg R9A07G043_RSPI1_RST>;
 			dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
 			dma-names = "tx", "rx";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			num-cs = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -270,7 +270,7 @@ spi2: spi@1004b400 {
 			resets = <&cpg R9A07G043_RSPI2_RST>;
 			dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
 			dma-names = "tx", "rx";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			num-cs = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -291,7 +291,7 @@ scif0: serial@1004b800 {
 					  "bri", "dri", "tei";
 			clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
 			status = "disabled";
 		};
@@ -310,7 +310,7 @@ scif1: serial@1004bc00 {
 					  "bri", "dri", "tei";
 			clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>;
 			status = "disabled";
 		};
@@ -329,7 +329,7 @@ scif2: serial@1004c000 {
 					  "bri", "dri", "tei";
 			clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>;
 			status = "disabled";
 		};
@@ -348,7 +348,7 @@ scif3: serial@1004c400 {
 					  "bri", "dri", "tei";
 			clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>;
 			status = "disabled";
 		};
@@ -367,7 +367,7 @@ scif4: serial@1004c800 {
 					  "bri", "dri", "tei";
 			clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>;
 			status = "disabled";
 		};
@@ -382,7 +382,7 @@ sci0: serial@1004d000 {
 			interrupt-names = "eri", "rxi", "txi", "tei";
 			clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G043_SCI0_RST>;
 			status = "disabled";
 		};
@@ -397,7 +397,7 @@ sci1: serial@1004d400 {
 			interrupt-names = "eri", "rxi", "txi", "tei";
 			clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G043_SCI1_RST>;
 			status = "disabled";
 		};
@@ -425,7 +425,7 @@ canfd: can@10050000 {
 			resets = <&cpg R9A07G043_CANFD_RSTP_N>,
 				 <&cpg R9A07G043_CANFD_RSTC_N>;
 			reset-names = "rstp_n", "rstc_n";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			status = "disabled";
 
 			channel0 {
@@ -454,7 +454,7 @@ i2c0: i2c@10058000 {
 			clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>;
 			clock-frequency = <100000>;
 			resets = <&cpg R9A07G043_I2C0_MRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -476,7 +476,7 @@ i2c1: i2c@10058400 {
 			clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>;
 			clock-frequency = <100000>;
 			resets = <&cpg R9A07G043_I2C1_MRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -498,7 +498,7 @@ i2c2: i2c@10058800 {
 			clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>;
 			clock-frequency = <100000>;
 			resets = <&cpg R9A07G043_I2C2_MRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -520,7 +520,7 @@ i2c3: i2c@10058c00 {
 			clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>;
 			clock-frequency = <100000>;
 			resets = <&cpg R9A07G043_I2C3_MRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -534,7 +534,7 @@ adc: adc@10059000 {
 			resets = <&cpg R9A07G043_ADC_PRESETN>,
 				 <&cpg R9A07G043_ADC_ADRST_N>;
 			reset-names = "presetn", "adrst-n";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			status = "disabled";
 
 			#address-cells = <1>;
@@ -554,7 +554,7 @@ tsu: thermal@10059400 {
 			reg = <0 0x10059400 0 0x400>;
 			clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>;
 			resets = <&cpg R9A07G043_TSU_PRESETN>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			#thermal-sensor-cells = <1>;
 		};
 
@@ -568,7 +568,7 @@ sbc: spi@10060000 {
 			clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>,
 				 <&cpg CPG_MOD R9A07G043_SPI_CLK>;
 			resets = <&cpg R9A07G043_SPI_RST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -581,7 +581,7 @@ cpg: clock-controller@11010000 {
 			clock-names = "extal";
 			#clock-cells = <2>;
 			#reset-cells = <1>;
-			#power-domain-cells = <0>;
+			#power-domain-cells = <1>;
 		};
 
 		sysc: system-controller@11020000 {
@@ -599,7 +599,7 @@ pinctrl: pinctrl@11030000 {
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G043_GPIO_RSTN>,
 				 <&cpg R9A07G043_GPIO_PORT_RESETN>,
 				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
@@ -635,7 +635,7 @@ dmac: dma-controller@11820000 {
 			clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>,
 				 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>;
 			clock-names = "main", "register";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G043_DMAC_ARESETN>,
 				 <&cpg R9A07G043_DMAC_RST_ASYNC>;
 			reset-names = "arst", "rst_async";
@@ -655,7 +655,7 @@ sdhi0: mmc@11c00000 {
 				 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
 			resets = <&cpg R9A07G043_SDHI0_IXRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -671,7 +671,7 @@ sdhi1: mmc@11c10000 {
 				 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
 			resets = <&cpg R9A07G043_SDHI1_IXRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -689,7 +689,7 @@ eth0: ethernet@11c20000 {
 				 <&cpg CPG_CORE R9A07G043_CLK_HP>;
 			clock-names = "axi", "chi", "refclk";
 			resets = <&cpg R9A07G043_ETH0_RST_HW_N>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -709,7 +709,7 @@ eth1: ethernet@11c30000 {
 				 <&cpg CPG_CORE R9A07G043_CLK_HP>;
 			clock-names = "axi", "chi", "refclk";
 			resets = <&cpg R9A07G043_ETH1_RST_HW_N>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -721,7 +721,7 @@ phyrst: usbphy-ctrl@11c40000 {
 			reg = <0 0x11c40000 0 0x10000>;
 			clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>;
 			resets = <&cpg R9A07G043_USB_PRESETN>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			#reset-cells = <1>;
 			status = "disabled";
 		};
@@ -736,7 +736,7 @@ ohci0: usb@11c50000 {
 				 <&cpg R9A07G043_USB_U2H0_HRESETN>;
 			phys = <&usb2_phy0 1>;
 			phy-names = "usb";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -750,7 +750,7 @@ ohci1: usb@11c70000 {
 				 <&cpg R9A07G043_USB_U2H1_HRESETN>;
 			phys = <&usb2_phy1 1>;
 			phy-names = "usb";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -765,7 +765,7 @@ ehci0: usb@11c50100 {
 			phys = <&usb2_phy0 2>;
 			phy-names = "usb";
 			companion = <&ohci0>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -780,7 +780,7 @@ ehci1: usb@11c70100 {
 			phys = <&usb2_phy1 2>;
 			phy-names = "usb";
 			companion = <&ohci1>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -793,7 +793,7 @@ usb2_phy0: usb-phy@11c50200 {
 				 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
 			resets = <&phyrst 0>;
 			#phy-cells = <1>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -806,7 +806,7 @@ usb2_phy1: usb-phy@11c70200 {
 				 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
 			resets = <&phyrst 1>;
 			#phy-cells = <1>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -825,7 +825,7 @@ hsusb: usb@11c60000 {
 			renesas,buswait = <7>;
 			phys = <&usb2_phy0 3>;
 			phy-names = "usb";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -840,7 +840,7 @@ wdt0: watchdog@12800800 {
 				     <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "wdt", "perrout";
 			resets = <&cpg R9A07G043_WDT0_PRESETN>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -851,7 +851,7 @@ ostm0: timer@12801000 {
 			interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_EDGE_RISING>;
 			clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>;
 			resets = <&cpg R9A07G043_OSTM0_PRESETZ>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -862,7 +862,7 @@ ostm1: timer@12801400 {
 			interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_EDGE_RISING>;
 			clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>;
 			resets = <&cpg R9A07G043_OSTM1_PRESETZ>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -873,7 +873,7 @@ ostm2: timer@12801800 {
 			interrupts = <SOC_PERIPHERAL_IRQ(48) IRQ_TYPE_EDGE_RISING>;
 			clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>;
 			resets = <&cpg R9A07G043_OSTM2_PRESETZ>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index 01d08ebb4a78..1ac71b9cbbb6 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -75,7 +75,7 @@ cru: video@10830000 {
 		resets = <&cpg R9A07G043_CRU_PRESETN>,
 			 <&cpg R9A07G043_CRU_ARESETN>;
 		reset-names = "presetn", "aresetn";
-		power-domains = <&cpg>;
+		power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 		status = "disabled";
 
 		ports {
@@ -106,7 +106,7 @@ csi2: csi2@10830400 {
 		resets = <&cpg R9A07G043_CRU_PRESETN>,
 			 <&cpg R9A07G043_CRU_CMN_RSTB>;
 		reset-names = "presetn", "cmn-rstb";
-		power-domains = <&cpg>;
+		power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 		status = "disabled";
 
 		ports {
@@ -194,7 +194,7 @@ irqc: interrupt-controller@110a0000 {
 		clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>,
 			<&cpg CPG_MOD R9A07G043_IA55_PCLK>;
 		clock-names = "clk", "pclk";
-		power-domains = <&cpg>;
+		power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 		resets = <&cpg R9A07G043_IA55_RESETN>;
 	};
 
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index 09ef10b39f46..925203746b28 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -62,7 +62,7 @@ plic: interrupt-controller@12c00000 {
 		interrupt-controller;
 		reg = <0x0 0x12c00000 0 0x400000>;
 		clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
-		power-domains = <&cpg>;
+		power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;
 		resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
 		interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
 	};
-- 
2.39.2

Re: [PATCH 13/17] arm64: dts: renesas: r9a07g043: Update #power-domain-cells = <1>

[Geert Uytterhoeven]

Hi Claudiu,

On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Update CPG #power-domain-cells = <1> and move all the IPs to be part of the
> always on power domain as the driver has been modified to support multiple
> power domains.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> @@ -138,7 +138,7 @@ mtu3: timer@10001200 {
>                                           "tgia8", "tgib8", "tgic8", "tgid8",
>                                           "tciv8", "tciu8";
>                         clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>;
> -                       power-domains = <&cpg>;
> +                       power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>;

This should be R9A07G043_PD_MTU, but that domain is not yet supported
by the driver.  Instead of adding incorrect hardware descriptions,
I'd rather defer this until all domains are handled by the driver.

>                         resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>;
>                         #pwm-cells = <2>;
>                         status = "disabled";

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 14/17] arm64: dts: renesas: r9a07g044: Update #power-domain-cells = <1>

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Update CPG #power-domain-cells = <1> and move all the IPs to be part of the
always on power domain as the driver has been modified to support multiple
power domains.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 100 ++++++++++-----------
 1 file changed, 50 insertions(+), 50 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 66f68fc2b241..c6aa62351b89 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -238,7 +238,7 @@ mtu3: timer@10001200 {
 					  "tgia8", "tgib8", "tgic8", "tgid8",
 					  "tciv8", "tciu8";
 			clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
 			#pwm-cells = <2>;
 			status = "disabled";
@@ -259,7 +259,7 @@ ssi0: ssi@10049c00 {
 			resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
 			dmas = <&dmac 0x2655>, <&dmac 0x2656>;
 			dma-names = "tx", "rx";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			#sound-dai-cells = <0>;
 			status = "disabled";
 		};
@@ -279,7 +279,7 @@ ssi1: ssi@1004a000 {
 			resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
 			dmas = <&dmac 0x2659>, <&dmac 0x265a>;
 			dma-names = "tx", "rx";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			#sound-dai-cells = <0>;
 			status = "disabled";
 		};
@@ -298,7 +298,7 @@ ssi2: ssi@1004a400 {
 			resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
 			dmas = <&dmac 0x265f>;
 			dma-names = "rt";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			#sound-dai-cells = <0>;
 			status = "disabled";
 		};
@@ -318,7 +318,7 @@ ssi3: ssi@1004a800 {
 			resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
 			dmas = <&dmac 0x2661>, <&dmac 0x2662>;
 			dma-names = "tx", "rx";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			#sound-dai-cells = <0>;
 			status = "disabled";
 		};
@@ -334,7 +334,7 @@ spi0: spi@1004ac00 {
 			resets = <&cpg R9A07G044_RSPI0_RST>;
 			dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
 			dma-names = "tx", "rx";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			num-cs = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -352,7 +352,7 @@ spi1: spi@1004b000 {
 			resets = <&cpg R9A07G044_RSPI1_RST>;
 			dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
 			dma-names = "tx", "rx";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			num-cs = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -370,7 +370,7 @@ spi2: spi@1004b400 {
 			resets = <&cpg R9A07G044_RSPI2_RST>;
 			dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
 			dma-names = "tx", "rx";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			num-cs = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -390,7 +390,7 @@ scif0: serial@1004b800 {
 					  "bri", "dri", "tei";
 			clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
 			status = "disabled";
 		};
@@ -408,7 +408,7 @@ scif1: serial@1004bc00 {
 					  "bri", "dri", "tei";
 			clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
 			status = "disabled";
 		};
@@ -426,7 +426,7 @@ scif2: serial@1004c000 {
 					  "bri", "dri", "tei";
 			clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
 			status = "disabled";
 		};
@@ -444,7 +444,7 @@ scif3: serial@1004c400 {
 					  "bri", "dri", "tei";
 			clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
 			status = "disabled";
 		};
@@ -462,7 +462,7 @@ scif4: serial@1004c800 {
 					  "bri", "dri", "tei";
 			clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
 			status = "disabled";
 		};
@@ -477,7 +477,7 @@ sci0: serial@1004d000 {
 			interrupt-names = "eri", "rxi", "txi", "tei";
 			clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G044_SCI0_RST>;
 			status = "disabled";
 		};
@@ -492,7 +492,7 @@ sci1: serial@1004d400 {
 			interrupt-names = "eri", "rxi", "txi", "tei";
 			clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G044_SCI1_RST>;
 			status = "disabled";
 		};
@@ -520,7 +520,7 @@ canfd: can@10050000 {
 			resets = <&cpg R9A07G044_CANFD_RSTP_N>,
 				 <&cpg R9A07G044_CANFD_RSTC_N>;
 			reset-names = "rstp_n", "rstc_n";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 
 			channel0 {
@@ -549,7 +549,7 @@ i2c0: i2c@10058000 {
 			clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
 			clock-frequency = <100000>;
 			resets = <&cpg R9A07G044_I2C0_MRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -571,7 +571,7 @@ i2c1: i2c@10058400 {
 			clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
 			clock-frequency = <100000>;
 			resets = <&cpg R9A07G044_I2C1_MRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -593,7 +593,7 @@ i2c2: i2c@10058800 {
 			clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
 			clock-frequency = <100000>;
 			resets = <&cpg R9A07G044_I2C2_MRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -615,7 +615,7 @@ i2c3: i2c@10058c00 {
 			clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
 			clock-frequency = <100000>;
 			resets = <&cpg R9A07G044_I2C3_MRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -629,7 +629,7 @@ adc: adc@10059000 {
 			resets = <&cpg R9A07G044_ADC_PRESETN>,
 				 <&cpg R9A07G044_ADC_ADRST_N>;
 			reset-names = "presetn", "adrst-n";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 
 			#address-cells = <1>;
@@ -667,7 +667,7 @@ tsu: thermal@10059400 {
 			reg = <0 0x10059400 0 0x400>;
 			clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
 			resets = <&cpg R9A07G044_TSU_PRESETN>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			#thermal-sensor-cells = <1>;
 		};
 
@@ -682,7 +682,7 @@ sbc: spi@10060000 {
 			clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,
 				 <&cpg CPG_MOD R9A07G044_SPI_CLK>;
 			resets = <&cpg R9A07G044_SPI_RST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -702,7 +702,7 @@ cru: video@10830000 {
 			resets = <&cpg R9A07G044_CRU_PRESETN>,
 				 <&cpg R9A07G044_CRU_ARESETN>;
 			reset-names = "presetn", "aresetn";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 
 			ports {
@@ -743,7 +743,7 @@ csi2: csi2@10830400 {
 			resets = <&cpg R9A07G044_CRU_PRESETN>,
 				 <&cpg R9A07G044_CRU_CMN_RSTB>;
 			reset-names = "presetn", "cmn-rstb";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 
 			ports {
@@ -791,7 +791,7 @@ dsi: dsi@10850000 {
 				 <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
 				 <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
 			reset-names = "rst", "arst", "prst";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -803,7 +803,7 @@ vspd: vsp@10870000 {
 				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
 				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
 			clock-names = "aclk", "pclk", "vclk";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G044_LCDC_RESET_N>;
 			renesas,fcp = <&fcpvd>;
 		};
@@ -816,7 +816,7 @@ fcpvd: fcp@10880000 {
 				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
 				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
 			clock-names = "aclk", "pclk", "vclk";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G044_LCDC_RESET_N>;
 		};
 
@@ -827,7 +827,7 @@ cpg: clock-controller@11010000 {
 			clock-names = "extal";
 			#clock-cells = <2>;
 			#reset-cells = <1>;
-			#power-domain-cells = <0>;
+			#power-domain-cells = <1>;
 		};
 
 		sysc: system-controller@11020000 {
@@ -852,7 +852,7 @@ pinctrl: pinctrl@11030000 {
 			interrupt-controller;
 			gpio-ranges = <&pinctrl 0 0 392>;
 			clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G044_GPIO_RSTN>,
 				 <&cpg R9A07G044_GPIO_PORT_RESETN>,
 				 <&cpg R9A07G044_GPIO_SPARE_RESETN>;
@@ -909,7 +909,7 @@ irqc: interrupt-controller@110a0000 {
 			clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
 				 <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
 			clock-names = "clk", "pclk";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G044_IA55_RESETN>;
 		};
 
@@ -943,7 +943,7 @@ dmac: dma-controller@11820000 {
 			clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
 				 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
 			clock-names = "main", "register";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G044_DMAC_ARESETN>,
 				 <&cpg R9A07G044_DMAC_RST_ASYNC>;
 			reset-names = "arst", "rst_async";
@@ -964,7 +964,7 @@ gpu: gpu@11840000 {
 				 <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>,
 				 <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>;
 			clock-names = "gpu", "bus", "bus_ace";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G044_GPU_RESETN>,
 				 <&cpg R9A07G044_GPU_AXI_RESETN>,
 				 <&cpg R9A07G044_GPU_ACE_RESETN>;
@@ -994,7 +994,7 @@ sdhi0: mmc@11c00000 {
 				 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
 			resets = <&cpg R9A07G044_SDHI0_IXRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1010,7 +1010,7 @@ sdhi1: mmc@11c10000 {
 				 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
 			resets = <&cpg R9A07G044_SDHI1_IXRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1028,7 +1028,7 @@ eth0: ethernet@11c20000 {
 				 <&cpg CPG_CORE R9A07G044_CLK_HP>;
 			clock-names = "axi", "chi", "refclk";
 			resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -1048,7 +1048,7 @@ eth1: ethernet@11c30000 {
 				 <&cpg CPG_CORE R9A07G044_CLK_HP>;
 			clock-names = "axi", "chi", "refclk";
 			resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -1060,7 +1060,7 @@ phyrst: usbphy-ctrl@11c40000 {
 			reg = <0 0x11c40000 0 0x10000>;
 			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
 			resets = <&cpg R9A07G044_USB_PRESETN>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			#reset-cells = <1>;
 			status = "disabled";
 		};
@@ -1075,7 +1075,7 @@ ohci0: usb@11c50000 {
 				 <&cpg R9A07G044_USB_U2H0_HRESETN>;
 			phys = <&usb2_phy0 1>;
 			phy-names = "usb";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1089,7 +1089,7 @@ ohci1: usb@11c70000 {
 				 <&cpg R9A07G044_USB_U2H1_HRESETN>;
 			phys = <&usb2_phy1 1>;
 			phy-names = "usb";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1104,7 +1104,7 @@ ehci0: usb@11c50100 {
 			phys = <&usb2_phy0 2>;
 			phy-names = "usb";
 			companion = <&ohci0>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1119,7 +1119,7 @@ ehci1: usb@11c70100 {
 			phys = <&usb2_phy1 2>;
 			phy-names = "usb";
 			companion = <&ohci1>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1132,7 +1132,7 @@ usb2_phy0: usb-phy@11c50200 {
 				 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
 			resets = <&phyrst 0>;
 			#phy-cells = <1>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1145,7 +1145,7 @@ usb2_phy1: usb-phy@11c70200 {
 				 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
 			resets = <&phyrst 1>;
 			#phy-cells = <1>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1164,7 +1164,7 @@ hsusb: usb@11c60000 {
 			renesas,buswait = <7>;
 			phys = <&usb2_phy0 3>;
 			phy-names = "usb";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1179,7 +1179,7 @@ wdt0: watchdog@12800800 {
 				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "wdt", "perrout";
 			resets = <&cpg R9A07G044_WDT0_PRESETN>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1194,7 +1194,7 @@ wdt1: watchdog@12800c00 {
 				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "wdt", "perrout";
 			resets = <&cpg R9A07G044_WDT1_PRESETN>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1205,7 +1205,7 @@ ostm0: timer@12801000 {
 			interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
 			clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>;
 			resets = <&cpg R9A07G044_OSTM0_PRESETZ>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1216,7 +1216,7 @@ ostm1: timer@12801400 {
 			interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
 			clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>;
 			resets = <&cpg R9A07G044_OSTM1_PRESETZ>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1227,7 +1227,7 @@ ostm2: timer@12801800 {
 			interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
 			clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>;
 			resets = <&cpg R9A07G044_OSTM2_PRESETZ>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 	};
-- 
2.39.2

Re: [PATCH 14/17] arm64: dts: renesas: r9a07g044: Update #power-domain-cells = <1>

[Geert Uytterhoeven]

Hi Claudiu,

On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Update CPG #power-domain-cells = <1> and move all the IPs to be part of the
> always on power domain as the driver has been modified to support multiple
> power domains.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> @@ -238,7 +238,7 @@ mtu3: timer@10001200 {
>                                           "tgia8", "tgib8", "tgic8", "tgid8",
>                                           "tciv8", "tciu8";
>                         clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
> -                       power-domains = <&cpg>;
> +                       power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>;

This should be R9A07G044_PD_MTU, but that domain is not yet supported
by the driver.  Instead of adding incorrect hardware descriptions,
I'd rather defer this until all domains are handled by the driver.

>                         resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
>                         #pwm-cells = <2>;
>                         status = "disabled";

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 15/17] arm64: dts: renesas: r9a07g054: Update #power-domain-cells = <1>

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Update CPG #power-domain-cells = <1> and move all the IPs to be part of the
always on power domain as the driver has been modified to support multiple
power domains.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 100 ++++++++++-----------
 1 file changed, 50 insertions(+), 50 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 1f1d481dc783..15fc6e6f79ce 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -238,7 +238,7 @@ mtu3: timer@10001200 {
 					  "tgia8", "tgib8", "tgic8", "tgid8",
 					  "tciv8", "tciu8";
 			clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;
 			#pwm-cells = <2>;
 			status = "disabled";
@@ -259,7 +259,7 @@ ssi0: ssi@10049c00 {
 			resets = <&cpg R9A07G054_SSI0_RST_M2_REG>;
 			dmas = <&dmac 0x2655>, <&dmac 0x2656>;
 			dma-names = "tx", "rx";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			#sound-dai-cells = <0>;
 			status = "disabled";
 		};
@@ -279,7 +279,7 @@ ssi1: ssi@1004a000 {
 			resets = <&cpg R9A07G054_SSI1_RST_M2_REG>;
 			dmas = <&dmac 0x2659>, <&dmac 0x265a>;
 			dma-names = "tx", "rx";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			#sound-dai-cells = <0>;
 			status = "disabled";
 		};
@@ -298,7 +298,7 @@ ssi2: ssi@1004a400 {
 			resets = <&cpg R9A07G054_SSI2_RST_M2_REG>;
 			dmas = <&dmac 0x265f>;
 			dma-names = "rt";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			#sound-dai-cells = <0>;
 			status = "disabled";
 		};
@@ -318,7 +318,7 @@ ssi3: ssi@1004a800 {
 			resets = <&cpg R9A07G054_SSI3_RST_M2_REG>;
 			dmas = <&dmac 0x2661>, <&dmac 0x2662>;
 			dma-names = "tx", "rx";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			#sound-dai-cells = <0>;
 			status = "disabled";
 		};
@@ -334,7 +334,7 @@ spi0: spi@1004ac00 {
 			resets = <&cpg R9A07G054_RSPI0_RST>;
 			dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
 			dma-names = "tx", "rx";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			num-cs = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -352,7 +352,7 @@ spi1: spi@1004b000 {
 			resets = <&cpg R9A07G054_RSPI1_RST>;
 			dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
 			dma-names = "tx", "rx";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			num-cs = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -370,7 +370,7 @@ spi2: spi@1004b400 {
 			resets = <&cpg R9A07G054_RSPI2_RST>;
 			dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
 			dma-names = "tx", "rx";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			num-cs = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -391,7 +391,7 @@ scif0: serial@1004b800 {
 					  "bri", "dri", "tei";
 			clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>;
 			status = "disabled";
 		};
@@ -410,7 +410,7 @@ scif1: serial@1004bc00 {
 					  "bri", "dri", "tei";
 			clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>;
 			status = "disabled";
 		};
@@ -429,7 +429,7 @@ scif2: serial@1004c000 {
 					  "bri", "dri", "tei";
 			clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>;
 			status = "disabled";
 		};
@@ -448,7 +448,7 @@ scif3: serial@1004c400 {
 					  "bri", "dri", "tei";
 			clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>;
 			status = "disabled";
 		};
@@ -467,7 +467,7 @@ scif4: serial@1004c800 {
 					  "bri", "dri", "tei";
 			clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>;
 			status = "disabled";
 		};
@@ -482,7 +482,7 @@ sci0: serial@1004d000 {
 			interrupt-names = "eri", "rxi", "txi", "tei";
 			clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G054_SCI0_RST>;
 			status = "disabled";
 		};
@@ -497,7 +497,7 @@ sci1: serial@1004d400 {
 			interrupt-names = "eri", "rxi", "txi", "tei";
 			clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G054_SCI1_RST>;
 			status = "disabled";
 		};
@@ -525,7 +525,7 @@ canfd: can@10050000 {
 			resets = <&cpg R9A07G054_CANFD_RSTP_N>,
 				 <&cpg R9A07G054_CANFD_RSTC_N>;
 			reset-names = "rstp_n", "rstc_n";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 
 			channel0 {
@@ -554,7 +554,7 @@ i2c0: i2c@10058000 {
 			clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>;
 			clock-frequency = <100000>;
 			resets = <&cpg R9A07G054_I2C0_MRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -576,7 +576,7 @@ i2c1: i2c@10058400 {
 			clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>;
 			clock-frequency = <100000>;
 			resets = <&cpg R9A07G054_I2C1_MRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -598,7 +598,7 @@ i2c2: i2c@10058800 {
 			clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>;
 			clock-frequency = <100000>;
 			resets = <&cpg R9A07G054_I2C2_MRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -620,7 +620,7 @@ i2c3: i2c@10058c00 {
 			clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>;
 			clock-frequency = <100000>;
 			resets = <&cpg R9A07G054_I2C3_MRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -634,7 +634,7 @@ adc: adc@10059000 {
 			resets = <&cpg R9A07G054_ADC_PRESETN>,
 				 <&cpg R9A07G054_ADC_ADRST_N>;
 			reset-names = "presetn", "adrst-n";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 
 			#address-cells = <1>;
@@ -672,7 +672,7 @@ tsu: thermal@10059400 {
 			reg = <0 0x10059400 0 0x400>;
 			clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>;
 			resets = <&cpg R9A07G054_TSU_PRESETN>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			#thermal-sensor-cells = <1>;
 		};
 
@@ -687,7 +687,7 @@ sbc: spi@10060000 {
 			clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>,
 				 <&cpg CPG_MOD R9A07G054_SPI_CLK>;
 			resets = <&cpg R9A07G054_SPI_RST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -707,7 +707,7 @@ cru: video@10830000 {
 			resets = <&cpg R9A07G054_CRU_PRESETN>,
 				 <&cpg R9A07G054_CRU_ARESETN>;
 			reset-names = "presetn", "aresetn";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 
 			ports {
@@ -748,7 +748,7 @@ csi2: csi2@10830400 {
 			resets = <&cpg R9A07G054_CRU_PRESETN>,
 				 <&cpg R9A07G054_CRU_CMN_RSTB>;
 			reset-names = "presetn", "cmn-rstb";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 
 			ports {
@@ -796,7 +796,7 @@ dsi: dsi@10850000 {
 				 <&cpg R9A07G054_MIPI_DSI_ARESET_N>,
 				 <&cpg R9A07G054_MIPI_DSI_PRESET_N>;
 			reset-names = "rst", "arst", "prst";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -809,7 +809,7 @@ vspd: vsp@10870000 {
 				 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
 				 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
 			clock-names = "aclk", "pclk", "vclk";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G054_LCDC_RESET_N>;
 			renesas,fcp = <&fcpvd>;
 		};
@@ -822,7 +822,7 @@ fcpvd: fcp@10880000 {
 				 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
 				 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
 			clock-names = "aclk", "pclk", "vclk";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G054_LCDC_RESET_N>;
 		};
 
@@ -833,7 +833,7 @@ cpg: clock-controller@11010000 {
 			clock-names = "extal";
 			#clock-cells = <2>;
 			#reset-cells = <1>;
-			#power-domain-cells = <0>;
+			#power-domain-cells = <1>;
 		};
 
 		sysc: system-controller@11020000 {
@@ -859,7 +859,7 @@ pinctrl: pinctrl@11030000 {
 			interrupt-controller;
 			gpio-ranges = <&pinctrl 0 0 392>;
 			clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G054_GPIO_RSTN>,
 				 <&cpg R9A07G054_GPIO_PORT_RESETN>,
 				 <&cpg R9A07G054_GPIO_SPARE_RESETN>;
@@ -916,7 +916,7 @@ irqc: interrupt-controller@110a0000 {
 			clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>,
 				 <&cpg CPG_MOD R9A07G054_IA55_PCLK>;
 			clock-names = "clk", "pclk";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G054_IA55_RESETN>;
 		};
 
@@ -950,7 +950,7 @@ dmac: dma-controller@11820000 {
 			clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
 				 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
 			clock-names = "main", "register";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G054_DMAC_ARESETN>,
 				 <&cpg R9A07G054_DMAC_RST_ASYNC>;
 			reset-names = "arst", "rst_async";
@@ -971,7 +971,7 @@ gpu: gpu@11840000 {
 				 <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>,
 				 <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>;
 			clock-names = "gpu", "bus", "bus_ace";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			resets = <&cpg R9A07G054_GPU_RESETN>,
 				 <&cpg R9A07G054_GPU_AXI_RESETN>,
 				 <&cpg R9A07G054_GPU_ACE_RESETN>;
@@ -1001,7 +1001,7 @@ sdhi0: mmc@11c00000 {
 				 <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
 			resets = <&cpg R9A07G054_SDHI0_IXRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1017,7 +1017,7 @@ sdhi1: mmc@11c10000 {
 				 <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
 			resets = <&cpg R9A07G054_SDHI1_IXRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1035,7 +1035,7 @@ eth0: ethernet@11c20000 {
 				 <&cpg CPG_CORE R9A07G054_CLK_HP>;
 			clock-names = "axi", "chi", "refclk";
 			resets = <&cpg R9A07G054_ETH0_RST_HW_N>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -1055,7 +1055,7 @@ eth1: ethernet@11c30000 {
 				 <&cpg CPG_CORE R9A07G054_CLK_HP>;
 			clock-names = "axi", "chi", "refclk";
 			resets = <&cpg R9A07G054_ETH1_RST_HW_N>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -1067,7 +1067,7 @@ phyrst: usbphy-ctrl@11c40000 {
 			reg = <0 0x11c40000 0 0x10000>;
 			clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>;
 			resets = <&cpg R9A07G054_USB_PRESETN>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			#reset-cells = <1>;
 			status = "disabled";
 		};
@@ -1082,7 +1082,7 @@ ohci0: usb@11c50000 {
 				 <&cpg R9A07G054_USB_U2H0_HRESETN>;
 			phys = <&usb2_phy0 1>;
 			phy-names = "usb";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1096,7 +1096,7 @@ ohci1: usb@11c70000 {
 				 <&cpg R9A07G054_USB_U2H1_HRESETN>;
 			phys = <&usb2_phy1 1>;
 			phy-names = "usb";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1111,7 +1111,7 @@ ehci0: usb@11c50100 {
 			phys = <&usb2_phy0 2>;
 			phy-names = "usb";
 			companion = <&ohci0>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1126,7 +1126,7 @@ ehci1: usb@11c70100 {
 			phys = <&usb2_phy1 2>;
 			phy-names = "usb";
 			companion = <&ohci1>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1139,7 +1139,7 @@ usb2_phy0: usb-phy@11c50200 {
 				 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
 			resets = <&phyrst 0>;
 			#phy-cells = <1>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1152,7 +1152,7 @@ usb2_phy1: usb-phy@11c70200 {
 				 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
 			resets = <&phyrst 1>;
 			#phy-cells = <1>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1171,7 +1171,7 @@ hsusb: usb@11c60000 {
 			renesas,buswait = <7>;
 			phys = <&usb2_phy0 3>;
 			phy-names = "usb";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1186,7 +1186,7 @@ wdt0: watchdog@12800800 {
 				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "wdt", "perrout";
 			resets = <&cpg R9A07G054_WDT0_PRESETN>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1201,7 +1201,7 @@ wdt1: watchdog@12800c00 {
 				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "wdt", "perrout";
 			resets = <&cpg R9A07G054_WDT1_PRESETN>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1212,7 +1212,7 @@ ostm0: timer@12801000 {
 			interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
 			clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>;
 			resets = <&cpg R9A07G054_OSTM0_PRESETZ>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1223,7 +1223,7 @@ ostm1: timer@12801400 {
 			interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
 			clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>;
 			resets = <&cpg R9A07G054_OSTM1_PRESETZ>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -1234,7 +1234,7 @@ ostm2: timer@12801800 {
 			interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
 			clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>;
 			resets = <&cpg R9A07G054_OSTM2_PRESETZ>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 	};
-- 
2.39.2

Re: [PATCH 15/17] arm64: dts: renesas: r9a07g054: Update #power-domain-cells = <1>

[Geert Uytterhoeven]

On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Update CPG #power-domain-cells = <1> and move all the IPs to be part of the
> always on power domain as the driver has been modified to support multiple
> power domains.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

> --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
> @@ -238,7 +238,7 @@ mtu3: timer@10001200 {
>                                           "tgia8", "tgib8", "tgic8", "tgid8",
>                                           "tciv8", "tciu8";
>                         clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
> -                       power-domains = <&cpg>;
> +                       power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>;

This should be R9A07G054_PD_MTU, but that domain is not yet supported
by the driver.  Instead of adding incorrect hardware descriptions,
I'd rather defer this until all domains are handled by the driver.

>                         resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;
>                         #pwm-cells = <2>;
>                         status = "disabled";

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 16/17] arm64: dts: renesas: r9a08g045: Update #power-domain-cells = <1>

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Update CPG #power-domain-cells = <1> and move all the IPs to be part of the
IP specific power domain as the driver has been modified to support multiple
power domains.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index dfee878c0f49..11be621aaa82 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -62,7 +62,7 @@ scif0: serial@1004b800 {
 					  "bri", "dri", "tei";
 			clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
 			clock-names = "fck";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A08G045_PD_SCIF0>;
 			resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
 			status = "disabled";
 		};
@@ -74,7 +74,7 @@ cpg: clock-controller@11010000 {
 			clock-names = "extal";
 			#clock-cells = <2>;
 			#reset-cells = <1>;
-			#power-domain-cells = <0>;
+			#power-domain-cells = <1>;
 		};
 
 		sysc: system-controller@11020000 {
@@ -99,7 +99,7 @@ pinctrl: pinctrl@11030000 {
 			interrupt-parent = <&irqc>;
 			gpio-ranges = <&pinctrl 0 0 152>;
 			clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A08G045_PD_ALWAYS_ON>;
 			resets = <&cpg R9A08G045_GPIO_RSTN>,
 				 <&cpg R9A08G045_GPIO_PORT_RESETN>,
 				 <&cpg R9A08G045_GPIO_SPARE_RESETN>;
@@ -168,7 +168,7 @@ irqc: interrupt-controller@11050000 {
 			clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
 				 <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
 			clock-names = "clk", "pclk";
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A08G045_PD_ALWAYS_ON>;
 			resets = <&cpg R9A08G045_IA55_RESETN>;
 		};
 
@@ -183,7 +183,7 @@ sdhi0: mmc@11c00000  {
 				 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
 			resets = <&cpg R9A08G045_SDHI0_IXRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A08G045_PD_SDHI0>;
 			status = "disabled";
 		};
 
@@ -198,7 +198,7 @@ sdhi1: mmc@11c10000 {
 				 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
 			resets = <&cpg R9A08G045_SDHI1_IXRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A08G045_PD_SDHI1>;
 			status = "disabled";
 		};
 
@@ -213,7 +213,7 @@ sdhi2: mmc@11c20000 {
 				 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
 			resets = <&cpg R9A08G045_SDHI2_IXRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A08G045_PD_SDHI2>;
 			status = "disabled";
 		};
 
@@ -230,7 +230,7 @@ eth0: ethernet@11c30000 {
 				 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
 			clock-names = "axi", "chi", "refclk";
 			resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A08G045_PD_ETHER0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -249,7 +249,7 @@ eth1: ethernet@11c40000 {
 				 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
 			clock-names = "axi", "chi", "refclk";
 			resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A08G045_PD_ETHER1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -275,7 +275,7 @@ wdt0: watchdog@12800800 {
 				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "wdt", "perrout";
 			resets = <&cpg R9A08G045_WDT0_PRESETN>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A08G045_PD_WDT0>;
 			status = "disabled";
 		};
 	};
-- 
2.39.2

Re: [PATCH 16/17] arm64: dts: renesas: r9a08g045: Update #power-domain-cells = <1>

[Geert Uytterhoeven]

Hi Claudiu,

On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Update CPG #power-domain-cells = <1> and move all the IPs to be part of the
> IP specific power domain as the driver has been modified to support multiple
> power domains.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> @@ -168,7 +168,7 @@ irqc: interrupt-controller@11050000 {
>                         clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
>                                  <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
>                         clock-names = "clk", "pclk";
> -                       power-domains = <&cpg>;
> +                       power-domains = <&cpg R9A08G045_PD_ALWAYS_ON>;

R9A08G045_PD_IA55

>                         resets = <&cpg R9A08G045_IA55_RESETN>;
>                 };
>

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 17/17] arm64: dts: renesas: r9a09g011: Update #power-domain-cells = <1>

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Update CPG #power-domain-cells = <1> and move all the IPs to be part of the
always on power domain as the driver has been modified to support multiple
power domains.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 28 +++++++++++-----------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
index 50ed66d42a24..74af0f730b89 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
@@ -81,7 +81,7 @@ sdhi0: mmc@85000000 {
 				 <&cpg CPG_MOD R9A09G011_SDI0_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
 			resets = <&cpg R9A09G011_SDI0_IXRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -97,7 +97,7 @@ sdhi1: mmc@85010000  {
 				 <&cpg CPG_MOD R9A09G011_SDI1_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
 			resets = <&cpg R9A09G011_SDI1_IXRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -113,7 +113,7 @@ emmc: mmc@85020000  {
 				 <&cpg CPG_MOD R9A09G011_EMM_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
 			resets = <&cpg R9A09G011_EMM_IXRST>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -129,7 +129,7 @@ usb3drd: usb3drd@85070400 {
 				 <&cpg CPG_MOD R9A09G011_USB_PCLK>;
 			clock-names = "axi", "reg";
 			resets = <&cpg R9A09G011_USB_DRD_RESET>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>;
 			ranges;
 			#address-cells = <2>;
 			#size-cells = <2>;
@@ -144,7 +144,7 @@ usb3host: usb@85060000 {
 					 <&cpg CPG_MOD R9A09G011_USB_PCLK>;
 				clock-names = "axi", "reg";
 				resets = <&cpg R9A09G011_USB_ARESETN_H>;
-				power-domains = <&cpg>;
+				power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>;
 				status = "disabled";
 			};
 
@@ -157,7 +157,7 @@ usb3peri: usb3peri@85070000 {
 					 <&cpg CPG_MOD R9A09G011_USB_PCLK>;
 				clock-names = "axi", "reg";
 				resets = <&cpg R9A09G011_USB_ARESETN_P>;
-				power-domains = <&cpg>;
+				power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>;
 				status = "disabled";
 			};
 		};
@@ -207,7 +207,7 @@ avb: ethernet@a3300000 {
 				 <&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>;
 			clock-names = "axi", "chi", "gptp";
 			resets = <&cpg R9A09G011_ETH0_RST_HW_N>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -220,7 +220,7 @@ cpg: clock-controller@a3500000 {
 			clock-names = "extal";
 			#clock-cells = <2>;
 			#reset-cells = <1>;
-			#power-domain-cells = <0>;
+			#power-domain-cells = <1>;
 		};
 
 		pwc: pwc@a3700000 {
@@ -244,7 +244,7 @@ csi0: spi@a4020000 {
 				 <&cpg CPG_MOD R9A09G011_CPERI_GRPG_PCLK>;
 			clock-names = "csiclk", "pclk";
 			resets = <&cpg R9A09G011_CSI_GPG_PRESETN>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -258,7 +258,7 @@ csi4: spi@a4020200 {
 				 <&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>;
 			clock-names = "csiclk", "pclk";
 			resets = <&cpg R9A09G011_CSI_GPH_PRESETN>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -274,7 +274,7 @@ i2c0: i2c@a4030000 {
 			interrupt-names = "tia", "tis";
 			clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK0>;
 			resets = <&cpg R9A09G011_IIC_GPA_PRESETN>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -288,7 +288,7 @@ i2c2: i2c@a4030100 {
 			interrupt-names = "tia", "tis";
 			clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK1>;
 			resets = <&cpg R9A09G011_IIC_GPB_PRESETN>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -311,7 +311,7 @@ wdt0: watchdog@a4050000 {
 			clock-names = "pclk", "oscclk";
 			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 			resets = <&cpg R9A09G011_WDT0_PRESETN>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -361,7 +361,7 @@ pinctrl: pinctrl@b6250000 {
 				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>;
-			power-domains = <&cpg>;
+			power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>;
 			resets = <&cpg R9A09G011_PFC_PRESETN>;
 		};
 	};
-- 
2.39.2

Re: [PATCH 17/17] arm64: dts: renesas: r9a09g011: Update #power-domain-cells = <1>

[Geert Uytterhoeven]

Hi Claudiu,

On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Update CPG #power-domain-cells = <1> and move all the IPs to be part of the
> always on power domain as the driver has been modified to support multiple
> power domains.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Thanks for your patch!

As RZ/V2M uses the Internal Power Domain Controller (PMC), which
is not yet supported by the driver, I'd rather defer this until all
domains are handled by the driver.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds