[RFC PATCH v3 13/35] Documentation/devicetree/bindings/clock: Add renesas,sh7750-cpg binding document.

[RFC PATCH v3 13/35] Documentation/devicetree/bindings/clock: Add renesas,sh7750-cpg binding document.

[Yoshinori Sato]

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
 .../bindings/clock/renesas,sh7750-cpg.yaml    | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml

diff --git a/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
new file mode 100644
index 000000000000..a640968ed005
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7750/7751 Clock Pulse Generator (CPG)
+
+maintainers:
+  - Yoshinori Sato <ysato@users.sourceforge.jp>
+
+description:
+  The Clock Pulse Generator (CPG) generates core clocks for the SoC.  It
+  includes PLLs, and variable ratio dividers.
+
+  The CPG may also provide a Clock Domain for SoC devices, in combination with
+  the CPG Module Stop (MSTP) Clocks.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - renesas,sh7750-cpg             # SH7750
+          - renesas,sh7750s-cpg            # SH775S
+          - renesas,sh7750r-cpg            # SH7750R
+          - renesas,sh7751-cpg             # SH7751
+          - renesas,sh7751r-cpg            # SH7751R
+      - const: renesas,sh7750-cpg
+
+  reg:
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: FRQCR
+      - const: CLKSTP00
+
+  clocks: true
+
+  clock-names: true
+
+  '#clock-cells':
+    const: 1
+
+  renesas,mode:
+    description: Board-specific settings of the MD[0-2] pins on SoC
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 6
+
+  '#power-domain-cells':
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/sh7750.h>
+    cpg: clock-controller@ffc00000 {
+        #clock-cells = <1>;
+        #power-domain-cells = <0>;
+        compatible = "renesas,sh7751r-cpg";
+        clocks = <&xtal>;
+        clock-names = "xtal";
+        reg = <0xffc00000 20>, <0xfe0a0000 16>;
+    };
-- 
2.39.2

[RFC PATCH v3 15/35] Documentation/devicetree/bindings/interrupt-controller: Add renesas,sh7751-intc.yaml

[Yoshinori Sato]

SH7751 interrupt controller binding definition.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
 .../renesas,sh7751-intc.yaml                  | 102 ++++++++++++++++++
 1 file changed, 102 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
new file mode 100644
index 000000000000..02cc8e73eaf9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7751 Interrupt Controller
+
+maintainers:
+  - Yoshinori Sato <ysato@users.sourceforge.jp>
+
+properties:
+  compatible:
+    items:
+      - const: renesas,sh7751-intc
+
+  '#interrupt-cells':
+    # an interrupt index and flags, as defined in interrupts.txt in
+    # this directory
+    const: 2
+
+  interrupt-controller: true
+
+  reg:
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: ICR
+      - const: INTPRI00
+
+  renesas,icr-irlm:
+    type: boolean
+    description: Use ICR.IRLM=1
+
+  renesas,ipr-map:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: |
+      IRQ to IPR mapping definition.
+
+required:
+  - compatible
+  - '#interrupt-cells'
+  - interrupt-controller
+  - reg
+  - reg-names
+  - renesas,ipr-map
+
+additionalProperties: false
+
+examples:
+  - |
+        shintc: interrupt-controller@ffd00000 {
+                compatible = "renesas,sh7751-intc";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0xffd00000 14>, <0xfe080000 128>;
+                renesas,ipr-map = IPRDEF(0x240, IPRD, IPR_B12), /* IRL0 */
+                                  IPRDEF(0x2a0, IPRD, IPR_B8),  /* IRL1 */
+                                  IPRDEF(0x300, IPRD, IPR_B4),  /* IRL2 */
+                                  IPRDEF(0x360, IPRD, IPR_B0),  /* IRL3 */
+                                  IPRDEF(0x400, IPRA, IPR_B12), /* TMU0 */
+                                  IPRDEF(0x420, IPRA, IPR_B8),  /* TMU1 */
+                                  IPRDEF(0x440, IPRA, IPR_B4),  /* TMU2 TNUI */
+                                  IPRDEF(0x460, IPRA, IPR_B4),  /* TMU2 TICPI */
+                                  IPRDEF(0x480, IPRA, IPR_B0),  /* RTC ATI */
+                                  IPRDEF(0x4a0, IPRA, IPR_B0),  /* RTC PRI */
+                                  IPRDEF(0x4c0, IPRA, IPR_B0),  /* RTC CUI */
+                                  IPRDEF(0x4e0, IPRB, IPR_B4),  /* SCI ERI */
+                                  IPRDEF(0x500, IPRB, IPR_B4),  /* SCI RXI */
+                                  IPRDEF(0x520, IPRB, IPR_B4),  /* SCI TXI */
+                                  IPRDEF(0x540, IPRB, IPR_B4),  /* SCI TEI */
+                                  IPRDEF(0x560, IPRB, IPR_B12), /* WDT */
+                                  IPRDEF(0x580, IPRB, IPR_B8),  /* REF RCMI */
+                                  IPRDEF(0x5a0, IPRB, IPR_B4),  /* REF ROVI */
+                                  IPRDEF(0x600, IPRC, IPR_B0),  /* H-UDI */
+                                  IPRDEF(0x620, IPRC, IPR_B12), /* GPIO */
+                                  IPRDEF(0x640, IPRC, IPR_B8),  /* DMAC DMTE0 */
+                                  IPRDEF(0x660, IPRC, IPR_B8),  /* DMAC DMTE1 */
+                                  IPRDEF(0x680, IPRC, IPR_B8),  /* DMAC DMTE2 */
+                                  IPRDEF(0x6a0, IPRC, IPR_B8),  /* DMAC DMTE3 */
+                                  IPRDEF(0x6c0, IPRC, IPR_B8),  /* DMAC DMAE */
+                                  IPRDEF(0x700, IPRC, IPR_B4),  /* SCIF ERI */
+                                  IPRDEF(0x720, IPRC, IPR_B4),  /* SCIF RXI */
+                                  IPRDEF(0x740, IPRC, IPR_B4),  /* SCIF BRI */
+                                  IPRDEF(0x760, IPRC, IPR_B4),  /* SCIF TXI */
+                                  IPRDEF(0x780, IPRC, IPR_B8),  /* DMAC DMTE4 */
+                                  IPRDEF(0x7a0, IPRC, IPR_B8),  /* DMAC DMTE5 */
+                                  IPRDEF(0x7c0, IPRC, IPR_B8),  /* DMAC DMTE6 */
+                                  IPRDEF(0x7e0, IPRC, IPR_B8),  /* DMAC DMTE7 */
+                                  IPRDEF(0xa00, INTPRI00, IPR_B0),      /* PCIC PCISERR */
+                                  IPRDEF(0xa20, INTPRI00, IPR_B4),      /* PCIC CIDMA3 */
+                                  IPRDEF(0xa40, INTPRI00, IPR_B4),      /* PCIC CIDMA2 */
+                                  IPRDEF(0xa60, INTPRI00, IPR_B4),      /* PCIC PCIDMA1 */
+                                  IPRDEF(0xa80, INTPRI00, IPR_B4),      /* PCIC PCIDMA0 */
+                                  IPRDEF(0xaa0, INTPRI00, IPR_B4),      /* PCIC PCIPWON */
+                                  IPRDEF(0xac0, INTPRI00, IPR_B4),      /* PCIC PCIPWDWN */
+                                  IPRDEF(0xae0, INTPRI00, IPR_B4),      /* PCIC PCIERR */
+                                  IPRDEF(0xb00, INTPRI00, IPR_B8),      /* TMU3 */
+                                  IPRDEF(0xb80, INTPRI00, IPR_B12);     /* TMU4 */
+        };
+...
-- 
2.39.2

[RFC PATCH v3 17/35] Documentation/devicetree/bindings/interrupt-controller: Add renesas,sh7751-irl-ext.yaml

[Yoshinori Sato]

SH7751 external interrupt encoder binding definition.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
 .../renesas,sh7751-irl-ext.yaml               | 89 +++++++++++++++++++
 1 file changed, 89 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
new file mode 100644
index 000000000000..323229ccc4c3
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-irl-ext.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7751 IRL external encoder with enable regs.
+
+maintainers:
+  - Yoshinori Sato <ysato@users.sourceforge.jp>
+
+description: |
+  This is the generally used external interrupt encoder on SH7751 based boards.
+
+properties:
+  compatible:
+    items:
+      - const: renesas,sh7751-irl-ext
+
+  reg:
+    minItems: 1
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 1
+
+  '#address-cells':
+    const: 0
+
+  '#size-cells':
+    const: 0
+
+  renesas,width:
+    description: Enable register width
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  renesas,regtype:
+    description: Enable register type
+    $ref: /schemas/types.yaml#/definitions/string
+    oneOf:
+      - description:
+          1 is interrupt enable / 0 is interrupt disable.
+        const: enable
+      - description:
+          1 is interrupt mask / 0 is interrupt unmask.
+        const: mask
+
+  renesas,irqbit:
+    description: IRQ to enable register bit mapping
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+
+
+required:
+  - compatible
+  - reg
+  - interrupt-controller
+  - '#interrupt-cells'
+  - renesas,width
+  - renesas,regtype
+  - renesas,irqbit
+
+additionalProperties: false
+
+examples:
+  - |
+    r2dintc: sh7751irl_encoder@a4000000 {
+        compatible = "renesas,sh7751-irl-ext";
+        reg = <0xa4000000 0x02>;
+        interrupt-controller;
+        #address-cells = <0>;
+        #size-cells = <0>;
+        #interrupt-cells = <1>;
+        renesas,width = <16>;
+        renesas,regtype = "enable";
+        renesas,irqbit =  <11>,         /* PCI INTD */
+                          <9>,          /* CF IDE */
+                          <8>,          /* CF CD */
+                          <12>,         /* PCI INTC */
+                          <10>,         /* SM501 */
+                          <6>,          /* KEY */
+                          <5>,          /* RTC ALARM */
+                          <4>,          /* RTC T */
+                          <7>,          /* SDCARD */
+                          <14>,         /* PCI INTA */
+                          <13>,         /* PCI INTB */
+                          <0>,          /* EXT */
+                          <15>;         /* TP */
+    };
-- 
2.39.2

[RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.

[Yoshinori Sato]

Renesas SuperH binding definition.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
 .../devicetree/bindings/sh/cpus.yaml          | 45 +++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sh/cpus.yaml

diff --git a/Documentation/devicetree/bindings/sh/cpus.yaml b/Documentation/devicetree/bindings/sh/cpus.yaml
new file mode 100644
index 000000000000..273df4dfb74e
--- /dev/null
+++ b/Documentation/devicetree/bindings/sh/cpus.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sh/cpus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SuperH CPUs
+
+maintainers:
+  - Yoshinori Sato <ysato@users.sourceforge.jp>
+
+description: |+
+  The device tree allows to describe the layout of CPUs in a system through
+  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
+  defining properties for every cpu.
+
+  Bindings for CPU nodes follow the Devicetree Specification, available from:
+
+  https://www.devicetree.org/specifications/
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - renesas,sh4
+      - const: renesas,sh
+
+  clock-frequency:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      CPU core clock freqency.
+
+required:
+  - compatible
+
+additionalProperties: true
+
+examples:
+  - |
+        cpus {
+                cpu: cpu@0 {
+                      compatible = "renesas,sh4", "renesas,sh";
+                };
+        };
+...
-- 
2.39.2

[RFC PATCH v3 26/35] arch/sh/boot/dts: SH7751R SoC Internal peripheral definition dtsi.

[Yoshinori Sato]

Renesas SuperH SH7751R common definition.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
 arch/sh/boot/dts/sh7751r.dtsi | 148 ++++++++++++++++++++++++++++++++++
 1 file changed, 148 insertions(+)
 create mode 100644 arch/sh/boot/dts/sh7751r.dtsi

diff --git a/arch/sh/boot/dts/sh7751r.dtsi b/arch/sh/boot/dts/sh7751r.dtsi
new file mode 100644
index 000000000000..66f71372baad
--- /dev/null
+++ b/arch/sh/boot/dts/sh7751r.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the SH7751R SoC
+ */
+
+#include <dt-bindings/interrupt-controller/sh_intc.h>
+#include <dt-bindings/clock/sh7750.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+		      compatible = "renesas,sh4", "renesas,sh";
+		      device_type = "cpu";
+		      reg = <0>;
+		      clocks = <&cpg SH7750_CPG_ICK>;
+		      clock-names = "ick";
+		      icache-size = <16384>;
+		      icache-line-size = <32>;
+		      dcache-size = <32768>;
+		      dcache-line-size = <32>;
+		};
+	};
+
+	xtal: oscillator {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+		clock-output-names = "xtal";
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&shintc>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		cpg: clock-controller@ffc00000 {
+			#clock-cells = <1>;
+			#power-domain-cells = <0>;
+			compatible = "renesas,sh7751r-cpg", "renesas,sh7750-cpg";
+			clocks = <&xtal>;
+			clock-names = "xtal";
+			reg = <0xffc00000 20>, <0xfe0a0000 16>;
+			reg-names = "FRQCR", "CLKSTP00";
+		};
+
+		shintc: interrupt-controller@ffd00000 {
+			compatible = "renesas,sh7751-intc";
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			reg = <0xffd00000 20>, <0xfe080000 128>;
+			reg-names = "ICR", "INTPRI00";
+			renesas,ipr-map = IPRDEF(0x240, IPRD, IPR_B12),	/* IRL0 */
+					  IPRDEF(0x2a0, IPRD, IPR_B8),	/* IRL1 */
+					  IPRDEF(0x300, IPRD, IPR_B4),	/* IRL2 */
+					  IPRDEF(0x360, IPRD, IPR_B0),	/* IRL3 */
+					  IPRDEF(0x400, IPRA, IPR_B12),	/* TMU0 */
+					  IPRDEF(0x420, IPRA, IPR_B8),	/* TMU1 */
+					  IPRDEF(0x440, IPRA, IPR_B4),	/* TMU2 TNUI */
+					  IPRDEF(0x460, IPRA, IPR_B4),	/* TMU2 TICPI */
+					  IPRDEF(0x480, IPRA, IPR_B0),	/* RTC ATI */
+					  IPRDEF(0x4a0, IPRA, IPR_B0),	/* RTC PRI */
+					  IPRDEF(0x4c0, IPRA, IPR_B0),	/* RTC CUI */
+					  IPRDEF(0x4e0, IPRB, IPR_B4),	/* SCI ERI */
+					  IPRDEF(0x500, IPRB, IPR_B4),	/* SCI RXI */
+					  IPRDEF(0x520, IPRB, IPR_B4),	/* SCI TXI */
+					  IPRDEF(0x540, IPRB, IPR_B4),	/* SCI TEI */
+					  IPRDEF(0x560, IPRB, IPR_B12),	/* WDT */
+					  IPRDEF(0x580, IPRB, IPR_B8),	/* REF RCMI */
+					  IPRDEF(0x5a0, IPRB, IPR_B4),	/* REF ROVI */
+					  IPRDEF(0x600, IPRC, IPR_B0),	/* H-UDI */
+					  IPRDEF(0x620, IPRC, IPR_B12),	/* GPIO */
+					  IPRDEF(0x640, IPRC, IPR_B8),	/* DMAC DMTE0 */
+					  IPRDEF(0x660, IPRC, IPR_B8),	/* DMAC DMTE1 */
+					  IPRDEF(0x680, IPRC, IPR_B8),	/* DMAC DMTE2 */
+					  IPRDEF(0x6a0, IPRC, IPR_B8),	/* DMAC DMTE3 */
+					  IPRDEF(0x6c0, IPRC, IPR_B8),	/* DMAC DMAE */
+					  IPRDEF(0x700, IPRC, IPR_B4),	/* SCIF ERI */
+					  IPRDEF(0x720, IPRC, IPR_B4),	/* SCIF RXI */
+					  IPRDEF(0x740, IPRC, IPR_B4),	/* SCIF BRI */
+					  IPRDEF(0x760, IPRC, IPR_B4),	/* SCIF TXI */
+					  IPRDEF(0x780, IPRC, IPR_B8),	/* DMAC DMTE4 */
+					  IPRDEF(0x7a0, IPRC, IPR_B8),	/* DMAC DMTE5 */
+					  IPRDEF(0x7c0, IPRC, IPR_B8),	/* DMAC DMTE6 */
+					  IPRDEF(0x7e0, IPRC, IPR_B8),	/* DMAC DMTE7 */
+					  IPRDEF(0xa00, INTPRI00, IPR_B0),	/* PCIC PCISERR */
+					  IPRDEF(0xa20, INTPRI00, IPR_B4),	/* PCIC PCIDMA3 */
+					  IPRDEF(0xa40, INTPRI00, IPR_B4),	/* PCIC PCIDMA2 */
+					  IPRDEF(0xa60, INTPRI00, IPR_B4),	/* PCIC PCIDMA1 */
+					  IPRDEF(0xa80, INTPRI00, IPR_B4),	/* PCIC PCIDMA0 */
+					  IPRDEF(0xaa0, INTPRI00, IPR_B4),	/* PCIC PCIPWON */
+					  IPRDEF(0xac0, INTPRI00, IPR_B4),	/* PCIC PCIPWDWN */
+					  IPRDEF(0xae0, INTPRI00, IPR_B4),	/* PCIC PCIERR */
+					  IPRDEF(0xb00, INTPRI00, IPR_B8),	/* TMU3 */
+					  IPRDEF(0xb80, INTPRI00, IPR_B12);	/* TMU4 */
+		};
+
+		/* sci0 is rarely used, so it is not defined here. */
+		scif1: serial@ffe80000 {
+			compatible = "renesas,scif-sh7751", "renesas,scif";
+			reg = <0xffe80000 0x100>;
+			interrupts = <evt2irq(0x700) 0>,
+				     <evt2irq(0x720) 0>,
+				     <evt2irq(0x760) 0>,
+				     <evt2irq(0x740) 0>;
+			interrupt-names = "eri", "rxi", "txi", "bri";
+			clocks = <&cpg SH7750_CPG_SCIF_CLK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+		};
+
+		/* Normally ch0 and ch1 are used, so we will define ch0 to ch2 here. */
+		tmu0: timer@ffd80000 {
+			compatible = "renesas,tmu-sh", "renesas,tmu";
+			reg = <0xffd80000 12>;
+			interrupts = <evt2irq(0x400) 0>,
+				     <evt2irq(0x420) 0>,
+				     <evt2irq(0x440) 0>,
+				     <evt2irq(0x460) 0>;
+			interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
+			clocks = <&cpg SH7750_CPG_TMU012_CLK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			#renesas,channels = <3>;
+		};
+
+		pcic: pci@fe200000 {
+			compatible = "renesas,pci-sh7751";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			device_type = "pci";
+			bus-range = <0 0>;
+			ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>,
+				 <0x01000000 0 0x00000000 0xfe240000 0 0x00040000>;
+			reg = <0xfe200000 0x0400>,
+			      <0x0c000000 0x04000000>,
+			      <0xff800000 0x0030>;
+		};
+	};
+};
-- 
2.39.2

[RFC PATCH v3 27/35] Documentation/devicetree/bindings: vendor-prefix add IO DATA DEVICE Inc.

[Yoshinori Sato]

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 573578db9509..2179a9d61e6a 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -657,6 +657,8 @@ patternProperties:
     description: Inventec
   "^inversepath,.*":
     description: Inverse Path
+  "^iodata,.*":
+    description: IO DATA DEVICE Inc.
   "^iom,.*":
     description: Iomega Corporation
   "^irondevice,.*":
-- 
2.39.2

[RFC PATCH v3 28/35] Documentation/devicetree/bindings/ata: ata-generic.yaml add usl-5p and rts7751r2d.

[Yoshinori Sato]

usl-5p and rts7751r2d using ata-generic driver.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
 Documentation/devicetree/bindings/ata/ata-generic.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/ata/ata-generic.yaml b/Documentation/devicetree/bindings/ata/ata-generic.yaml
index 0697927f3d7e..1025b3b351d0 100644
--- a/Documentation/devicetree/bindings/ata/ata-generic.yaml
+++ b/Documentation/devicetree/bindings/ata/ata-generic.yaml
@@ -18,6 +18,8 @@ properties:
       - enum:
           - arm,vexpress-cf
           - fsl,mpc8349emitx-pata
+          - iodata,usl-5p-ata
+          - renesas,rts7751r2d-ata
       - const: ata-generic
 
   reg:
-- 
2.39.2

[RFC PATCH v3 29/35] Documentation/devicetree/bindings/soc/renesas/sh.yaml: Add SH7751 based target.

[Yoshinori Sato]

Renesas SuperH based target definition.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
 .../devicetree/bindings/soc/renesas/sh.yaml   | 32 +++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/renesas/sh.yaml

diff --git a/Documentation/devicetree/bindings/soc/renesas/sh.yaml b/Documentation/devicetree/bindings/soc/renesas/sh.yaml
new file mode 100644
index 000000000000..3fbff2532ad3
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/renesas/sh.yaml
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/renesas/sh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SuperH Platform
+
+maintainers:
+  - Yoshinori Sato <ysato@users.sourceforge.jp>
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: RTS7751R2D Plus
+        items:
+          - enum:
+              - renesas,rts7751r2d # Renesas SH4 2D graphics board
+          - const: renesas,sh7751r
+
+      - description: Julian board
+        items:
+          - enum:
+              - iodata,landisk  # LANDISK HDL-U
+              - iodata,usl-5p   # USL-5P
+          - const: renesas,sh7751r
+
+additionalProperties: true
+
+...
-- 
2.39.2

[RFC PATCH v3 30/35] arch/sh/boot/dts: RTS7751R2D Plus DeviceTree.

[Yoshinori Sato]

Renesas RTS7751R2D Plus devicetree.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
 arch/sh/boot/dts/rts7751r2dplus.dts | 157 ++++++++++++++++++++++++++++
 1 file changed, 157 insertions(+)
 create mode 100644 arch/sh/boot/dts/rts7751r2dplus.dts

diff --git a/arch/sh/boot/dts/rts7751r2dplus.dts b/arch/sh/boot/dts/rts7751r2dplus.dts
new file mode 100644
index 000000000000..7fc9692da257
--- /dev/null
+++ b/arch/sh/boot/dts/rts7751r2dplus.dts
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Renesas RTS7751R2D Plus
+ */
+
+/dts-v1/;
+
+#include "sh7751r.dtsi"
+
+/ {
+	model = "Renesas RTS7715R2D Plus";
+	compatible = "renesas,rts7751r2d", "renesas,sh7751r";
+
+	aliases {
+		serial0 = &scif1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@c000000 {
+		device_type = "memory";
+		reg = <0x0c000000 0x4000000>;
+	};
+
+	oscillator {
+		clock-frequency = <22222222>;
+	};
+
+	r2dintc: sh7751irl_encoder@a4000000 {
+		compatible = "renesas,sh7751-irl-ext";
+		reg = <0xa4000000 0x02>;
+		interrupt-controller;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <1>;
+		renesas,width = <16>;
+		renesas,regtype = "enable";
+		renesas,irqbit =  <11>,		/* PCI INTD */
+				  <9>,		/* CF IDE */
+				  <8>,		/* CF CD */
+				  <12>,		/* PCI INTC */
+				  <10>,		/* SM501 */
+				  <6>,		/* KEY */
+				  <5>,		/* RTC ALARM */
+				  <4>,		/* RTC T */
+				  <7>,		/* SDCARD */
+				  <14>,		/* PCI INTA */
+				  <13>,		/* PCI INTB */
+				  <0>,		/* EXT */
+				  <15>;		/* TP */
+	};
+
+	display@1,0 {
+		compatible = "smi,sm501";
+		reg = <0x10000000 0x03e00000
+		       0x13e00000 0x00200000>;
+		interrupt-parent = <&r2dintc>;
+		interrupts = <4>;
+		mode = "640x480-16@60";
+		little-endian;
+		smi,devices = "usb-host","uart0";
+		interrupt-name = "sm501";
+		route = "own";
+		swap-fb-endian;
+
+		crt {
+			flags = "use_init_mode",
+				"use_hwcursor",
+				"use_hwaccel",
+				"disable_at_exit";
+		};
+
+		panel {
+			bpp = <16>;
+			edid = [00 ff ff ff ff ff ff 00 00 00 00 00 00 00 00 00
+				00 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 f0 0a 80 fb 20 e0 25 10 32 60
+				02 00 00 00 00 00 00 06 00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 bd];
+			flags = "use_init_mode",
+				"use_hwcursor",
+				"use_hwaccel",
+				"disable_at_exit";
+		};
+	};
+
+	compact-flash@b4001000 {
+		compatible = "renesas,rts7751r2d-ata", "ata-generic";
+		reg = <0xb4001000 0x0e>, <0xb400080c 2>;
+		reg-shift = <1>;
+		interrupt-parent = <&r2dintc>;
+		interrupts = <1>;
+	};
+
+	flash@0 {
+		compatible = "cfi-flash";
+		reg = <0x00000000 0x02000000>;
+		device-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "U-Boot";
+			reg = <0x00000000 0x00040000>;
+		};
+
+		partition@1 {
+			label = "Environemt";
+			reg = <0x00040000 0x00040000>;
+		};
+
+		partition@2 {
+			label = "Kernel";
+			reg = <0x00080000 0x001c0000>;
+		};
+
+		partition@3 {
+			label = "Flash_FS";
+			reg = <0x00240000 0x00dc0000>;
+		};
+	};
+
+	soc {
+		clock-controller@ffc00000 {
+			renesas,mode = <5>;
+		};
+
+		pci@fe200000 {
+			compatible = "renesas,pci-sh7751";
+			interrupt-parent = <&r2dintc>;
+			renesas,bcr1 = <0x40080000>;
+			renesas,intm = <0x0000c3ff>;
+			renesas,aintm = <0x0000380f>;
+			renesas,config = <1 0xfb900047>, <4 0xab000001>;
+			renesas,mcrmask = <0x40000004>;
+
+			interrupt-map = <0x0000 0 0 1 &r2dintc 9>,
+					<0x0000 0 0 2 &r2dintc 10>,
+					<0x0000 0 0 3 &r2dintc 3>,
+					<0x0000 0 0 4 &r2dintc 0>,
+					<0x0800 0 0 1 &r2dintc 10>,
+					<0x0800 0 0 2 &r2dintc 3>,
+					<0x0800 0 0 3 &r2dintc 0>,
+					<0x0800 0 0 4 &r2dintc 9>,
+					<0x1000 0 0 1 &r2dintc 3>,
+					<0x1000 0 0 2 &r2dintc 0>,
+					<0x1000 0 0 3 &r2dintc 9>,
+					<0x1000 0 0 4 &r2dintc 10>;
+			interrupt-map-mask = <0x1800 0 0 7>;
+		};
+	};
+};
-- 
2.39.2

[RFC PATCH v3 31/35] arch/sh/boot/dts: LANDISK DeviceTree.

[Yoshinori Sato]

IO DATA Device LANDISK devicetree.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
 arch/sh/boot/dts/landisk.dts | 79 ++++++++++++++++++++++++++++++++++++
 1 file changed, 79 insertions(+)
 create mode 100644 arch/sh/boot/dts/landisk.dts

diff --git a/arch/sh/boot/dts/landisk.dts b/arch/sh/boot/dts/landisk.dts
new file mode 100644
index 000000000000..bcbaf5e4af13
--- /dev/null
+++ b/arch/sh/boot/dts/landisk.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the IO DATA DEVICE LANDISK
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/clock/sh7750.h>
+#include "sh7751r.dtsi"
+
+/ {
+	model = "IO DATA Device LANDISK";
+	compatible = "iodata,landisk", "renesas,sh7751r";
+
+	aliases {
+		serial0 = &scif1;
+	};
+
+	chosen {
+		stdout-path = "serial0:9600n8";
+	};
+
+	memory@c000000 {
+		device_type = "memory";
+		reg = <0x0c000000 0x4000000>;
+	};
+
+	julianintc: sh7751irl_encoder@b0000005 {
+		compatible = "renesas,sh7751-irl-ext";
+		reg = <0xb0000005 0x01>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		renesas,width = <8>;
+		renesas,regtype = "enable";
+		renesas,irqbit = <0xffffffff>,	/* Not use */
+				 <0xffffffff>,
+				 <0xffffffff>,
+				 <0xffffffff>,
+				 <0xffffffff>,
+				 <0>,		/* PCI INTA */
+				 <1>,		/* PCI INTB */
+				 <2>,		/* PCI INTC */
+				 <3>,		/* PCI INTD */
+				 <4>,		/* ATA */
+				 <5>,		/* CF */
+				 <6>,		/* Power Switch */
+				 <7>;		/* Button */
+	};
+
+	oscillator {
+		clock-frequency = <22222222>;
+	};
+
+	soc {
+		clock-controller@ffc00000 {
+			renesas,mode = <5>;
+		};
+
+		pci@fe200000 {
+			compatible = "renesas,pci-sh7751";
+			renesas,bcr1 = <0x00080000>;
+			renesas,config = <6 0xd0000000>;
+			renesas,mcrmask = <0x40000004>;
+			interrupt-map = <0x0000 0 0 1 &julianintc 5>,
+					<0x0000 0 0 2 &julianintc 6>,
+					<0x0000 0 0 3 &julianintc 7>,
+					<0x0000 0 0 4 &julianintc 8>,
+					<0x0800 0 0 1 &julianintc 6>,
+					<0x0800 0 0 2 &julianintc 7>,
+					<0x0800 0 0 3 &julianintc 8>,
+					<0x0800 0 0 4 &julianintc 5>,
+					<0x1000 0 0 1 &julianintc 7>,
+					<0x1000 0 0 2 &julianintc 8>,
+					<0x1000 0 0 3 &julianintc 5>,
+					<0x1000 0 0 4 &julianintc 6>;
+			interrupt-map-mask = <0x1800 0 0 7>;
+		};
+	};
+};
-- 
2.39.2

[RFC PATCH v3 32/35] arch/sh/boot/dts: USL-5P DeviceTree.

[Yoshinori Sato]

IO DATA Device USL-5P devicetree.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
 arch/sh/boot/dts/usl-5p.dts | 88 +++++++++++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)
 create mode 100644 arch/sh/boot/dts/usl-5p.dts

diff --git a/arch/sh/boot/dts/usl-5p.dts b/arch/sh/boot/dts/usl-5p.dts
new file mode 100644
index 000000000000..ce5320348140
--- /dev/null
+++ b/arch/sh/boot/dts/usl-5p.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the IO DATA DEVICE USL-5P
+ */
+
+/dts-v1/;
+
+#include "sh7751r.dtsi"
+
+/ {
+	model = "IO-DATA Device USL-5P";
+	compatible = "iodata,usl-5p", "renesas,sh7751r";
+
+	aliases {
+		serial0 = &scif1;
+	};
+
+	chosen {
+		stdout-path = "serial0:9600n8";
+	};
+
+	memory@c000000 {
+		device_type = "memory";
+		reg = <0x0c000000 0x4000000>;
+	};
+
+	julianintc: sh7751irl_encoder@b0000005 {
+		compatible = "renesas,sh7751-irl-ext";
+		reg = <0xb0000005 0x01>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		renesas,width = <8>;
+		renesas,regtype = "enable";
+		renesas,irqbit = <0xffffffff>,	/* Not use */
+				 <0xffffffff>,
+				 <0xffffffff>,
+				 <0xffffffff>,
+				 <0xffffffff>,
+				 <0>,		/* PCI INTA */
+				 <1>,		/* PCI INTB */
+				 <2>,		/* PCI INTC */
+				 <3>,		/* PCI INTD */
+				 <4>,		/* ATA */
+				 <5>,		/* CF */
+				 <6>,		/* Power Switch */
+				 <7>;		/* Button */
+	};
+
+	oscillator {
+		clock-frequency = <22222222>;
+	};
+
+	compact-flash@b4001000 {
+		compatible = "iodata,usl-5p-ata", "ata-generic";
+		reg = <0xb4000040 0x0e>, <0xb400002c 2>;
+		reg-shift = <1>;
+		interrupt-parent = <&julianintc>;
+		interrupts = <10>;
+	};
+
+	soc {
+		clock-controller@ffc00000 {
+			renesas,mode = <5>;
+		};
+
+		pci@fe200000 {
+			compatible = "renesas,pci-sh7751";
+			renesas,bcr1 = <0x00080000>;
+			renesas,config = <6 0xd0000000>;
+			renesas,mcrmask = <0x40000004>;
+			interrupt-map = <0x0000 0 0 1 &julianintc 5>,
+					<0x0000 0 0 2 &julianintc 6>,
+					<0x0000 0 0 3 &julianintc 7>,
+					<0x0000 0 0 4 &julianintc 8>,
+					<0x0800 0 0 1 &julianintc 6>,
+					<0x0800 0 0 2 &julianintc 7>,
+					<0x0800 0 0 3 &julianintc 8>,
+					<0x0800 0 0 4 &julianintc 5>,
+					<0x1000 0 0 1 &julianintc 7>,
+					<0x1000 0 0 2 &julianintc 8>,
+					<0x1000 0 0 3 &julianintc 5>,
+					<0x1000 0 0 4 &julianintc 6>;
+			interrupt-map-mask = <0x1800 0 0 7>;
+		};
+	};
+};
-- 
2.39.2

Re: [RFC PATCH v3 28/35] Documentation/devicetree/bindings/ata: ata-generic.yaml add usl-5p and rts7751r2d.

[Damien Le Moal]

The patch title should be something like:

dt-bindings: ata: ata-generic: add usl-5p and rts7751r2d

without a period at the end.

On 10/14/23 23:54, Yoshinori Sato wrote:
> usl-5p and rts7751r2d using ata-generic driver.

Please use a full sentence. There is no verb here.

> 
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
>  Documentation/devicetree/bindings/ata/ata-generic.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/ata/ata-generic.yaml b/Documentation/devicetree/bindings/ata/ata-generic.yaml
> index 0697927f3d7e..1025b3b351d0 100644
> --- a/Documentation/devicetree/bindings/ata/ata-generic.yaml
> +++ b/Documentation/devicetree/bindings/ata/ata-generic.yaml
> @@ -18,6 +18,8 @@ properties:
>        - enum:
>            - arm,vexpress-cf
>            - fsl,mpc8349emitx-pata
> +          - iodata,usl-5p-ata
> +          - renesas,rts7751r2d-ata
>        - const: ata-generic
>  
>    reg:

-- 
Damien Le Moal
Western Digital Research

Re: [RFC PATCH v3 13/35] Documentation/devicetree/bindings/clock: Add renesas,sh7750-cpg binding document.

[Geert Uytterhoeven]

Hi Sato-san,

On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

Thanks for your patch!

> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
> @@ -0,0 +1,74 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas SH7750/7751 Clock Pulse Generator (CPG)
> +
> +maintainers:
> +  - Yoshinori Sato <ysato@users.sourceforge.jp>
> +
> +description:
> +  The Clock Pulse Generator (CPG) generates core clocks for the SoC.  It
> +  includes PLLs, and variable ratio dividers.
> +
> +  The CPG may also provide a Clock Domain for SoC devices, in combination with
> +  the CPG Module Stop (MSTP) Clocks.
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - renesas,sh7750-cpg             # SH7750
> +          - renesas,sh7750s-cpg            # SH775S
> +          - renesas,sh7750r-cpg            # SH7750R
> +          - renesas,sh7751-cpg             # SH7751
> +          - renesas,sh7751r-cpg            # SH7751R
> +      - const: renesas,sh7750-cpg

As there are important differences between the CPG variants, I think
it makes sense to drop the "renesas,sh7750-cpg", fallback, like you
BTW already did in the example below.
Then you can drop the "items", and just keep "enum".

> +examples:
> +  - |
> +    #include <dt-bindings/clock/sh7750.h>
> +    cpg: clock-controller@ffc00000 {
> +        #clock-cells = <1>;
> +        #power-domain-cells = <0>;
> +        compatible = "renesas,sh7751r-cpg";
> +        clocks = <&xtal>;
> +        clock-names = "xtal";
> +        reg = <0xffc00000 20>, <0xfe0a0000 16>;

$ make dt_binding_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.example.dtb:
clock-controller@ffc00000: compatible: ['renesas,sh7751r-cpg'] is too
short
        from schema $id:
http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml#
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.example.dtb:
clock-controller@ffc00000: 'reg-names' is a required property
        from schema $id:
http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml#

> +    };
> --
> 2.39.2
>



--
Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.

[Geert Uytterhoeven]

Hi Sato-san,

On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Renesas SuperH binding definition.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

Thanks for your patch!

> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
> @@ -0,0 +1,45 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/sh/cpus.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas SuperH CPUs
> +
> +maintainers:
> +  - Yoshinori Sato <ysato@users.sourceforge.jp>
> +
> +description: |+
> +  The device tree allows to describe the layout of CPUs in a system through
> +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> +  defining properties for every cpu.
> +
> +  Bindings for CPU nodes follow the Devicetree Specification, available from:
> +
> +  https://www.devicetree.org/specifications/
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:

Missing

    - jcore,j2

> +          - renesas,sh4


> +      - const: renesas,sh

I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
"renesas,sh", though.
Is there a common base of instructions that are available on all SH cores?

Missing reg property.
Missing "device_type: true".

> +
> +  clock-frequency:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description: |
> +      CPU core clock freqency.

Perhaps a "clocks" property instead, or as an alternative?

On sh7750, you do have

    clocks = <&cpg SH7750_CPG_ICK>;

> +
> +required:
> +  - compatible
> +
> +additionalProperties: true
> +
> +examples:
> +  - |
> +        cpus {

make dt_binding_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/sh/cpus.yaml:

Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
'#address-cells' is a required property
        from schema $id: http://devicetree.org/schemas/cpus.yaml#
        Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
'#size-cells' is a required property
from schema $id: http://devicetree.org/schemas/cpus.yaml#

> +                cpu: cpu@0 {
> +                      compatible = "renesas,sh4", "renesas,sh";

Documentation/devicetree/bindings/sh/cpus.example.dts:19.28-21.19:
Warning (unit_address_vs_reg): /example-0/cpus/cpu@0: node has a unit
name, but no reg or ranges property
Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus: cpu@0:
'cache-level' is a required property
        from schema $id: http://devicetree.org/schemas/cpus.yaml#

> +                };
> +        };
> +...

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [RFC PATCH v3 27/35] Documentation/devicetree/bindings: vendor-prefix add IO DATA DEVICE Inc.

[Geert Uytterhoeven]

Hi Sato-san,

On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

Thanks for your patch!

Please use a one-line prefix that matches the history of the file:

    dt-bindings: vendor-prefixes: Add IO DATA DEVICE Inc.

> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -657,6 +657,8 @@ patternProperties:
>      description: Inventec
>    "^inversepath,.*":
>      description: Inverse Path
> +  "^iodata,.*":
> +    description: IO DATA DEVICE Inc.
>    "^iom,.*":
>      description: Iomega Corporation
>    "^irondevice,.*":

For the actual change:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [RFC PATCH v3 29/35] Documentation/devicetree/bindings/soc/renesas/sh.yaml: Add SH7751 based target.

[Geert Uytterhoeven]

Hi Sato-san,

On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Renesas SuperH based target definition.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

Thanks for your patch!

Please use a one-line prefix that matches the history of the other
files next to it:

    dt-bindings: soc: renesas: Document SH7751 based targets

> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/renesas/sh.yaml
> @@ -0,0 +1,32 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/renesas/sh.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas SuperH Platform
> +
> +maintainers:
> +  - Yoshinori Sato <ysato@users.sourceforge.jp>
> +
> +properties:
> +  $nodename:
> +    const: '/'
> +  compatible:
> +    oneOf:
> +      - description: RTS7751R2D Plus
> +        items:
> +          - enum:
> +              - renesas,rts7751r2d # Renesas SH4 2D graphics board
> +          - const: renesas,sh7751r
> +
> +      - description: Julian board
> +        items:
> +          - enum:
> +              - iodata,landisk  # LANDISK HDL-U
> +              - iodata,usl-5p   # USL-5P

These depend on "[RFC PATCH v3 27/35] Documentation/devicetree/bindings:
vendor-prefix add IO DATA DEVICE Inc.", so that patch should be moved
forward in the series.

> +          - const: renesas,sh7751r

Please merge both sections, as they use the same number of compatible
values and the same fallback.

> +
> +additionalProperties: true
> +
> +...
> --
> 2.39.2
>


--
Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [RFC PATCH v3 29/35] Documentation/devicetree/bindings/soc/renesas/sh.yaml: Add SH7751 based target.

[Geert Uytterhoeven]

Hi Sato-san,

On Wed, Oct 18, 2023 at 8:48 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> <ysato@users.sourceforge.jp> wrote:
> > +              - iodata,landisk  # LANDISK HDL-U
> > +              - iodata,usl-5p   # USL-5P
>
> These depend on "[RFC PATCH v3 27/35] Documentation/devicetree/bindings:
> vendor-prefix add IO DATA DEVICE Inc.", so that patch should be moved

My apologies. Somehow the patches didn't end up in the right order
in my mailbox, so please ignore this comment.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [RFC PATCH v3 29/35] Documentation/devicetree/bindings/soc/renesas/sh.yaml: Add SH7751 based target.

[Geert Uytterhoeven]

Hi Sato-san,

On Wed, Oct 18, 2023 at 8:48 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> <ysato@users.sourceforge.jp> wrote:
> > Renesas SuperH based target definition.
> >
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/renesas/sh.yaml
> > @@ -0,0 +1,32 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/soc/renesas/sh.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas SuperH Platform
> > +
> > +maintainers:
> > +  - Yoshinori Sato <ysato@users.sourceforge.jp>
> > +
> > +properties:
> > +  $nodename:
> > +    const: '/'
> > +  compatible:
> > +    oneOf:
> > +      - description: RTS7751R2D Plus
> > +        items:
> > +          - enum:
> > +              - renesas,rts7751r2d # Renesas SH4 2D graphics board
> > +          - const: renesas,sh7751r
> > +
> > +      - description: Julian board
> > +        items:
> > +          - enum:
> > +              - iodata,landisk  # LANDISK HDL-U
> > +              - iodata,usl-5p   # USL-5P
> > +          - const: renesas,sh7751r
>
> Please merge both sections, as they use the same number of compatible
> values and the same fallback.

Unless we want to add an "renesas,sh7380" intermediate, as that is
the actual SoC in the landisk? I do not know what is the difference
between SH7380 and SH7751R.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [RFC PATCH v3 15/35] Documentation/devicetree/bindings/interrupt-controller: Add renesas,sh7751-intc.yaml

[Geert Uytterhoeven]

Hi Sato-san,

On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> SH7751 interrupt controller binding definition.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

Thanks for your patch!

> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
> @@ -0,0 +1,102 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-intc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas SH7751 Interrupt Controller
> +
> +maintainers:
> +  - Yoshinori Sato <ysato@users.sourceforge.jp>
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: renesas,sh7751-intc
> +
> +  '#interrupt-cells':
> +    # an interrupt index and flags, as defined in interrupts.txt in
> +    # this directory

I think you can drop this comment.

> +    const: 2

> +examples:
> +  - |

Missing

    #include <dt-bindings/interrupt-controller/sh_intc.h>

Please run

    make dt_binding_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml

to catch such issues before posting.

> +        shintc: interrupt-controller@ffd00000 {

Please align this to the "|" above, and use 4 spaces for each additional
indentation step.

> +                compatible = "renesas,sh7751-intc";

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [RFC PATCH v3 15/35] Documentation/devicetree/bindings/interrupt-controller: Add renesas,sh7751-intc.yaml

[Geert Uytterhoeven]

Hi Sato-san,

On Thu, Oct 19, 2023 at 1:29 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> <ysato@users.sourceforge.jp> wrote:
> > SH7751 interrupt controller binding definition.
> >
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
>
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
> > @@ -0,0 +1,102 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-intc.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas SH7751 Interrupt Controller
> > +
> > +maintainers:
> > +  - Yoshinori Sato <ysato@users.sourceforge.jp>
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - const: renesas,sh7751-intc
> > +
> > +  '#interrupt-cells':
> > +    # an interrupt index and flags, as defined in interrupts.txt in
> > +    # this directory
>
> I think you can drop this comment.
>
> > +    const: 2

And given the second cell is always zero, and the driver uses
irq_domain_xlate_onecell, I guess this should be one instead?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [RFC PATCH v3 30/35] arch/sh/boot/dts: RTS7751R2D Plus DeviceTree.

[Geert Uytterhoeven]

Hi Sato-san,

On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Renesas RTS7751R2D Plus devicetree.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/sh/boot/dts/rts7751r2dplus.dts

> +       oscillator {
> +               clock-frequency = <22222222>;
> +       };

When adding or overriding properties to/in existing device nodes,
please refer to the nodes using symbolic labels.  I.e. please add

    &xtal {
                clock-frequency = <22222222>;
     };

at the bottom of this file instead.

> +       display@1,0 {
> +               compatible = "smi,sm501";
> +               reg = <0x10000000 0x03e00000
> +                      0x13e00000 0x00200000>;
> +               interrupt-parent = <&r2dintc>;
> +               interrupts = <4>;
> +               mode = "640x480-16@60";
> +               little-endian;
> +               smi,devices = "usb-host","uart0";
> +               interrupt-name = "sm501";
> +               route = "own";
> +               swap-fb-endian;
> +
> +               crt {
> +                       flags = "use_init_mode",
> +                               "use_hwcursor",
> +                               "use_hwaccel",
> +                               "disable_at_exit";

"make dtbs_check" does not like flags being non-integer.
Might be an artefact of having only plain text bindings in
Documentation/devicetree/bindings/display/sm501fb.txt

> +               };
> +
> +               panel {
> +                       bpp = <16>;
> +                       edid = [00 ff ff ff ff ff ff 00 00 00 00 00 00 00 00 00
> +                               00 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 f0 0a 80 fb 20 e0 25 10 32 60
> +                               02 00 00 00 00 00 00 06 00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 bd];
> +                       flags = "use_init_mode",
> +                               "use_hwcursor",
> +                               "use_hwaccel",
> +                               "disable_at_exit";

Likewise.

> +               };
> +       };
> +
> +       compact-flash@b4001000 {
> +               compatible = "renesas,rts7751r2d-ata", "ata-generic";
> +               reg = <0xb4001000 0x0e>, <0xb400080c 2>;
> +               reg-shift = <1>;
> +               interrupt-parent = <&r2dintc>;
> +               interrupts = <1>;
> +       };
> +
> +       flash@0 {
> +               compatible = "cfi-flash";
> +               reg = <0x00000000 0x02000000>;
> +               device-width = <2>;
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +
> +               partition@0 {
> +                       label = "U-Boot";
> +                       reg = <0x00000000 0x00040000>;
> +               };
> +
> +               partition@1 {
> +                       label = "Environemt";

Environment

> +                       reg = <0x00040000 0x00040000>;
> +               };
> +
> +               partition@2 {
> +                       label = "Kernel";
> +                       reg = <0x00080000 0x001c0000>;
> +               };
> +
> +               partition@3 {
> +                       label = "Flash_FS";
> +                       reg = <0x00240000 0x00dc0000>;
> +               };
> +       };
> +
> +       soc {
> +               clock-controller@ffc00000 {
> +                       renesas,mode = <5>;
> +               };

    &cpg {
                renesas,mode = <5>;
    };

At the bottom of this file.

> +
> +               pci@fe200000 {

Likewise, "&pcic { ... };" at the bottom of this file.

> +                       compatible = "renesas,pci-sh7751";

No need to override the compatible property, it is already set in
sh7751.dtsi.

> +                       interrupt-parent = <&r2dintc>;
> +                       renesas,bcr1 = <0x40080000>;
> +                       renesas,intm = <0x0000c3ff>;
> +                       renesas,aintm = <0x0000380f>;
> +                       renesas,config = <1 0xfb900047>, <4 0xab000001>;
> +                       renesas,mcrmask = <0x40000004>;
> +
> +                       interrupt-map = <0x0000 0 0 1 &r2dintc 9>,
> +                                       <0x0000 0 0 2 &r2dintc 10>,
> +                                       <0x0000 0 0 3 &r2dintc 3>,
> +                                       <0x0000 0 0 4 &r2dintc 0>,
> +                                       <0x0800 0 0 1 &r2dintc 10>,
> +                                       <0x0800 0 0 2 &r2dintc 3>,
> +                                       <0x0800 0 0 3 &r2dintc 0>,
> +                                       <0x0800 0 0 4 &r2dintc 9>,
> +                                       <0x1000 0 0 1 &r2dintc 3>,
> +                                       <0x1000 0 0 2 &r2dintc 0>,
> +                                       <0x1000 0 0 3 &r2dintc 9>,
> +                                       <0x1000 0 0 4 &r2dintc 10>;
> +                       interrupt-map-mask = <0x1800 0 0 7>;
> +               };
> +       };
> +};

Some of my comments apply to landisk.dts and usl-5p.dts, too.
And please run "make dtbs_check" ;-)

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [RFC PATCH v3 31/35] arch/sh/boot/dts: LANDISK DeviceTree.

[Geert Uytterhoeven]

Hi Sato-san,

On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> IO DATA Device LANDISK devicetree.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/sh/boot/dts/landisk.dts
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the IO DATA DEVICE LANDISK
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/clock/sh7750.h>

This include can be dropped, as it is already included by sh7751r.dtsi.

> +#include "sh7751r.dtsi"

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [RFC PATCH v3 26/35] arch/sh/boot/dts: SH7751R SoC Internal peripheral definition dtsi.

[Geert Uytterhoeven]

Hi Sato-san,

On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Renesas SuperH SH7751R common definition.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/sh/boot/dts/sh7751r.dtsi
> @@ -0,0 +1,148 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the SH7751R SoC
> + */
> +
> +#include <dt-bindings/interrupt-controller/sh_intc.h>
> +#include <dt-bindings/clock/sh7750.h>
> +
> +/ {
> +       #address-cells = <1>;
> +       #size-cells = <1>;
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               cpu@0 {
> +                     compatible = "renesas,sh4", "renesas,sh";
> +                     device_type = "cpu";
> +                     reg = <0>;
> +                     clocks = <&cpg SH7750_CPG_ICK>;
> +                     clock-names = "ick";
> +                     icache-size = <16384>;
> +                     icache-line-size = <32>;
> +                     dcache-size = <32768>;
> +                     dcache-line-size = <32>;

Wrong indentation (2 TABs and 6 spaces instead of 3 TABs).

> +               };
> +       };
> +
> +       xtal: oscillator {
> +               #clock-cells = <0>;
> +               compatible = "fixed-clock";
> +               clock-frequency = <0>;
> +               clock-output-names = "xtal";
> +       };
> +
> +       soc {

> +               scif1: serial@ffe80000 {
> +                       compatible = "renesas,scif-sh7751", "renesas,scif";
> +                       reg = <0xffe80000 0x100>;
> +                       interrupts = <evt2irq(0x700) 0>,
> +                                    <evt2irq(0x720) 0>,
> +                                    <evt2irq(0x760) 0>,
> +                                    <evt2irq(0x740) 0>;
> +                       interrupt-names = "eri", "rxi", "txi", "bri";
> +                       clocks = <&cpg SH7750_CPG_SCIF_CLK>;
> +                       clock-names = "fck";
> +                       power-domains = <&cpg>;

status = "disabled";

and add

    &scif1 {
            status = "okay";
    };

to each board .dts file that uses scif1.

> +               };

> +               pcic: pci@fe200000 {
> +                       compatible = "renesas,pci-sh7751";
> +                       #address-cells = <3>;
> +                       #size-cells = <2>;
> +                       #interrupt-cells = <1>;
> +                       device_type = "pci";
> +                       bus-range = <0 0>;
> +                       ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>,
> +                                <0x01000000 0 0x00000000 0xfe240000 0 0x00040000>;
> +                       reg = <0xfe200000 0x0400>,
> +                             <0x0c000000 0x04000000>,
> +                             <0xff800000 0x0030>;

status = "disabled";

and add

    &pcic {
            status = "okay";
    };

to each board .dts file that uses pcic.

> +               };
> +       };
> +};

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.

[Yoshinori Sato]

On Wed, 18 Oct 2023 23:27:43 +0900,
Geert Uytterhoeven wrote:
> 
> Hi Sato-san,
> 
> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> <ysato@users.sourceforge.jp> wrote:
> > Renesas SuperH binding definition.
> >
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
> > @@ -0,0 +1,45 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/sh/cpus.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas SuperH CPUs
> > +
> > +maintainers:
> > +  - Yoshinori Sato <ysato@users.sourceforge.jp>
> > +
> > +description: |+
> > +  The device tree allows to describe the layout of CPUs in a system through
> > +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> > +  defining properties for every cpu.
> > +
> > +  Bindings for CPU nodes follow the Devicetree Specification, available from:
> > +
> > +  https://www.devicetree.org/specifications/
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> 
> Missing
> 
>     - jcore,j2
> 
> > +          - renesas,sh4
> 
> 
> > +      - const: renesas,sh
> 
> I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
> "renesas,sh", though.
> Is there a common base of instructions that are available on all SH cores?

The base instruction set is sh2.
Before that, there is sh1, but this is not compatible with Linux.
I think it would be a good idea to change this to "renesas,sh2",
but the SH7619 (SH2 CPU) would look like the following.
cpus {
	cpu: cpu@0 {
        	compatible = "renesas,sh2", "renesas,sh2";
        };
};

> Missing reg property.
> Missing "device_type: true".
> 
> > +
> > +  clock-frequency:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    description: |
> > +      CPU core clock freqency.
> 
> Perhaps a "clocks" property instead, or as an alternative?
> 
> On sh7750, you do have
> 
>     clocks = <&cpg SH7750_CPG_ICK>;
> 
> > +
> > +required:
> > +  - compatible
> > +
> > +additionalProperties: true
> > +
> > +examples:
> > +  - |
> > +        cpus {
> 
> make dt_binding_check
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/sh/cpus.yaml:
> 
> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
> '#address-cells' is a required property
>         from schema $id: http://devicetree.org/schemas/cpus.yaml#
>         Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
> '#size-cells' is a required property
> from schema $id: http://devicetree.org/schemas/cpus.yaml#
> 
> > +                cpu: cpu@0 {
> > +                      compatible = "renesas,sh4", "renesas,sh";
> 
> Documentation/devicetree/bindings/sh/cpus.example.dts:19.28-21.19:
> Warning (unit_address_vs_reg): /example-0/cpus/cpu@0: node has a unit
> name, but no reg or ranges property
> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus: cpu@0:
> 'cache-level' is a required property
>         from schema $id: http://devicetree.org/schemas/cpus.yaml#
> 
> > +                };
> > +        };
> > +...
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> -- 
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

-- 
Yosinori Sato

Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.

[D. Jeff Dionne]

Hi Sato-san,

We must not imply that Renesas is responsible for J2, or that it is a sanctioned SH core.

J-Core has the responsibility for maintenance of those SH ISA compatible cores.

J.

> On Oct 25, 2023, at 20:14, Yoshinori Sato <ysato@users.sourceforge.jp> wrote:
> 
> On Wed, 18 Oct 2023 23:27:43 +0900,
> Geert Uytterhoeven wrote:
>> 
>> Hi Sato-san,
>> 
>> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
>> <ysato@users.sourceforge.jp> wrote:
>>> Renesas SuperH binding definition.
>>> 
>>> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
>> 
>> Thanks for your patch!
>> 
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
>>> @@ -0,0 +1,45 @@
>>> +# SPDX-License-Identifier: GPL-2.0
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/sh/cpus.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Renesas SuperH CPUs
>>> +
>>> +maintainers:
>>> +  - Yoshinori Sato <ysato@users.sourceforge.jp>
>>> +
>>> +description: |+
>>> +  The device tree allows to describe the layout of CPUs in a system through
>>> +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
>>> +  defining properties for every cpu.
>>> +
>>> +  Bindings for CPU nodes follow the Devicetree Specification, available from:
>>> +
>>> +  https://www.devicetree.org/specifications/
>>> +
>>> +properties:
>>> +  compatible:
>>> +    items:
>>> +      - enum:
>> 
>> Missing
>> 
>>    - jcore,j2
>> 
>>> +          - renesas,sh4
>> 
>> 
>>> +      - const: renesas,sh
>> 
>> I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
>> "renesas,sh", though.
>> Is there a common base of instructions that are available on all SH cores?
> 
> The base instruction set is sh2.
> Before that, there is sh1, but this is not compatible with Linux.
> I think it would be a good idea to change this to "renesas,sh2",
> but the SH7619 (SH2 CPU) would look like the following.
> cpus {
> 	cpu: cpu@0 {
>        	compatible = "renesas,sh2", "renesas,sh2";
>        };
> };
> 
>> Missing reg property.
>> Missing "device_type: true".
>> 
>>> +
>>> +  clock-frequency:
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>> +    description: |
>>> +      CPU core clock freqency.
>> 
>> Perhaps a "clocks" property instead, or as an alternative?
>> 
>> On sh7750, you do have
>> 
>>    clocks = <&cpg SH7750_CPG_ICK>;
>> 
>>> +
>>> +required:
>>> +  - compatible
>>> +
>>> +additionalProperties: true
>>> +
>>> +examples:
>>> +  - |
>>> +        cpus {
>> 
>> make dt_binding_check
>> DT_SCHEMA_FILES=Documentation/devicetree/bindings/sh/cpus.yaml:
>> 
>> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
>> '#address-cells' is a required property
>>        from schema $id: http://devicetree.org/schemas/cpus.yaml#
>>        Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
>> '#size-cells' is a required property
>> from schema $id: http://devicetree.org/schemas/cpus.yaml#
>> 
>>> +                cpu: cpu@0 {
>>> +                      compatible = "renesas,sh4", "renesas,sh";
>> 
>> Documentation/devicetree/bindings/sh/cpus.example.dts:19.28-21.19:
>> Warning (unit_address_vs_reg): /example-0/cpus/cpu@0: node has a unit
>> name, but no reg or ranges property
>> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus: cpu@0:
>> 'cache-level' is a required property
>>        from schema $id: http://devicetree.org/schemas/cpus.yaml#
>> 
>>> +                };
>>> +        };
>>> +...
>> 
>> Gr{oetje,eeting}s,
>> 
>>                        Geert
>> 
>> -- 
>> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>> 
>> In personal conversations with technical people, I call myself a hacker. But
>> when I'm talking to journalists I just say "programmer" or something like that.
>>                                -- Linus Torvalds
> 
> -- 
> Yosinori Sato

Re: [RFC PATCH v3 29/35] Documentation/devicetree/bindings/soc/renesas/sh.yaml: Add SH7751 based target.

[Yoshinori Sato]

On Thu, 19 Oct 2023 04:44:12 +0900,
Geert Uytterhoeven wrote:
> 
> Hi Sato-san,
> 
> On Wed, Oct 18, 2023 at 8:48 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> > <ysato@users.sourceforge.jp> wrote:
> > > Renesas SuperH based target definition.
> > >
> > > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> 
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/soc/renesas/sh.yaml
> > > @@ -0,0 +1,32 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/soc/renesas/sh.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Renesas SuperH Platform
> > > +
> > > +maintainers:
> > > +  - Yoshinori Sato <ysato@users.sourceforge.jp>
> > > +
> > > +properties:
> > > +  $nodename:
> > > +    const: '/'
> > > +  compatible:
> > > +    oneOf:
> > > +      - description: RTS7751R2D Plus
> > > +        items:
> > > +          - enum:
> > > +              - renesas,rts7751r2d # Renesas SH4 2D graphics board
> > > +          - const: renesas,sh7751r
> > > +
> > > +      - description: Julian board
> > > +        items:
> > > +          - enum:
> > > +              - iodata,landisk  # LANDISK HDL-U
> > > +              - iodata,usl-5p   # USL-5P
> > > +          - const: renesas,sh7751r
> >
> > Please merge both sections, as they use the same number of compatible
> > values and the same fallback.
> 
> Unless we want to add an "renesas,sh7380" intermediate, as that is
> the actual SoC in the landisk? I do not know what is the difference
> between SH7380 and SH7751R.

Everything here is SH7751R.
I didn't include J2, so I'll add it.
Other SoCs will be added after changing to DeviceTree.

> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> -- 
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

-- 
Yosinori Sato

Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.

[Geert Uytterhoeven]

Hi Sato-san,

On Wed, Oct 25, 2023 at 1:14 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> On Wed, 18 Oct 2023 23:27:43 +0900,
> Geert Uytterhoeven wrote:
> > On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> > <ysato@users.sourceforge.jp> wrote:
> > > Renesas SuperH binding definition.
> > >
> > > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/sh/cpus.yaml

> > > +properties:
> > > +  compatible:
> > > +    items:
> > > +      - enum:
> >
> > Missing
> >
> >     - jcore,j2
> >
> > > +          - renesas,sh4
> >
> >
> > > +      - const: renesas,sh
> >
> > I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
> > "renesas,sh", though.
> > Is there a common base of instructions that are available on all SH cores?
>
> The base instruction set is sh2.
> Before that, there is sh1, but this is not compatible with Linux.
> I think it would be a good idea to change this to "renesas,sh2",
> but the SH7619 (SH2 CPU) would look like the following.
> cpus {
>         cpu: cpu@0 {
>                 compatible = "renesas,sh2", "renesas,sh2";
>         };
> };

SH7619 would just use a single compatible value:

    compatible = "renesas,sh2".

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.

[Geert Uytterhoeven]

Hi Jeff,

On Wed, Oct 25, 2023 at 1:33 PM D. Jeff Dionne <djeffdionne@gmail.com> wrote:
> > On Oct 25, 2023, at 20:14, Yoshinori Sato <ysato@users.sourceforge.jp> wrote:
> > On Wed, 18 Oct 2023 23:27:43 +0900,
> > Geert Uytterhoeven wrote:
> >> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> >> <ysato@users.sourceforge.jp> wrote:
> >>> Renesas SuperH binding definition.
> >>>
> >>> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
> >>> @@ -0,0 +1,45 @@
> >>> +# SPDX-License-Identifier: GPL-2.0
> >>> +%YAML 1.2
> >>> +---
> >>> +$id: http://devicetree.org/schemas/sh/cpus.yaml#
> >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>> +
> >>> +title: Renesas SuperH CPUs
> >>> +
> >>> +maintainers:
> >>> +  - Yoshinori Sato <ysato@users.sourceforge.jp>
> >>> +
> >>> +description: |+
> >>> +  The device tree allows to describe the layout of CPUs in a system through
> >>> +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> >>> +  defining properties for every cpu.
> >>> +
> >>> +  Bindings for CPU nodes follow the Devicetree Specification, available from:
> >>> +
> >>> +  https://www.devicetree.org/specifications/
> >>> +
> >>> +properties:
> >>> +  compatible:
> >>> +    items:
> >>> +      - enum:
> >>
> >> Missing
> >>
> >>    - jcore,j2

> We must not imply that Renesas is responsible for J2, or that it is a sanctioned SH core.

Compatible values do not declare any such endorsement.

> J-Core has the responsibility for maintenance of those SH ISA compatible cores.

The question is: does J2 implement the same instruction set as SH2,
i.e. can it run unmodified SH2 code?

> >>
> >>> +          - renesas,sh4
> >>
> >>
> >>> +      - const: renesas,sh
> >>
> >> I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
> >> "renesas,sh", though.
> >> Is there a common base of instructions that are available on all SH cores?
> >
> > The base instruction set is sh2.
> > Before that, there is sh1, but this is not compatible with Linux.
> > I think it would be a good idea to change this to "renesas,sh2",

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [RFC PATCH v3 29/35] Documentation/devicetree/bindings/soc/renesas/sh.yaml: Add SH7751 based target.

[Yoshinori Sato]

On Thu, 19 Oct 2023 04:44:12 +0900,
Geert Uytterhoeven wrote:
> 
> Hi Sato-san,
> 
> On Wed, Oct 18, 2023 at 8:48 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> > <ysato@users.sourceforge.jp> wrote:
> > > Renesas SuperH based target definition.
> > >
> > > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> 
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/soc/renesas/sh.yaml
> > > @@ -0,0 +1,32 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/soc/renesas/sh.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Renesas SuperH Platform
> > > +
> > > +maintainers:
> > > +  - Yoshinori Sato <ysato@users.sourceforge.jp>
> > > +
> > > +properties:
> > > +  $nodename:
> > > +    const: '/'
> > > +  compatible:
> > > +    oneOf:
> > > +      - description: RTS7751R2D Plus
> > > +        items:
> > > +          - enum:
> > > +              - renesas,rts7751r2d # Renesas SH4 2D graphics board
> > > +          - const: renesas,sh7751r
> > > +
> > > +      - description: Julian board
> > > +        items:
> > > +          - enum:
> > > +              - iodata,landisk  # LANDISK HDL-U
> > > +              - iodata,usl-5p   # USL-5P
> > > +          - const: renesas,sh7751r
> >
> > Please merge both sections, as they use the same number of compatible
> > values and the same fallback.
> 
> Unless we want to add an "renesas,sh7380" intermediate, as that is
> the actual SoC in the landisk? I do not know what is the difference
> between SH7380 and SH7751R.

Details of the SH7380 have not been released,
but the hardware appears to be the same as the SH7751R.
I checked the original firmware source, and it was treated as the
same as the SH7751R.

> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> -- 
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

-- 
Yosinori Sato

Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.

[Yoshinori Sato]

On Wed, 25 Oct 2023 20:33:07 +0900,
D. Jeff Dionne wrote:
> 
> Hi Sato-san,
> 
> We must not imply that Renesas is responsible for J2, or that it is a sanctioned SH core.
> 
> J-Core has the responsibility for maintenance of those SH ISA compatible cores.
>

Yes. I know.
I intended to write about ISA compatibility.

> J.
> 
> > On Oct 25, 2023, at 20:14, Yoshinori Sato <ysato@users.sourceforge.jp> wrote:
> > 
> > On Wed, 18 Oct 2023 23:27:43 +0900,
> > Geert Uytterhoeven wrote:
> >> 
> >> Hi Sato-san,
> >> 
> >> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> >> <ysato@users.sourceforge.jp> wrote:
> >>> Renesas SuperH binding definition.
> >>> 
> >>> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> >> 
> >> Thanks for your patch!
> >> 
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
> >>> @@ -0,0 +1,45 @@
> >>> +# SPDX-License-Identifier: GPL-2.0
> >>> +%YAML 1.2
> >>> +---
> >>> +$id: http://devicetree.org/schemas/sh/cpus.yaml#
> >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>> +
> >>> +title: Renesas SuperH CPUs
> >>> +
> >>> +maintainers:
> >>> +  - Yoshinori Sato <ysato@users.sourceforge.jp>
> >>> +
> >>> +description: |+
> >>> +  The device tree allows to describe the layout of CPUs in a system through
> >>> +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> >>> +  defining properties for every cpu.
> >>> +
> >>> +  Bindings for CPU nodes follow the Devicetree Specification, available from:
> >>> +
> >>> +  https://www.devicetree.org/specifications/
> >>> +
> >>> +properties:
> >>> +  compatible:
> >>> +    items:
> >>> +      - enum:
> >> 
> >> Missing
> >> 
> >>    - jcore,j2
> >> 
> >>> +          - renesas,sh4
> >> 
> >> 
> >>> +      - const: renesas,sh
> >> 
> >> I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
> >> "renesas,sh", though.
> >> Is there a common base of instructions that are available on all SH cores?
> > 
> > The base instruction set is sh2.
> > Before that, there is sh1, but this is not compatible with Linux.
> > I think it would be a good idea to change this to "renesas,sh2",
> > but the SH7619 (SH2 CPU) would look like the following.
> > cpus {
> > 	cpu: cpu@0 {
> >        	compatible = "renesas,sh2", "renesas,sh2";
> >        };
> > };
> > 
> >> Missing reg property.
> >> Missing "device_type: true".
> >> 
> >>> +
> >>> +  clock-frequency:
> >>> +    $ref: /schemas/types.yaml#/definitions/uint32
> >>> +    description: |
> >>> +      CPU core clock freqency.
> >> 
> >> Perhaps a "clocks" property instead, or as an alternative?
> >> 
> >> On sh7750, you do have
> >> 
> >>    clocks = <&cpg SH7750_CPG_ICK>;
> >> 
> >>> +
> >>> +required:
> >>> +  - compatible
> >>> +
> >>> +additionalProperties: true
> >>> +
> >>> +examples:
> >>> +  - |
> >>> +        cpus {
> >> 
> >> make dt_binding_check
> >> DT_SCHEMA_FILES=Documentation/devicetree/bindings/sh/cpus.yaml:
> >> 
> >> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
> >> '#address-cells' is a required property
> >>        from schema $id: http://devicetree.org/schemas/cpus.yaml#
> >>        Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
> >> '#size-cells' is a required property
> >> from schema $id: http://devicetree.org/schemas/cpus.yaml#
> >> 
> >>> +                cpu: cpu@0 {
> >>> +                      compatible = "renesas,sh4", "renesas,sh";
> >> 
> >> Documentation/devicetree/bindings/sh/cpus.example.dts:19.28-21.19:
> >> Warning (unit_address_vs_reg): /example-0/cpus/cpu@0: node has a unit
> >> name, but no reg or ranges property
> >> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus: cpu@0:
> >> 'cache-level' is a required property
> >>        from schema $id: http://devicetree.org/schemas/cpus.yaml#
> >> 
> >>> +                };
> >>> +        };
> >>> +...
> >> 
> >> Gr{oetje,eeting}s,
> >> 
> >>                        Geert
> >> 
> >> -- 
> >> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> >> 
> >> In personal conversations with technical people, I call myself a hacker. But
> >> when I'm talking to journalists I just say "programmer" or something like that.
> >>                                -- Linus Torvalds
> > 
> > -- 
> > Yosinori Sato
> 

-- 
Yosinori Sato

Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.

[D. Jeff Dionne]

On Oct 25, 2023, at 21:04, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> 
> Hi Jeff,

Hi Geert,

> 
> On Wed, Oct 25, 2023 at 1:33 PM D. Jeff Dionne <djeffdionne@gmail.com> wrote:
>>> On Oct 25, 2023, at 20:14, Yoshinori Sato <ysato@users.sourceforge.jp> wrote:
>>> On Wed, 18 Oct 2023 23:27:43 +0900,
>>> Geert Uytterhoeven wrote:
>>>> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
>>>> <ysato@users.sourceforge.jp> wrote:
>>>>> Renesas SuperH binding definition.
>>>>> 
>>>>> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> 
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
>>>>> @@ -0,0 +1,45 @@
>>>>> +# SPDX-License-Identifier: GPL-2.0
>>>>> +%YAML 1.2
>>>>> +---
>>>>> +$id: http://devicetree.org/schemas/sh/cpus.yaml#
>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>> +
>>>>> +title: Renesas SuperH CPUs
>>>>> +
>>>>> +maintainers:
>>>>> +  - Yoshinori Sato <ysato@users.sourceforge.jp>
>>>>> +
>>>>> +description: |+
>>>>> +  The device tree allows to describe the layout of CPUs in a system through
>>>>> +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
>>>>> +  defining properties for every cpu.
>>>>> +
>>>>> +  Bindings for CPU nodes follow the Devicetree Specification, available from:
>>>>> +
>>>>> +  https://www.devicetree.org/specifications/
>>>>> +
>>>>> +properties:
>>>>> +  compatible:
>>>>> +    items:
>>>>> +      - enum:
>>>> 
>>>> Missing
>>>> 
>>>>   - jcore,j2
> 
>> We must not imply that Renesas is responsible for J2, or that it is a sanctioned SH core.
> 
> Compatible values do not declare any such endorsement.
> 
>> J-Core has the responsibility for maintenance of those SH ISA compatible cores.
> 
> The question is: does J2 implement the same instruction set as SH2,
> i.e. can it run unmodified SH2 code?

It can run all SH2 code, but an SH2 cannot run all J2 code.

The GCC compilers we use for J2 generate J2 code, not strictly SH2 code.

The main difference is SH3 dynamic shift, and (S390 derived) Compare And Swap.  The new FPU is in testing now, and AFAIK there is no FPU for SH2 but I’m not sure.

Cheers,
J.


>>>> 
>>>>> +          - renesas,sh4
>>>> 
>>>> 
>>>>> +      - const: renesas,sh
>>>> 
>>>> I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
>>>> "renesas,sh", though.
>>>> Is there a common base of instructions that are available on all SH cores?
>>> 
>>> The base instruction set is sh2.
>>> Before that, there is sh1, but this is not compatible with Linux.
>>> I think it would be a good idea to change this to "renesas,sh2",
> 
> Gr{oetje,eeting}s,
> 
>                        Geert
> 
> -- 
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                -- Linus Torvalds

Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.

[Geert Uytterhoeven]

Hi Jeff,

On Wed, Oct 25, 2023 at 2:10 PM D. Jeff Dionne <djeffdionne@gmail.com> wrote:
> On Oct 25, 2023, at 21:04, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Wed, Oct 25, 2023 at 1:33 PM D. Jeff Dionne <djeffdionne@gmail.com> wrote:
> >>> On Oct 25, 2023, at 20:14, Yoshinori Sato <ysato@users.sourceforge.jp> wrote:
> >>> On Wed, 18 Oct 2023 23:27:43 +0900,
> >>> Geert Uytterhoeven wrote:
> >>>> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> >>>> <ysato@users.sourceforge.jp> wrote:
> >>>>> Renesas SuperH binding definition.
> >>>>>
> >>>>> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> >
> >>>>> --- /dev/null
> >>>>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml

> >>>>> +properties:
> >>>>> +  compatible:
> >>>>> +    items:
> >>>>> +      - enum:
> >>>>
> >>>> Missing
> >>>>
> >>>>   - jcore,j2
> >
> >> We must not imply that Renesas is responsible for J2, or that it is a sanctioned SH core.
> >
> > Compatible values do not declare any such endorsement.
> >
> >> J-Core has the responsibility for maintenance of those SH ISA compatible cores.
> >
> > The question is: does J2 implement the same instruction set as SH2,
> > i.e. can it run unmodified SH2 code?
>
> It can run all SH2 code, but an SH2 cannot run all J2 code.

This is exactly what

    compatible = "jcore,j2", "renesas,sh2";

represents.
Cfr. Section 2.3.1 ("compatible") of the Devicetree Specification
https://www.devicetree.org/specifications

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.

[D. Jeff Dionne]

> On Oct 25, 2023, at 21:17, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> 
> Hi Jeff,
> 
> On Wed, Oct 25, 2023 at 2:10 PM D. Jeff Dionne <djeffdionne@gmail.com> wrote:
>> On Oct 25, 2023, at 21:04, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>>> On Wed, Oct 25, 2023 at 1:33 PM D. Jeff Dionne <djeffdionne@gmail.com> wrote:
>>>>> On Oct 25, 2023, at 20:14, Yoshinori Sato <ysato@users.sourceforge.jp> wrote:
>>>>> On Wed, 18 Oct 2023 23:27:43 +0900,
>>>>> Geert Uytterhoeven wrote:
>>>>>> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
>>>>>> <ysato@users.sourceforge.jp> wrote:
>>>>>>> Renesas SuperH binding definition.
>>>>>>> 
>>>>>>> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
>>> 
>>>>>>> --- /dev/null
>>>>>>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
> 
>>>>>>> +properties:
>>>>>>> +  compatible:
>>>>>>> +    items:
>>>>>>> +      - enum:
>>>>>> 
>>>>>> Missing
>>>>>> 
>>>>>>  - jcore,j2
>>> 
>>>> We must not imply that Renesas is responsible for J2, or that it is a sanctioned SH core.
>>> 
>>> Compatible values do not declare any such endorsement.
>>> 
>>>> J-Core has the responsibility for maintenance of those SH ISA compatible cores.
>>> 
>>> The question is: does J2 implement the same instruction set as SH2,
>>> i.e. can it run unmodified SH2 code?
>> 
>> It can run all SH2 code, but an SH2 cannot run all J2 code.
> 
> This is exactly what
> 
>    compatible = "jcore,j2", "renesas,sh2";

Oh, yes.  I agree, this is correct.  Once this is settled upon, we can change new J2 cores so they will export their ROM device tree with the sh2 fallback.

Down thread, Sato-san proposes “renesas,sh4”, “renesas,sh”  I’m not sure I understand what a “renesas,sh” base fallback is.

J.

> represents.
> Cfr. Section 2.3.1 ("compatible") of the Devicetree Specification
> https://www.devicetree.org/specifications
> 
> Gr{oetje,eeting}s,
> 
>                        Geert
> 
> -- 
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                -- Linus Torvalds