From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Conor Dooley <mail@conchuod.ie>
Cc: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>,
Conor.Dooley@microchip.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu, heiko@sntech.de,
atishp@rivosinc.com, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org,
linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
biju.das.jz@bp.renesas.com,
prabhakar.mahadev-lad.rj@bp.renesas.com
Subject: Re: [PATCH v3 07/10] riscv: boot: dts: r9a07g043: Add placeholder nodes
Date: Tue, 20 Sep 2022 14:17:50 +0200 [thread overview]
Message-ID: <CAMuHMdUGD9s96JJafsYdfnPqvg6KLvmC9GUS4yjaaXi2hYrJYQ@mail.gmail.com> (raw)
In-Reply-To: <e15f3e2a-2761-84d9-c5c9-118717e0bb83@conchuod.ie>
Hi Conor,
On Fri, Sep 16, 2022 at 12:40 AM Conor Dooley <mail@conchuod.ie> wrote:
> On 15/09/2022 23:26, Lad, Prabhakar wrote:
> > On Thu, Sep 15, 2022 at 10:36 PM <Conor.Dooley@microchip.com> wrote:
> >> On 15/09/2022 19:15, Prabhakar wrote:
> >>> riscv: boot: dts: r9a07g043: Add placeholder nodes
> >>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >>> Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI.
> >> Can you explain why do you need placeholder nodes for this and
> >> cannot just directly include the other dtsis?
> >>
> > Since the RZ/G2UL SoC is ARM64 where it has a GIC and on RZ/Five SoC
> > we have PLIC for interrupts. Also the interrupt numbering for RZ/Five
> > SoC differs from RZ/G2UL SoC hence we are not directly using the
> > RZ/G2UL SoC DTSI [0].
> >
> > [0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=v6.0-rc5
> >
> > For the RZ/Five SMARC EVK I am re-using the below files [1] (SoM) and
> > [2] (Carrier board) as the RZ/Five SMARC EVK is pin compatible. Since
> > I am re-using these when trying to compile the RZ/Five DTB I get
> > compilation errors since the nodes dont exist (and there is no way
> > currently we can delete the node reference when the actual node itself
> > isn't present) hence these place holders.
> >
> > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi?h=v6.0-rc5
> > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi?h=v6.0-rc5
>
> If this method is acceptable to Geert, this explanation 100% needs to
> go into the commit message.
We've been using these placeholders a lot in Renesas SoC-specific
.dtsi files, as they allow us to introduce gradually support for a new SoC
that is mounted on an existing PCB, and thus shares a board-specific
.dtsi file. Hence I'm fine with this.
However, I think more properties can be dropped from the placeholders.
There is no need to have e.g. 'reg-names' and 'status = "disabled"'
(there is no compatible value, so no matching is done).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2022-09-20 12:18 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-15 18:15 [PATCH v3 00/10] Add support for Renesas RZ/Five SoC Prabhakar
2022-09-15 18:15 ` [PATCH v3 01/10] dt-bindings: soc: renesas: Move renesas.yaml from arm to soc Prabhakar
2022-09-15 21:13 ` Conor.Dooley
2022-09-15 21:56 ` Lad, Prabhakar
2022-09-20 12:00 ` Geert Uytterhoeven
2022-09-15 18:15 ` [PATCH v3 02/10] dt-bindings: riscv: Sort the CPU core list alphabetically Prabhakar
2022-09-15 20:53 ` Heiko Stuebner
2022-09-15 18:15 ` [PATCH v3 03/10] dt-bindings: riscv: Add Andes AX45MP core to the list Prabhakar
2022-09-15 18:15 ` [PATCH v3 04/10] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Prabhakar
2022-09-15 18:15 ` [PATCH v3 05/10] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Prabhakar
2022-09-15 20:58 ` Conor.Dooley
2022-09-15 22:18 ` Lad, Prabhakar
2022-09-15 22:25 ` Conor.Dooley
2022-09-15 18:15 ` [PATCH v3 06/10] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Prabhakar
2022-09-15 18:15 ` [PATCH v3 07/10] riscv: boot: dts: r9a07g043: Add placeholder nodes Prabhakar
2022-09-15 21:36 ` Conor.Dooley
2022-09-15 22:26 ` Lad, Prabhakar
2022-09-15 22:40 ` Conor Dooley
2022-09-20 12:17 ` Geert Uytterhoeven [this message]
2022-09-20 12:31 ` Conor Dooley
2022-09-20 13:46 ` Lad, Prabhakar
2022-09-15 18:15 ` [PATCH v3 08/10] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Prabhakar
2022-09-15 21:56 ` Conor.Dooley
2022-09-15 22:41 ` Lad, Prabhakar
2022-09-15 22:44 ` Conor.Dooley
2022-09-15 22:51 ` Lad, Prabhakar
2022-09-20 12:32 ` Geert Uytterhoeven
2022-09-20 14:05 ` Lad, Prabhakar
2022-09-20 15:07 ` Geert Uytterhoeven
2022-09-20 16:05 ` Lad, Prabhakar
2022-09-15 18:15 ` [PATCH v3 09/10] MAINTAINERS: Add entry for Renesas RISC-V architecture Prabhakar
2022-09-20 12:34 ` Geert Uytterhoeven
2022-09-15 18:15 ` [PATCH v3 10/10] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC Prabhakar
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