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[209.85.128.174]) by smtp.gmail.com with ESMTPSA id bn44-20020a05620a2aec00b006bb619a6a85sm5297417qkb.48.2022.08.20.01.46.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 20 Aug 2022 01:46:08 -0700 (PDT) Received: by mail-yw1-f174.google.com with SMTP id 00721157ae682-3378303138bso135844627b3.9; Sat, 20 Aug 2022 01:46:08 -0700 (PDT) X-Received: by 2002:a81:f47:0:b0:31f:434b:5ee with SMTP id 68-20020a810f47000000b0031f434b05eemr11598577ywp.383.1660985168100; Sat, 20 Aug 2022 01:46:08 -0700 (PDT) MIME-Version: 1.0 References: <20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220815151451.23293-6-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Sat, 20 Aug 2022 10:45:56 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC To: Conor Dooley Cc: "Lad, Prabhakar" , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Anup Patel , Linux-Renesas , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-riscv , Linux Kernel Mailing List , Prabhakar Lad , Biju Das Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Conor, On Fri, Aug 19, 2022 at 8:40 PM wrote: > On 15/08/2022 16:14, Lad Prabhakar wrote: > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > > Single). > > > > Below is the list of IP blocks added in the initial SoC DTSI which can be > > used to boot via initramfs on RZ/Five SMARC EVK: > > - AX45MP CPU > > - CPG > > - PINCTRL > > - PLIC > > - SCIF0 > > - SYSC > > > > Signed-off-by: Lad Prabhakar > > --- > > v1->v2 > > * Dropped including makefile change > > * Updated ndev count > > --- > > arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++ > > 1 file changed, 121 insertions(+) > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi > > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi > > new file mode 100644 > > index 000000000000..b288d2607796 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi > > @@ -0,0 +1,121 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +/* > > + * Device Tree Source for the RZ/Five SoC > > + * > > + * Copyright (C) 2022 Renesas Electronics Corp. > > + */ > > + > > +#include > > +#include > > + > > +/ { > > + compatible = "renesas,r9a07g043"; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ > > + extal_clk: extal-clk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + /* This value must be overridden by the board */ > > + clock-frequency = <0>; > > What's the value in having the clock-frequency here if the board .dtsi > overwrites it? dtbs_check will complain if someone forgets to fill it > IIUC & what the missing frequency means is also kinda obvious, no? Some external clocks may be optional. Hence "dtbs_check" will complain if no "clock-frequency" is missing. > > That aside, by convention so far we have put things like extals or > reference clocks below the /cpus node. Could you do the same here too > please? Really? We've been putting them at the root node for a long time, since the separate "clocks" grouping subnode was deprecated. The extal-clk is not even part of the SoC, so it should definitely not be under the /cpus node. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds