From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: Magnus Damm <magnus.damm@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Prabhakar <prabhakar.csengg@gmail.com>
Subject: Re: [PATCH 2/2] arm64: dts: renesas: r8a774e1: Add cpuidle support for CA5x cores
Date: Thu, 3 Sep 2020 14:39:29 +0200 [thread overview]
Message-ID: <CAMuHMdUKMr+uaXYXyRrJS+HZT93H5LiPoPRcmjNj9Pph7RVnPQ@mail.gmail.com> (raw)
In-Reply-To: <20200827145315.26261-3-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Prabhakar,
On Thu, Aug 27, 2020 at 4:53 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Enable cpuidle (core shutdown) support for RZ/G2H CA5x cores.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> @@ -127,6 +127,7 @@
> power-domains = <&sysc R8A774E1_PD_CA57_CPU0>;
> next-level-cache = <&L2_CA57>;
> enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0>;
> dynamic-power-coefficient = <854>;
> clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
> operating-points-v2 = <&cluster0_opp>;
> @@ -141,6 +142,7 @@
> power-domains = <&sysc R8A774E1_PD_CA57_CPU1>;
> next-level-cache = <&L2_CA57>;
> enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0>;
> clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
> operating-points-v2 = <&cluster0_opp>;
> capacity-dmips-mhz = <1024>;
> @@ -154,6 +156,7 @@
> power-domains = <&sysc R8A774E1_PD_CA57_CPU2>;
> next-level-cache = <&L2_CA57>;
> enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0>;
> clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
> operating-points-v2 = <&cluster0_opp>;
> capacity-dmips-mhz = <1024>;
> @@ -167,6 +170,7 @@
> power-domains = <&sysc R8A774E1_PD_CA57_CPU3>;
> next-level-cache = <&L2_CA57>;
> enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_1>;
CPU_SLEEP_0
> clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
> operating-points-v2 = <&cluster0_opp>;
> capacity-dmips-mhz = <1024>;
> @@ -180,6 +184,7 @@
> power-domains = <&sysc R8A774E1_PD_CA53_CPU0>;
> next-level-cache = <&L2_CA53>;
> enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_1>;
> #cooling-cells = <2>;
> dynamic-power-coefficient = <277>;
> clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
> @@ -194,6 +199,7 @@
> power-domains = <&sysc R8A774E1_PD_CA53_CPU1>;
> next-level-cache = <&L2_CA53>;
> enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_1>;
> clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
> operating-points-v2 = <&cluster1_opp>;
> capacity-dmips-mhz = <535>;
> @@ -206,6 +212,7 @@
> power-domains = <&sysc R8A774E1_PD_CA53_CPU2>;
> next-level-cache = <&L2_CA53>;
> enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_1>;
> clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
> operating-points-v2 = <&cluster1_opp>;
> capacity-dmips-mhz = <535>;
> @@ -218,6 +225,7 @@
> power-domains = <&sysc R8A774E1_PD_CA53_CPU3>;
> next-level-cache = <&L2_CA53>;
> enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_1>;
> clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
> operating-points-v2 = <&cluster1_opp>;
> capacity-dmips-mhz = <535>;
With the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
No need to resend, will fix while queueing in renesas-devel for v5.10.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
prev parent reply other threads:[~2020-09-03 13:54 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-27 14:53 [PATCH 0/2] r8a774e1 add fdp1 and cpuidle support Lad Prabhakar
2020-08-27 14:53 ` [PATCH 1/2] arm64: dts: renesas: r8a774e1: Add FDP1 device nodes Lad Prabhakar
2020-09-03 12:31 ` Geert Uytterhoeven
2020-09-04 10:33 ` Kieran Bingham
2020-08-27 14:53 ` [PATCH 2/2] arm64: dts: renesas: r8a774e1: Add cpuidle support for CA5x cores Lad Prabhakar
2020-09-03 12:39 ` Geert Uytterhoeven [this message]
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