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[209.85.219.178]) by smtp.gmail.com with ESMTPSA id 00721157ae682-63f14c26102sm29111467b3.75.2024.06.24.08.41.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Jun 2024 08:41:08 -0700 (PDT) Received: by mail-yb1-f178.google.com with SMTP id 3f1490d57ef6-e02c4983bfaso4279281276.2; Mon, 24 Jun 2024 08:41:08 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCULCC3ncAztxjHXNng8H6X/tsccXlHwsbkdc3kdWK49cofZO4Yg1ta3VTPw3wK9jdyw5pncPE/S+Ab3292bnwcncirwKAF/Yx6QidYAQPR8gcXZ/7sohZg0TKDj2Vn5dILLN+RcCmrUizSLfZ6OT8MXjVdQHvRxd2vs/aero3PmvRAtsh4+NluDA4wvcJe2xoI8Y44vhd0qkMK5HxIWuzfREXzJc0/I+lI6S6IZ4PuKTKFcT0HLrMzsSg9HWJYURGt9 X-Received: by 2002:a25:b11f:0:b0:dff:3028:4631 with SMTP id 3f1490d57ef6-e0300f86570mr5309852276.33.1719243668079; Mon, 24 Jun 2024 08:41:08 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240621112303.1607621-1-claudiu.beznea.uj@bp.renesas.com> <20240621112303.1607621-9-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: <20240621112303.1607621-9-claudiu.beznea.uj@bp.renesas.com> From: Geert Uytterhoeven Date: Mon, 24 Jun 2024 17:40:56 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support To: Claudiu Cc: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com, linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Claudiu, On Fri, Jun 21, 2024 at 1:23=E2=80=AFPM Claudiu = wrote: > From: Claudiu Beznea > > Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is compatible with > the version available on Renesas RZ/V2H (R9A09G075). Most of the IP > variants that the RIIC driver is working with supports fast mode plus. > However, it happens that on the same SoC to have IP instatiations that > support fast mode plus as well as IP instantiation that doesn't support > it. For this, introduced the renesas,riic-no-fast-mode-plus property. > > Signed-off-by: Claudiu Beznea Thanks for your patch! > --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml > +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml > @@ -25,6 +25,10 @@ properties: > - renesas,riic-r9a07g054 # RZ/V2L > - const: renesas,riic-rz # RZ/A or RZ/G2L > > + - items: > + - const: renesas,riic-r9a08g045 # RZ/G3S > + - const: renesas,riic-r9a09g057 > + LGTM. > - const: renesas,riic-r9a09g057 # RZ/V2H(P) > > reg: > @@ -66,6 +70,10 @@ properties: > resets: > maxItems: 1 > > + renesas,riic-no-fast-mode-plus: > + description: specifies if fast mode plus is not supported > + type: boolean > + Do you really need this? The bus' clock-frequency property should take into account the combined capabilities of all of controller, target, and wiring. It is up to the DTS writer to validate that all timing conditions are met. > required: > - compatible > - reg Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds