[PATCH 00/12] i2c: riic: Add support for Renesas RZ/G3S

[PATCH 00/12] i2c: riic: Add support for Renesas RZ/G3S

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Hi,

Series adds I2C support for the Renesas RZ/G3S SoC.

Series is split as follows:
- patch 01/12      - add clock, reset and PM domain support
- patch 02-03/12   - add some cleanups on RIIC driver
- patch 05/12      - enable runtime autosuspend support on the RIIC driver
- patch 06/12      - add suspend to RAM support on the RIIC driver
- patch 07/12      - prepares for the addition of fast mode plus
- patch 08/12      - updates the I2C documentation for the RZ/G3S SoC
- patch 09/12      - add fast mode plus support on the RIIC driver
- patches 10-12/12 - device tree support

Thank you,
Claudiu Beznea

Claudiu Beznea (12):
  clk: renesas: r9a08g045: Add clock, reset and power domain support for
    I2C
  i2c: riic: Use temporary variable for struct device
  i2c: riic: Call pm_runtime_get_sync() when need to access registers
  i2c: riic: Use pm_runtime_resume_and_get()
  i2c: riic: Enable runtime PM autosuspend support
  i2c: riic: Add suspend/resume support
  i2c: riic: Define individual arrays to describe the register offsets
  dt-bindings: i2c: renesas,riic: Document the R9A08G045 support
  i2c: riic: Add support for fast mode plus
  arm64: dts: renesas: r9a08g045: Add I2C nodes
  arm64: dts: renesas: rzg3s-smarc: Enable i2c0 node
  arm64: dts: renesas: rzg3s-smarc-som: Enable i2c1 node

 .../devicetree/bindings/i2c/renesas,riic.yaml |   8 +
 arch/arm64/boot/dts/renesas/r9a08g045.dtsi    |  90 +++++++
 .../boot/dts/renesas/rzg3s-smarc-som.dtsi     |   5 +
 arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi  |   7 +
 drivers/clk/renesas/r9a08g045-cpg.c           |  20 ++
 drivers/i2c/busses/i2c-riic.c                 | 240 ++++++++++++------
 6 files changed, 299 insertions(+), 71 deletions(-)

-- 
2.39.2

[PATCH 01/12] clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Add clock, reset and power domain support for the I2C channels available
on the Renesas RZ/G3S SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/clk/renesas/r9a08g045-cpg.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index b068733b145f..a07eb3b359fc 100644
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -213,6 +213,10 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
 	DEF_COUPLED("eth1_axi",		R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1),
 	DEF_COUPLED("eth1_chi",		R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1),
 	DEF_MOD("eth1_refclk",		R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9),
+	DEF_MOD("i2c0",			R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0),
+	DEF_MOD("i2c1",			R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1),
+	DEF_MOD("i2c2",			R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2),
+	DEF_MOD("i2c3",			R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3),
 	DEF_MOD("scif0_clk_pck",	R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),
 	DEF_MOD("gpio_hclk",		R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
 };
@@ -227,6 +231,10 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
 	DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
 	DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0),
 	DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1),
+	DEF_RST(R9A08G045_I2C0_MRST, 0x880, 0),
+	DEF_RST(R9A08G045_I2C1_MRST, 0x880, 1),
+	DEF_RST(R9A08G045_I2C2_MRST, 0x880, 2),
+	DEF_RST(R9A08G045_I2C3_MRST, 0x880, 3),
 	DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0),
 	DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),
 	DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),
@@ -272,6 +280,18 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
 	DEF_PD("eth1",		R9A08G045_PD_ETHER1,
 				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)),
 				RZG2L_PD_F_NONE),
+	DEF_PD("i2c0",		R9A08G045_PD_I2C0,
+				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)),
+				RZG2L_PD_F_NONE),
+	DEF_PD("i2c1",		R9A08G045_PD_I2C1,
+				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)),
+				RZG2L_PD_F_NONE),
+	DEF_PD("i2c2",		R9A08G045_PD_I2C2,
+				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)),
+				RZG2L_PD_F_NONE),
+	DEF_PD("i2c3",		R9A08G045_PD_I2C3,
+				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)),
+				RZG2L_PD_F_NONE),
 	DEF_PD("scif0",		R9A08G045_PD_SCIF0,
 				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),
 				RZG2L_PD_F_NONE),
-- 
2.39.2

[PATCH 02/12] i2c: riic: Use temporary variable for struct device

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Use a temporary variable for the struct device pointers to avoid
dereferencing.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/i2c/busses/i2c-riic.c | 53 ++++++++++++++++++-----------------
 1 file changed, 28 insertions(+), 25 deletions(-)

diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
index f608b1838cad..c08c988f50c7 100644
--- a/drivers/i2c/busses/i2c-riic.c
+++ b/drivers/i2c/busses/i2c-riic.c
@@ -131,11 +131,12 @@ static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u
 static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 {
 	struct riic_dev *riic = i2c_get_adapdata(adap);
+	struct device *dev = adap->dev.parent;
 	unsigned long time_left;
 	int i;
 	u8 start_bit;
 
-	pm_runtime_get_sync(adap->dev.parent);
+	pm_runtime_get_sync(dev);
 
 	if (riic_readb(riic, RIIC_ICCR2) & ICCR2_BBSY) {
 		riic->err = -EBUSY;
@@ -168,7 +169,7 @@ static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 	}
 
  out:
-	pm_runtime_put(adap->dev.parent);
+	pm_runtime_put(dev);
 
 	return riic->err ?: num;
 }
@@ -303,11 +304,12 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
 	int ret = 0;
 	unsigned long rate;
 	int total_ticks, cks, brl, brh;
+	struct device *dev = riic->adapter.dev.parent;
 
-	pm_runtime_get_sync(riic->adapter.dev.parent);
+	pm_runtime_get_sync(dev);
 
 	if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) {
-		dev_err(&riic->adapter.dev,
+		dev_err(dev,
 			"unsupported bus speed (%dHz). %d max\n",
 			t->bus_freq_hz, I2C_MAX_FAST_MODE_FREQ);
 		ret = -EINVAL;
@@ -347,7 +349,7 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
 	}
 
 	if (brl > (0x1F + 3)) {
-		dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n",
+		dev_err(dev, "invalid speed (%lu). Too slow.\n",
 			(unsigned long)t->bus_freq_hz);
 		ret = -EINVAL;
 		goto out;
@@ -396,7 +398,7 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
 	riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
 
 out:
-	pm_runtime_put(riic->adapter.dev.parent);
+	pm_runtime_put(dev);
 	return ret;
 }
 
@@ -415,13 +417,14 @@ static void riic_reset_control_assert(void *data)
 
 static int riic_i2c_probe(struct platform_device *pdev)
 {
+	struct device *dev = &pdev->dev;
 	struct riic_dev *riic;
 	struct i2c_adapter *adap;
 	struct i2c_timings i2c_t;
 	struct reset_control *rstc;
 	int i, ret;
 
-	riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL);
+	riic = devm_kzalloc(dev, sizeof(*riic), GFP_KERNEL);
 	if (!riic)
 		return -ENOMEM;
 
@@ -429,22 +432,22 @@ static int riic_i2c_probe(struct platform_device *pdev)
 	if (IS_ERR(riic->base))
 		return PTR_ERR(riic->base);
 
-	riic->clk = devm_clk_get(&pdev->dev, NULL);
+	riic->clk = devm_clk_get(dev, NULL);
 	if (IS_ERR(riic->clk)) {
-		dev_err(&pdev->dev, "missing controller clock");
+		dev_err(dev, "missing controller clock");
 		return PTR_ERR(riic->clk);
 	}
 
-	rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
+	rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
 	if (IS_ERR(rstc))
-		return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
+		return dev_err_probe(dev, PTR_ERR(rstc),
 				     "Error: missing reset ctrl\n");
 
 	ret = reset_control_deassert(rstc);
 	if (ret)
 		return ret;
 
-	ret = devm_add_action_or_reset(&pdev->dev, riic_reset_control_assert, rstc);
+	ret = devm_add_action_or_reset(dev, riic_reset_control_assert, rstc);
 	if (ret)
 		return ret;
 
@@ -453,29 +456,29 @@ static int riic_i2c_probe(struct platform_device *pdev)
 		if (ret < 0)
 			return ret;
 
-		ret = devm_request_irq(&pdev->dev, ret, riic_irqs[i].isr,
+		ret = devm_request_irq(dev, ret, riic_irqs[i].isr,
 				       0, riic_irqs[i].name, riic);
 		if (ret) {
-			dev_err(&pdev->dev, "failed to request irq %s\n", riic_irqs[i].name);
+			dev_err(dev, "failed to request irq %s\n", riic_irqs[i].name);
 			return ret;
 		}
 	}
 
-	riic->info = of_device_get_match_data(&pdev->dev);
+	riic->info = of_device_get_match_data(dev);
 
 	adap = &riic->adapter;
 	i2c_set_adapdata(adap, riic);
 	strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
 	adap->owner = THIS_MODULE;
 	adap->algo = &riic_algo;
-	adap->dev.parent = &pdev->dev;
-	adap->dev.of_node = pdev->dev.of_node;
+	adap->dev.parent = dev;
+	adap->dev.of_node = dev->of_node;
 
 	init_completion(&riic->msg_done);
 
-	i2c_parse_fw_timings(&pdev->dev, &i2c_t, true);
+	i2c_parse_fw_timings(dev, &i2c_t, true);
 
-	pm_runtime_enable(&pdev->dev);
+	pm_runtime_enable(dev);
 
 	ret = riic_init_hw(riic, &i2c_t);
 	if (ret)
@@ -487,24 +490,24 @@ static int riic_i2c_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, riic);
 
-	dev_info(&pdev->dev, "registered with %dHz bus speed\n",
-		 i2c_t.bus_freq_hz);
+	dev_info(dev, "registered with %dHz bus speed\n", i2c_t.bus_freq_hz);
 	return 0;
 
 out:
-	pm_runtime_disable(&pdev->dev);
+	pm_runtime_disable(dev);
 	return ret;
 }
 
 static void riic_i2c_remove(struct platform_device *pdev)
 {
 	struct riic_dev *riic = platform_get_drvdata(pdev);
+	struct device *dev = &pdev->dev;
 
-	pm_runtime_get_sync(&pdev->dev);
+	pm_runtime_get_sync(dev);
 	riic_writeb(riic, 0, RIIC_ICIER);
-	pm_runtime_put(&pdev->dev);
+	pm_runtime_put(dev);
 	i2c_del_adapter(&riic->adapter);
-	pm_runtime_disable(&pdev->dev);
+	pm_runtime_disable(dev);
 }
 
 static const struct riic_of_data riic_rz_a_info = {
-- 
2.39.2

[PATCH 03/12] i2c: riic: Call pm_runtime_get_sync() when need to access registers

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

There is no need to runtime resume the device as long as the IP registers
are not accessed. Calling pm_runtime_get_sync() at the register access
time leads to a simpler error path.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/i2c/busses/i2c-riic.c | 14 +++++---------
 1 file changed, 5 insertions(+), 9 deletions(-)

diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
index c08c988f50c7..83e4d5e14ab6 100644
--- a/drivers/i2c/busses/i2c-riic.c
+++ b/drivers/i2c/busses/i2c-riic.c
@@ -301,19 +301,15 @@ static const struct i2c_algorithm riic_algo = {
 
 static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
 {
-	int ret = 0;
 	unsigned long rate;
 	int total_ticks, cks, brl, brh;
 	struct device *dev = riic->adapter.dev.parent;
 
-	pm_runtime_get_sync(dev);
-
 	if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) {
 		dev_err(dev,
 			"unsupported bus speed (%dHz). %d max\n",
 			t->bus_freq_hz, I2C_MAX_FAST_MODE_FREQ);
-		ret = -EINVAL;
-		goto out;
+		return -EINVAL;
 	}
 
 	rate = clk_get_rate(riic->clk);
@@ -351,8 +347,7 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
 	if (brl > (0x1F + 3)) {
 		dev_err(dev, "invalid speed (%lu). Too slow.\n",
 			(unsigned long)t->bus_freq_hz);
-		ret = -EINVAL;
-		goto out;
+		return -EINVAL;
 	}
 
 	brh = total_ticks - brl;
@@ -384,6 +379,8 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
 		 t->scl_fall_ns / (1000000000 / rate),
 		 t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);
 
+	pm_runtime_get_sync(dev);
+
 	/* Changing the order of accessing IICRST and ICE may break things! */
 	riic_writeb(riic, ICCR1_IICRST | ICCR1_SOWP, RIIC_ICCR1);
 	riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);
@@ -397,9 +394,8 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
 
 	riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
 
-out:
 	pm_runtime_put(dev);
-	return ret;
+	return 0;
 }
 
 static struct riic_irq_desc riic_irqs[] = {
-- 
2.39.2

[PATCH 04/12] i2c: riic: Use pm_runtime_resume_and_get()

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

pm_runtime_get_sync() may return with error. In case it returns with error
dev->power.usage_count needs to be decremented. pm_runtime_resume_and_get()
takes care of this. Thus use it.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/i2c/busses/i2c-riic.c | 25 +++++++++++++++++++++----
 1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
index 83e4d5e14ab6..6b739483ef37 100644
--- a/drivers/i2c/busses/i2c-riic.c
+++ b/drivers/i2c/busses/i2c-riic.c
@@ -113,6 +113,8 @@ struct riic_irq_desc {
 	char *name;
 };
 
+static const char * const riic_rpm_err_msg = "Failed to runtime resume";
+
 static inline void riic_writeb(struct riic_dev *riic, u8 val, u8 offset)
 {
 	writeb(val, riic->base + riic->info->regs[offset]);
@@ -133,10 +135,14 @@ static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 	struct riic_dev *riic = i2c_get_adapdata(adap);
 	struct device *dev = adap->dev.parent;
 	unsigned long time_left;
-	int i;
+	int i, ret;
 	u8 start_bit;
 
-	pm_runtime_get_sync(dev);
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret) {
+		dev_err(dev, riic_rpm_err_msg);
+		return ret;
+	}
 
 	if (riic_readb(riic, RIIC_ICCR2) & ICCR2_BBSY) {
 		riic->err = -EBUSY;
@@ -301,6 +307,7 @@ static const struct i2c_algorithm riic_algo = {
 
 static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
 {
+	int ret;
 	unsigned long rate;
 	int total_ticks, cks, brl, brh;
 	struct device *dev = riic->adapter.dev.parent;
@@ -379,7 +386,11 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
 		 t->scl_fall_ns / (1000000000 / rate),
 		 t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);
 
-	pm_runtime_get_sync(dev);
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret) {
+		dev_err(dev, riic_rpm_err_msg);
+		return ret;
+	}
 
 	/* Changing the order of accessing IICRST and ICE may break things! */
 	riic_writeb(riic, ICCR1_IICRST | ICCR1_SOWP, RIIC_ICCR1);
@@ -498,8 +509,14 @@ static void riic_i2c_remove(struct platform_device *pdev)
 {
 	struct riic_dev *riic = platform_get_drvdata(pdev);
 	struct device *dev = &pdev->dev;
+	int ret;
+
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret) {
+		dev_err(dev, riic_rpm_err_msg);
+		return;
+	}
 
-	pm_runtime_get_sync(dev);
 	riic_writeb(riic, 0, RIIC_ICIER);
 	pm_runtime_put(dev);
 	i2c_del_adapter(&riic->adapter);
-- 
2.39.2

RE: [PATCH 04/12] i2c: riic: Use pm_runtime_resume_and_get()

[Biju Das]

Hi Claudiu,

Thanks for the patch.

> -----Original Message-----
> From: Claudiu <claudiu.beznea@tuxon.dev>
> Sent: Friday, June 21, 2024 12:23 PM
> Subject: [PATCH 04/12] i2c: riic: Use pm_runtime_resume_and_get()
> 
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> pm_runtime_get_sync() may return with error. In case it returns with error
> dev->power.usage_count needs to be decremented.
> dev->pm_runtime_resume_and_get()
> takes care of this. Thus use it.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>  drivers/i2c/busses/i2c-riic.c | 25 +++++++++++++++++++++----
>  1 file changed, 21 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index
> 83e4d5e14ab6..6b739483ef37 100644
> --- a/drivers/i2c/busses/i2c-riic.c
> +++ b/drivers/i2c/busses/i2c-riic.c
> @@ -113,6 +113,8 @@ struct riic_irq_desc {
>  	char *name;
>  };
> 
> +static const char * const riic_rpm_err_msg = "Failed to runtime
> +resume";
> +
>  static inline void riic_writeb(struct riic_dev *riic, u8 val, u8 offset)  {
>  	writeb(val, riic->base + riic->info->regs[offset]); @@ -133,10 +135,14 @@ static int
> riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
>  	struct riic_dev *riic = i2c_get_adapdata(adap);
>  	struct device *dev = adap->dev.parent;
>  	unsigned long time_left;
> -	int i;
> +	int i, ret;
>  	u8 start_bit;
> 
> -	pm_runtime_get_sync(dev);
> +	ret = pm_runtime_resume_and_get(dev);
> +	if (ret) {
> +		dev_err(dev, riic_rpm_err_msg);
> +		return ret;
> +	}
> 
>  	if (riic_readb(riic, RIIC_ICCR2) & ICCR2_BBSY) {
>  		riic->err = -EBUSY;
> @@ -301,6 +307,7 @@ static const struct i2c_algorithm riic_algo = {
> 
>  static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)  {
> +	int ret;
>  	unsigned long rate;
>  	int total_ticks, cks, brl, brh;
>  	struct device *dev = riic->adapter.dev.parent; @@ -379,7 +386,11 @@ static int
> riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
>  		 t->scl_fall_ns / (1000000000 / rate),
>  		 t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);
> 
> -	pm_runtime_get_sync(dev);
> +	ret = pm_runtime_resume_and_get(dev);
> +	if (ret) {
> +		dev_err(dev, riic_rpm_err_msg);
> +		return ret;
> +	}
> 
>  	/* Changing the order of accessing IICRST and ICE may break things! */
>  	riic_writeb(riic, ICCR1_IICRST | ICCR1_SOWP, RIIC_ICCR1); @@ -498,8 +509,14 @@ static void
> riic_i2c_remove(struct platform_device *pdev)  {
>  	struct riic_dev *riic = platform_get_drvdata(pdev);
>  	struct device *dev = &pdev->dev;
> +	int ret;
> +
> +	ret = pm_runtime_resume_and_get(dev);
> +	if (ret) {
> +		dev_err(dev, riic_rpm_err_msg);
> +		return;
> +	}

This change will lead to resource leak. Maybe if there is error
skip accessing the register. Or restore previous code,
just ignore condition in remove.

There are other place in i2c core driver where this call can fail.
You could fix as well.
https://elixir.bootlin.com/linux/v6.10-rc4/source/drivers/i2c/i2c-core-base.c#L509

Cheers,
Biju

> 
> -	pm_runtime_get_sync(dev);
>  	riic_writeb(riic, 0, RIIC_ICIER);
>  	pm_runtime_put(dev);
>  	i2c_del_adapter(&riic->adapter);
> --
> 2.39.2
> 

Re: [PATCH 04/12] i2c: riic: Use pm_runtime_resume_and_get()

[claudiu beznea]

Hi, Biju,

On 21.06.2024 15:24, Biju Das wrote:
> Hi Claudiu,
> 
> Thanks for the patch.
> 
>> -----Original Message-----
>> From: Claudiu <claudiu.beznea@tuxon.dev>
>> Sent: Friday, June 21, 2024 12:23 PM
>> Subject: [PATCH 04/12] i2c: riic: Use pm_runtime_resume_and_get()
>>
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> pm_runtime_get_sync() may return with error. In case it returns with error
>> dev->power.usage_count needs to be decremented.
>> dev->pm_runtime_resume_and_get()
>> takes care of this. Thus use it.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>> ---
>>  drivers/i2c/busses/i2c-riic.c | 25 +++++++++++++++++++++----
>>  1 file changed, 21 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index
>> 83e4d5e14ab6..6b739483ef37 100644
>> --- a/drivers/i2c/busses/i2c-riic.c
>> +++ b/drivers/i2c/busses/i2c-riic.c
>> @@ -113,6 +113,8 @@ struct riic_irq_desc {
>>  	char *name;
>>  };
>>
>> +static const char * const riic_rpm_err_msg = "Failed to runtime
>> +resume";
>> +
>>  static inline void riic_writeb(struct riic_dev *riic, u8 val, u8 offset)  {
>>  	writeb(val, riic->base + riic->info->regs[offset]); @@ -133,10 +135,14 @@ static int
>> riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
>>  	struct riic_dev *riic = i2c_get_adapdata(adap);
>>  	struct device *dev = adap->dev.parent;
>>  	unsigned long time_left;
>> -	int i;
>> +	int i, ret;
>>  	u8 start_bit;
>>
>> -	pm_runtime_get_sync(dev);
>> +	ret = pm_runtime_resume_and_get(dev);
>> +	if (ret) {
>> +		dev_err(dev, riic_rpm_err_msg);
>> +		return ret;
>> +	}
>>
>>  	if (riic_readb(riic, RIIC_ICCR2) & ICCR2_BBSY) {
>>  		riic->err = -EBUSY;
>> @@ -301,6 +307,7 @@ static const struct i2c_algorithm riic_algo = {
>>
>>  static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)  {
>> +	int ret;
>>  	unsigned long rate;
>>  	int total_ticks, cks, brl, brh;
>>  	struct device *dev = riic->adapter.dev.parent; @@ -379,7 +386,11 @@ static int
>> riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
>>  		 t->scl_fall_ns / (1000000000 / rate),
>>  		 t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);
>>
>> -	pm_runtime_get_sync(dev);
>> +	ret = pm_runtime_resume_and_get(dev);
>> +	if (ret) {
>> +		dev_err(dev, riic_rpm_err_msg);
>> +		return ret;
>> +	}
>>
>>  	/* Changing the order of accessing IICRST and ICE may break things! */
>>  	riic_writeb(riic, ICCR1_IICRST | ICCR1_SOWP, RIIC_ICCR1); @@ -498,8 +509,14 @@ static void
>> riic_i2c_remove(struct platform_device *pdev)  {
>>  	struct riic_dev *riic = platform_get_drvdata(pdev);
>>  	struct device *dev = &pdev->dev;
>> +	int ret;
>> +
>> +	ret = pm_runtime_resume_and_get(dev);
>> +	if (ret) {
>> +		dev_err(dev, riic_rpm_err_msg);
>> +		return;
>> +	}
> 
> This change will lead to resource leak. Maybe if there is error
> skip accessing the register. Or restore previous code,
> just ignore condition in remove.

Ok, I'll delete the adapter.

> 
> There are other place in i2c core driver where this call can fail.
> You could fix as well.
> https://elixir.bootlin.com/linux/v6.10-rc4/source/drivers/i2c/i2c-core-base.c#L509

Yes, there are many other places as well. Wolfram, would you prefer
touching that code, as well?

Thank you,
Claudiu Beznea

> 
> Cheers,
> Biju
> 
>>
>> -	pm_runtime_get_sync(dev);
>>  	riic_writeb(riic, 0, RIIC_ICIER);
>>  	pm_runtime_put(dev);
>>  	i2c_del_adapter(&riic->adapter);
>> --
>> 2.39.2
>>
> 

[PATCH 05/12] i2c: riic: Enable runtime PM autosuspend support

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Enable runtime PM autosuspend support for the RIIC driver. With this, in
case there are consecutive xfer requests the device wouldn't be runtime
enabled/disabled after each consecutive xfer but after the
the delay configured by user. With this, we can avoid touching hardware
registers involved in runtime PM suspend/resume saving in this way some
cycles. The default chosen autosuspend delay is zero to keep the
previous driver behavior.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/i2c/busses/i2c-riic.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
index 6b739483ef37..00fb09786e48 100644
--- a/drivers/i2c/busses/i2c-riic.c
+++ b/drivers/i2c/busses/i2c-riic.c
@@ -175,7 +175,8 @@ static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 	}
 
  out:
-	pm_runtime_put(dev);
+	pm_runtime_mark_last_busy(dev);
+	pm_runtime_put_autosuspend(dev);
 
 	return riic->err ?: num;
 }
@@ -405,7 +406,8 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
 
 	riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
 
-	pm_runtime_put(dev);
+	pm_runtime_mark_last_busy(dev);
+	pm_runtime_put_autosuspend(dev);
 	return 0;
 }
 
@@ -485,6 +487,8 @@ static int riic_i2c_probe(struct platform_device *pdev)
 
 	i2c_parse_fw_timings(dev, &i2c_t, true);
 
+	pm_runtime_set_autosuspend_delay(dev, 0);
+	pm_runtime_use_autosuspend(dev);
 	pm_runtime_enable(dev);
 
 	ret = riic_init_hw(riic, &i2c_t);
@@ -502,6 +506,7 @@ static int riic_i2c_probe(struct platform_device *pdev)
 
 out:
 	pm_runtime_disable(dev);
+	pm_runtime_dont_use_autosuspend(dev);
 	return ret;
 }
 
@@ -521,6 +526,7 @@ static void riic_i2c_remove(struct platform_device *pdev)
 	pm_runtime_put(dev);
 	i2c_del_adapter(&riic->adapter);
 	pm_runtime_disable(dev);
+	pm_runtime_dont_use_autosuspend(dev);
 }
 
 static const struct riic_of_data riic_rz_a_info = {
-- 
2.39.2

[PATCH 06/12] i2c: riic: Add suspend/resume support

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Add suspend/resume support for the RIIC driver. This is necessary for the
Renesas RZ/G3S SoC which support suspend to deep sleep state where power
to most of the SoC components is turned off. As a result the I2C controller
needs to be reconfigured after suspend/resume. For this, the reset line
was stored in the driver private data structure as well as i2c timings.
The reset line and I2C timings are necessary to re-initialize the
controller after resume.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/i2c/busses/i2c-riic.c | 66 +++++++++++++++++++++++++++++------
 1 file changed, 55 insertions(+), 11 deletions(-)

diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
index 00fb09786e48..f9b9e92570d8 100644
--- a/drivers/i2c/busses/i2c-riic.c
+++ b/drivers/i2c/busses/i2c-riic.c
@@ -105,6 +105,8 @@ struct riic_dev {
 	struct completion msg_done;
 	struct i2c_adapter adapter;
 	struct clk *clk;
+	struct reset_control *rstc;
+	struct i2c_timings i2c_t;
 };
 
 struct riic_irq_desc {
@@ -306,11 +308,12 @@ static const struct i2c_algorithm riic_algo = {
 	.functionality	= riic_func,
 };
 
-static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
+static int riic_init_hw(struct riic_dev *riic)
 {
 	int ret;
 	unsigned long rate;
 	int total_ticks, cks, brl, brh;
+	struct i2c_timings *t = &riic->i2c_t;
 	struct device *dev = riic->adapter.dev.parent;
 
 	if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) {
@@ -429,8 +432,6 @@ static int riic_i2c_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct riic_dev *riic;
 	struct i2c_adapter *adap;
-	struct i2c_timings i2c_t;
-	struct reset_control *rstc;
 	int i, ret;
 
 	riic = devm_kzalloc(dev, sizeof(*riic), GFP_KERNEL);
@@ -447,16 +448,16 @@ static int riic_i2c_probe(struct platform_device *pdev)
 		return PTR_ERR(riic->clk);
 	}
 
-	rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
-	if (IS_ERR(rstc))
-		return dev_err_probe(dev, PTR_ERR(rstc),
+	riic->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
+	if (IS_ERR(riic->rstc))
+		return dev_err_probe(dev, PTR_ERR(riic->rstc),
 				     "Error: missing reset ctrl\n");
 
-	ret = reset_control_deassert(rstc);
+	ret = reset_control_deassert(riic->rstc);
 	if (ret)
 		return ret;
 
-	ret = devm_add_action_or_reset(dev, riic_reset_control_assert, rstc);
+	ret = devm_add_action_or_reset(dev, riic_reset_control_assert, riic->rstc);
 	if (ret)
 		return ret;
 
@@ -485,13 +486,13 @@ static int riic_i2c_probe(struct platform_device *pdev)
 
 	init_completion(&riic->msg_done);
 
-	i2c_parse_fw_timings(dev, &i2c_t, true);
+	i2c_parse_fw_timings(dev, &riic->i2c_t, true);
 
 	pm_runtime_set_autosuspend_delay(dev, 0);
 	pm_runtime_use_autosuspend(dev);
 	pm_runtime_enable(dev);
 
-	ret = riic_init_hw(riic, &i2c_t);
+	ret = riic_init_hw(riic);
 	if (ret)
 		goto out;
 
@@ -501,7 +502,7 @@ static int riic_i2c_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, riic);
 
-	dev_info(dev, "registered with %dHz bus speed\n", i2c_t.bus_freq_hz);
+	dev_info(dev, "registered with %dHz bus speed\n", riic->i2c_t.bus_freq_hz);
 	return 0;
 
 out:
@@ -561,6 +562,48 @@ static const struct riic_of_data riic_rz_v2h_info = {
 	},
 };
 
+static int riic_i2c_suspend(struct device *dev)
+{
+	struct riic_dev *riic = dev_get_drvdata(dev);
+	int ret;
+
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret)
+		return ret;
+
+	i2c_mark_adapter_suspended(&riic->adapter);
+
+	/* Disable output on SDA, SCL pins. */
+	riic_clear_set_bit(riic, ICCR1_ICE, 0, RIIC_ICCR1);
+
+	pm_runtime_mark_last_busy(dev);
+	pm_runtime_put_sync(dev);
+
+	return reset_control_assert(riic->rstc);
+}
+
+static int riic_i2c_resume(struct device *dev)
+{
+	struct riic_dev *riic = dev_get_drvdata(dev);
+	int ret;
+
+	ret = reset_control_deassert(riic->rstc);
+	if (ret)
+		return ret;
+
+	ret = riic_init_hw(riic);
+	if (ret)
+		return ret;
+
+	i2c_mark_adapter_resumed(&riic->adapter);
+
+	return 0;
+}
+
+static const struct dev_pm_ops riic_i2c_pm_ops = {
+	SYSTEM_SLEEP_PM_OPS(riic_i2c_suspend, riic_i2c_resume)
+};
+
 static const struct of_device_id riic_i2c_dt_ids[] = {
 	{ .compatible = "renesas,riic-rz", .data = &riic_rz_a_info },
 	{ .compatible = "renesas,riic-r9a09g057", .data = &riic_rz_v2h_info },
@@ -573,6 +616,7 @@ static struct platform_driver riic_i2c_driver = {
 	.driver		= {
 		.name	= "i2c-riic",
 		.of_match_table = riic_i2c_dt_ids,
+		.pm	= pm_ptr(&riic_i2c_pm_ops),
 	},
 };
 
-- 
2.39.2

RE: [PATCH 06/12] i2c: riic: Add suspend/resume support

[Biju Das]

Hi Claudiu,

Thanks for the patch

> -----Original Message-----
> From: Claudiu <claudiu.beznea@tuxon.dev>
> Sent: Friday, June 21, 2024 12:23 PM
> Subject: [PATCH 06/12] i2c: riic: Add suspend/resume support
> 
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Add suspend/resume support for the RIIC driver. This is necessary for the Renesas RZ/G3S SoC which
> support suspend to deep sleep state where power to most of the SoC components is turned off. As a
> result the I2C controller needs to be reconfigured after suspend/resume. For this, the reset line
> was stored in the driver private data structure as well as i2c timings.
> The reset line and I2C timings are necessary to re-initialize the controller after resume.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>  drivers/i2c/busses/i2c-riic.c | 66 +++++++++++++++++++++++++++++------
>  1 file changed, 55 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index
> 00fb09786e48..f9b9e92570d8 100644
> --- a/drivers/i2c/busses/i2c-riic.c
> +++ b/drivers/i2c/busses/i2c-riic.c
> @@ -105,6 +105,8 @@ struct riic_dev {
>  	struct completion msg_done;
>  	struct i2c_adapter adapter;
>  	struct clk *clk;
> +	struct reset_control *rstc;
> +	struct i2c_timings i2c_t;
>  };
> 
>  struct riic_irq_desc {
> @@ -306,11 +308,12 @@ static const struct i2c_algorithm riic_algo = {
>  	.functionality	= riic_func,
>  };
> 
> -static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
> +static int riic_init_hw(struct riic_dev *riic)
>  {
>  	int ret;
>  	unsigned long rate;
>  	int total_ticks, cks, brl, brh;
> +	struct i2c_timings *t = &riic->i2c_t;
>  	struct device *dev = riic->adapter.dev.parent;
> 
>  	if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) { @@ -429,8 +432,6 @@ static int
> riic_i2c_probe(struct platform_device *pdev)
>  	struct device *dev = &pdev->dev;
>  	struct riic_dev *riic;
>  	struct i2c_adapter *adap;
> -	struct i2c_timings i2c_t;
> -	struct reset_control *rstc;
>  	int i, ret;
> 
>  	riic = devm_kzalloc(dev, sizeof(*riic), GFP_KERNEL); @@ -447,16 +448,16 @@ static int
> riic_i2c_probe(struct platform_device *pdev)
>  		return PTR_ERR(riic->clk);
>  	}
> 
> -	rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
> -	if (IS_ERR(rstc))
> -		return dev_err_probe(dev, PTR_ERR(rstc),
> +	riic->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
> +	if (IS_ERR(riic->rstc))
> +		return dev_err_probe(dev, PTR_ERR(riic->rstc),
>  				     "Error: missing reset ctrl\n");
> 
> -	ret = reset_control_deassert(rstc);
> +	ret = reset_control_deassert(riic->rstc);
>  	if (ret)
>  		return ret;
> 
> -	ret = devm_add_action_or_reset(dev, riic_reset_control_assert, rstc);
> +	ret = devm_add_action_or_reset(dev, riic_reset_control_assert,
> +riic->rstc);
>  	if (ret)
>  		return ret;
> 
> @@ -485,13 +486,13 @@ static int riic_i2c_probe(struct platform_device *pdev)
> 
>  	init_completion(&riic->msg_done);
> 
> -	i2c_parse_fw_timings(dev, &i2c_t, true);
> +	i2c_parse_fw_timings(dev, &riic->i2c_t, true);
> 
>  	pm_runtime_set_autosuspend_delay(dev, 0);
>  	pm_runtime_use_autosuspend(dev);
>  	pm_runtime_enable(dev);
> 
> -	ret = riic_init_hw(riic, &i2c_t);
> +	ret = riic_init_hw(riic);
>  	if (ret)
>  		goto out;
> 
> @@ -501,7 +502,7 @@ static int riic_i2c_probe(struct platform_device *pdev)
> 
>  	platform_set_drvdata(pdev, riic);
> 
> -	dev_info(dev, "registered with %dHz bus speed\n", i2c_t.bus_freq_hz);
> +	dev_info(dev, "registered with %dHz bus speed\n",
> +riic->i2c_t.bus_freq_hz);
>  	return 0;
> 
>  out:
> @@ -561,6 +562,48 @@ static const struct riic_of_data riic_rz_v2h_info = {
>  	},
>  };
> 
> +static int riic_i2c_suspend(struct device *dev) {
> +	struct riic_dev *riic = dev_get_drvdata(dev);
> +	int ret;
> +
> +	ret = pm_runtime_resume_and_get(dev);
> +	if (ret)
> +		return ret;
> +
> +	i2c_mark_adapter_suspended(&riic->adapter);
> +
> +	/* Disable output on SDA, SCL pins. */
> +	riic_clear_set_bit(riic, ICCR1_ICE, 0, RIIC_ICCR1);
> +
> +	pm_runtime_mark_last_busy(dev);
> +	pm_runtime_put_sync(dev);
> +
> +	return reset_control_assert(riic->rstc); }
> +
> +static int riic_i2c_resume(struct device *dev) {
> +	struct riic_dev *riic = dev_get_drvdata(dev);
> +	int ret;
> +
> +	ret = reset_control_deassert(riic->rstc);
> +	if (ret)
> +		return ret;
> +
> +	ret = riic_init_hw(riic);
> +	if (ret)
> +		return ret;

On error case we need to assert back??

Cheers,
Biju

> +
> +	i2c_mark_adapter_resumed(&riic->adapter);
> +
> +	return 0;
> +}
> +
> +static const struct dev_pm_ops riic_i2c_pm_ops = {
> +	SYSTEM_SLEEP_PM_OPS(riic_i2c_suspend, riic_i2c_resume) };
> +
>  static const struct of_device_id riic_i2c_dt_ids[] = {
>  	{ .compatible = "renesas,riic-rz", .data = &riic_rz_a_info },
>  	{ .compatible = "renesas,riic-r9a09g057", .data = &riic_rz_v2h_info }, @@ -573,6 +616,7 @@
> static struct platform_driver riic_i2c_driver = {
>  	.driver		= {
>  		.name	= "i2c-riic",
>  		.of_match_table = riic_i2c_dt_ids,
> +		.pm	= pm_ptr(&riic_i2c_pm_ops),
>  	},
>  };
> 
> --
> 2.39.2
> 

Re: [PATCH 06/12] i2c: riic: Add suspend/resume support

[claudiu beznea]

On 21.06.2024 15:30, Biju Das wrote:
> Hi Claudiu,
> 
> Thanks for the patch
> 
>> -----Original Message-----
>> From: Claudiu <claudiu.beznea@tuxon.dev>
>> Sent: Friday, June 21, 2024 12:23 PM
>> Subject: [PATCH 06/12] i2c: riic: Add suspend/resume support
>>
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Add suspend/resume support for the RIIC driver. This is necessary for the Renesas RZ/G3S SoC which
>> support suspend to deep sleep state where power to most of the SoC components is turned off. As a
>> result the I2C controller needs to be reconfigured after suspend/resume. For this, the reset line
>> was stored in the driver private data structure as well as i2c timings.
>> The reset line and I2C timings are necessary to re-initialize the controller after resume.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>> ---
>>  drivers/i2c/busses/i2c-riic.c | 66 +++++++++++++++++++++++++++++------
>>  1 file changed, 55 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index
>> 00fb09786e48..f9b9e92570d8 100644
>> --- a/drivers/i2c/busses/i2c-riic.c
>> +++ b/drivers/i2c/busses/i2c-riic.c
>> @@ -105,6 +105,8 @@ struct riic_dev {
>>  	struct completion msg_done;
>>  	struct i2c_adapter adapter;
>>  	struct clk *clk;
>> +	struct reset_control *rstc;
>> +	struct i2c_timings i2c_t;
>>  };
>>
>>  struct riic_irq_desc {
>> @@ -306,11 +308,12 @@ static const struct i2c_algorithm riic_algo = {
>>  	.functionality	= riic_func,
>>  };
>>
>> -static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
>> +static int riic_init_hw(struct riic_dev *riic)
>>  {
>>  	int ret;
>>  	unsigned long rate;
>>  	int total_ticks, cks, brl, brh;
>> +	struct i2c_timings *t = &riic->i2c_t;
>>  	struct device *dev = riic->adapter.dev.parent;
>>
>>  	if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) { @@ -429,8 +432,6 @@ static int
>> riic_i2c_probe(struct platform_device *pdev)
>>  	struct device *dev = &pdev->dev;
>>  	struct riic_dev *riic;
>>  	struct i2c_adapter *adap;
>> -	struct i2c_timings i2c_t;
>> -	struct reset_control *rstc;
>>  	int i, ret;
>>
>>  	riic = devm_kzalloc(dev, sizeof(*riic), GFP_KERNEL); @@ -447,16 +448,16 @@ static int
>> riic_i2c_probe(struct platform_device *pdev)
>>  		return PTR_ERR(riic->clk);
>>  	}
>>
>> -	rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
>> -	if (IS_ERR(rstc))
>> -		return dev_err_probe(dev, PTR_ERR(rstc),
>> +	riic->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
>> +	if (IS_ERR(riic->rstc))
>> +		return dev_err_probe(dev, PTR_ERR(riic->rstc),
>>  				     "Error: missing reset ctrl\n");
>>
>> -	ret = reset_control_deassert(rstc);
>> +	ret = reset_control_deassert(riic->rstc);
>>  	if (ret)
>>  		return ret;
>>
>> -	ret = devm_add_action_or_reset(dev, riic_reset_control_assert, rstc);
>> +	ret = devm_add_action_or_reset(dev, riic_reset_control_assert,
>> +riic->rstc);
>>  	if (ret)
>>  		return ret;
>>
>> @@ -485,13 +486,13 @@ static int riic_i2c_probe(struct platform_device *pdev)
>>
>>  	init_completion(&riic->msg_done);
>>
>> -	i2c_parse_fw_timings(dev, &i2c_t, true);
>> +	i2c_parse_fw_timings(dev, &riic->i2c_t, true);
>>
>>  	pm_runtime_set_autosuspend_delay(dev, 0);
>>  	pm_runtime_use_autosuspend(dev);
>>  	pm_runtime_enable(dev);
>>
>> -	ret = riic_init_hw(riic, &i2c_t);
>> +	ret = riic_init_hw(riic);
>>  	if (ret)
>>  		goto out;
>>
>> @@ -501,7 +502,7 @@ static int riic_i2c_probe(struct platform_device *pdev)
>>
>>  	platform_set_drvdata(pdev, riic);
>>
>> -	dev_info(dev, "registered with %dHz bus speed\n", i2c_t.bus_freq_hz);
>> +	dev_info(dev, "registered with %dHz bus speed\n",
>> +riic->i2c_t.bus_freq_hz);
>>  	return 0;
>>
>>  out:
>> @@ -561,6 +562,48 @@ static const struct riic_of_data riic_rz_v2h_info = {
>>  	},
>>  };
>>
>> +static int riic_i2c_suspend(struct device *dev) {
>> +	struct riic_dev *riic = dev_get_drvdata(dev);
>> +	int ret;
>> +
>> +	ret = pm_runtime_resume_and_get(dev);
>> +	if (ret)
>> +		return ret;
>> +
>> +	i2c_mark_adapter_suspended(&riic->adapter);
>> +
>> +	/* Disable output on SDA, SCL pins. */
>> +	riic_clear_set_bit(riic, ICCR1_ICE, 0, RIIC_ICCR1);
>> +
>> +	pm_runtime_mark_last_busy(dev);
>> +	pm_runtime_put_sync(dev);
>> +
>> +	return reset_control_assert(riic->rstc); }
>> +
>> +static int riic_i2c_resume(struct device *dev) {
>> +	struct riic_dev *riic = dev_get_drvdata(dev);
>> +	int ret;
>> +
>> +	ret = reset_control_deassert(riic->rstc);
>> +	if (ret)
>> +		return ret;
>> +
>> +	ret = riic_init_hw(riic);
>> +	if (ret)
>> +		return ret;
> 
> On error case we need to assert back??

Yes, it would be better as we cannot recover though other paths anymore, if
that happens.

> 
> Cheers,
> Biju
> 
>> +
>> +	i2c_mark_adapter_resumed(&riic->adapter);
>> +
>> +	return 0;
>> +}
>> +
>> +static const struct dev_pm_ops riic_i2c_pm_ops = {
>> +	SYSTEM_SLEEP_PM_OPS(riic_i2c_suspend, riic_i2c_resume) };
>> +
>>  static const struct of_device_id riic_i2c_dt_ids[] = {
>>  	{ .compatible = "renesas,riic-rz", .data = &riic_rz_a_info },
>>  	{ .compatible = "renesas,riic-r9a09g057", .data = &riic_rz_v2h_info }, @@ -573,6 +616,7 @@
>> static struct platform_driver riic_i2c_driver = {
>>  	.driver		= {
>>  		.name	= "i2c-riic",
>>  		.of_match_table = riic_i2c_dt_ids,
>> +		.pm	= pm_ptr(&riic_i2c_pm_ops),
>>  	},
>>  };
>>
>> --
>> 2.39.2
>>
> 

[PATCH 07/12] i2c: riic: Define individual arrays to describe the register offsets

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Define individual arrays to describe the register offsets. In this way
we can describe different IP variants that share the same register offsets
but have differences in other characteristics. Commit prepares for the
addition of fast mode plus.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/i2c/busses/i2c-riic.c | 58 +++++++++++++++++++----------------
 1 file changed, 31 insertions(+), 27 deletions(-)

diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
index f9b9e92570d8..46070f323810 100644
--- a/drivers/i2c/busses/i2c-riic.c
+++ b/drivers/i2c/busses/i2c-riic.c
@@ -91,7 +91,7 @@ enum riic_reg_list {
 };
 
 struct riic_of_data {
-	u8 regs[RIIC_REG_END];
+	const u8 *regs;
 };
 
 struct riic_dev {
@@ -530,36 +530,40 @@ static void riic_i2c_remove(struct platform_device *pdev)
 	pm_runtime_dont_use_autosuspend(dev);
 }
 
+static const u8 riic_rz_a_regs[RIIC_REG_END] = {
+	[RIIC_ICCR1] = 0x00,
+	[RIIC_ICCR2] = 0x04,
+	[RIIC_ICMR1] = 0x08,
+	[RIIC_ICMR3] = 0x10,
+	[RIIC_ICSER] = 0x18,
+	[RIIC_ICIER] = 0x1c,
+	[RIIC_ICSR2] = 0x24,
+	[RIIC_ICBRL] = 0x34,
+	[RIIC_ICBRH] = 0x38,
+	[RIIC_ICDRT] = 0x3c,
+	[RIIC_ICDRR] = 0x40,
+};
+
 static const struct riic_of_data riic_rz_a_info = {
-	.regs = {
-		[RIIC_ICCR1] = 0x00,
-		[RIIC_ICCR2] = 0x04,
-		[RIIC_ICMR1] = 0x08,
-		[RIIC_ICMR3] = 0x10,
-		[RIIC_ICSER] = 0x18,
-		[RIIC_ICIER] = 0x1c,
-		[RIIC_ICSR2] = 0x24,
-		[RIIC_ICBRL] = 0x34,
-		[RIIC_ICBRH] = 0x38,
-		[RIIC_ICDRT] = 0x3c,
-		[RIIC_ICDRR] = 0x40,
-	},
+	.regs = riic_rz_a_regs,
+};
+
+static const u8 riic_rz_v2h_regs[RIIC_REG_END] = {
+	[RIIC_ICCR1] = 0x00,
+	[RIIC_ICCR2] = 0x01,
+	[RIIC_ICMR1] = 0x02,
+	[RIIC_ICMR3] = 0x04,
+	[RIIC_ICSER] = 0x06,
+	[RIIC_ICIER] = 0x07,
+	[RIIC_ICSR2] = 0x09,
+	[RIIC_ICBRL] = 0x10,
+	[RIIC_ICBRH] = 0x11,
+	[RIIC_ICDRT] = 0x12,
+	[RIIC_ICDRR] = 0x13,
 };
 
 static const struct riic_of_data riic_rz_v2h_info = {
-	.regs = {
-		[RIIC_ICCR1] = 0x00,
-		[RIIC_ICCR2] = 0x01,
-		[RIIC_ICMR1] = 0x02,
-		[RIIC_ICMR3] = 0x04,
-		[RIIC_ICSER] = 0x06,
-		[RIIC_ICIER] = 0x07,
-		[RIIC_ICSR2] = 0x09,
-		[RIIC_ICBRL] = 0x10,
-		[RIIC_ICBRH] = 0x11,
-		[RIIC_ICDRT] = 0x12,
-		[RIIC_ICDRR] = 0x13,
-	},
+	.regs = riic_rz_v2h_regs,
 };
 
 static int riic_i2c_suspend(struct device *dev)
-- 
2.39.2

[PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is compatible with
the version available on Renesas RZ/V2H (R9A09G075). Most of the IP
variants that the RIIC driver is working with supports fast mode plus.
However, it happens that on the same SoC to have IP instatiations that
support fast mode plus as well as IP instantiation that doesn't support
it. For this, introduced the renesas,riic-no-fast-mode-plus property.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
index 91ecf17b7a81..c0964edbca69 100644
--- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
+++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
@@ -25,6 +25,10 @@ properties:
               - renesas,riic-r9a07g054  # RZ/V2L
           - const: renesas,riic-rz      # RZ/A or RZ/G2L
 
+      - items:
+          - const: renesas,riic-r9a08g045   # RZ/G3S
+          - const: renesas,riic-r9a09g057
+
       - const: renesas,riic-r9a09g057   # RZ/V2H(P)
 
   reg:
@@ -66,6 +70,10 @@ properties:
   resets:
     maxItems: 1
 
+  renesas,riic-no-fast-mode-plus:
+    description: specifies if fast mode plus is not supported
+    type: boolean
+
 required:
   - compatible
   - reg
-- 
2.39.2

RE: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support

[Biju Das]

Hi Claudiu,

> -----Original Message-----
> From: Claudiu <claudiu.beznea@tuxon.dev>
> Sent: Friday, June 21, 2024 12:23 PM
> Subject: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support
> 
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is compatible with the version available on
> Renesas RZ/V2H (R9A09G075). Most of the IP variants that the RIIC driver is working with supports
> fast mode plus.
> However, it happens that on the same SoC to have IP instatiations that support fast mode plus as
> well as IP instantiation that doesn't support it. For this, introduced the renesas,riic-no-fast-
> mode-plus property.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> index 91ecf17b7a81..c0964edbca69 100644
> --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> @@ -25,6 +25,10 @@ properties:
>                - renesas,riic-r9a07g054  # RZ/V2L
>            - const: renesas,riic-rz      # RZ/A or RZ/G2L
> 
> +      - items:
> +          - const: renesas,riic-r9a08g045   # RZ/G3S
> +          - const: renesas,riic-r9a09g057
> +
>        - const: renesas,riic-r9a09g057   # RZ/V2H(P)
> 
>    reg:
> @@ -66,6 +70,10 @@ properties:
>    resets:
>      maxItems: 1
> 
> +  renesas,riic-no-fast-mode-plus:
> +    description: specifies if fast mode plus is not supported
> +    type: Boolean

Can't this info, as part of device data?? Based on frequency and device data
is enough to derive this info??

Cheers,
Biju

> +
>  required:
>    - compatible
>    - reg
> --
> 2.39.2
> 

Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support

[claudiu beznea]

On 21.06.2024 15:34, Biju Das wrote:
> Hi Claudiu,
> 
>> -----Original Message-----
>> From: Claudiu <claudiu.beznea@tuxon.dev>
>> Sent: Friday, June 21, 2024 12:23 PM
>> Subject: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support
>>
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is compatible with the version available on
>> Renesas RZ/V2H (R9A09G075). Most of the IP variants that the RIIC driver is working with supports
>> fast mode plus.
>> However, it happens that on the same SoC to have IP instatiations that support fast mode plus as
>> well as IP instantiation that doesn't support it. For this, introduced the renesas,riic-no-fast-
>> mode-plus property.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>> ---
>>  Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 8 ++++++++
>>  1 file changed, 8 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>> b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>> index 91ecf17b7a81..c0964edbca69 100644
>> --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>> +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>> @@ -25,6 +25,10 @@ properties:
>>                - renesas,riic-r9a07g054  # RZ/V2L
>>            - const: renesas,riic-rz      # RZ/A or RZ/G2L
>>
>> +      - items:
>> +          - const: renesas,riic-r9a08g045   # RZ/G3S
>> +          - const: renesas,riic-r9a09g057
>> +
>>        - const: renesas,riic-r9a09g057   # RZ/V2H(P)
>>
>>    reg:
>> @@ -66,6 +70,10 @@ properties:
>>    resets:
>>      maxItems: 1
>>
>> +  renesas,riic-no-fast-mode-plus:
>> +    description: specifies if fast mode plus is not supported
>> +    type: Boolean
> 
> Can't this info, as part of device data?? Based on frequency and device data
> is enough to derive this info??

We can't rely completely on device data because on RZ/G3S we have 2 RIIC
channels that support fast mode plus and 2 that doesn't support it.

Thank you,
Claudiu Beznea

> 
> Cheers,
> Biju
> 
>> +
>>  required:
>>    - compatible
>>    - reg
>> --
>> 2.39.2
>>
> 

RE: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support

[Biju Das]

Hi claudiu,

> -----Original Message-----
> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> Sent: Friday, June 21, 2024 1:55 PM
> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support
> 
> 
> 
> On 21.06.2024 15:34, Biju Das wrote:
> > Hi Claudiu,
> >
> >> -----Original Message-----
> >> From: Claudiu <claudiu.beznea@tuxon.dev>
> >> Sent: Friday, June 21, 2024 12:23 PM
> >> Subject: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the
> >> R9A08G045 support
> >>
> >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>
> >> Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is compatible
> >> with the version available on Renesas RZ/V2H (R9A09G075). Most of the
> >> IP variants that the RIIC driver is working with supports fast mode plus.
> >> However, it happens that on the same SoC to have IP instatiations
> >> that support fast mode plus as well as IP instantiation that doesn't
> >> support it. For this, introduced the renesas,riic-no-fast- mode-plus property.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >> ---
> >>  Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 8 ++++++++
> >>  1 file changed, 8 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >> b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >> index 91ecf17b7a81..c0964edbca69 100644
> >> --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >> +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >> @@ -25,6 +25,10 @@ properties:
> >>                - renesas,riic-r9a07g054  # RZ/V2L
> >>            - const: renesas,riic-rz      # RZ/A or RZ/G2L
> >>
> >> +      - items:
> >> +          - const: renesas,riic-r9a08g045   # RZ/G3S
> >> +          - const: renesas,riic-r9a09g057
> >> +
> >>        - const: renesas,riic-r9a09g057   # RZ/V2H(P)
> >>
> >>    reg:
> >> @@ -66,6 +70,10 @@ properties:
> >>    resets:
> >>      maxItems: 1
> >>
> >> +  renesas,riic-no-fast-mode-plus:
> >> +    description: specifies if fast mode plus is not supported
> >> +    type: Boolean
> >
> > Can't this info, as part of device data?? Based on frequency and
> > device data is enough to derive this info??
> 
> We can't rely completely on device data because on RZ/G3S we have 2 RIIC channels that support fast
> mode plus and 2 that doesn't support it.

Can't array of bits for this channels won't help??
Based on the bit info, you have that details and check against frequency defined in DT.

Cheers,
Biju

Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support

[claudiu beznea]

On 21.06.2024 15:56, Biju Das wrote:
> 
> Hi claudiu,
> 
>> -----Original Message-----
>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>> Sent: Friday, June 21, 2024 1:55 PM
>> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support
>>
>>
>>
>> On 21.06.2024 15:34, Biju Das wrote:
>>> Hi Claudiu,
>>>
>>>> -----Original Message-----
>>>> From: Claudiu <claudiu.beznea@tuxon.dev>
>>>> Sent: Friday, June 21, 2024 12:23 PM
>>>> Subject: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the
>>>> R9A08G045 support
>>>>
>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>
>>>> Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is compatible
>>>> with the version available on Renesas RZ/V2H (R9A09G075). Most of the
>>>> IP variants that the RIIC driver is working with supports fast mode plus.
>>>> However, it happens that on the same SoC to have IP instatiations
>>>> that support fast mode plus as well as IP instantiation that doesn't
>>>> support it. For this, introduced the renesas,riic-no-fast- mode-plus property.
>>>>
>>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>> ---
>>>>  Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 8 ++++++++
>>>>  1 file changed, 8 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>>>> b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>>>> index 91ecf17b7a81..c0964edbca69 100644
>>>> --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>>>> +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>>>> @@ -25,6 +25,10 @@ properties:
>>>>                - renesas,riic-r9a07g054  # RZ/V2L
>>>>            - const: renesas,riic-rz      # RZ/A or RZ/G2L
>>>>
>>>> +      - items:
>>>> +          - const: renesas,riic-r9a08g045   # RZ/G3S
>>>> +          - const: renesas,riic-r9a09g057
>>>> +
>>>>        - const: renesas,riic-r9a09g057   # RZ/V2H(P)
>>>>
>>>>    reg:
>>>> @@ -66,6 +70,10 @@ properties:
>>>>    resets:
>>>>      maxItems: 1
>>>>
>>>> +  renesas,riic-no-fast-mode-plus:
>>>> +    description: specifies if fast mode plus is not supported
>>>> +    type: Boolean
>>>
>>> Can't this info, as part of device data?? Based on frequency and
>>> device data is enough to derive this info??
>>
>> We can't rely completely on device data because on RZ/G3S we have 2 RIIC channels that support fast
>> mode plus and 2 that doesn't support it.
> 
> Can't array of bits for this channels won't help??

Can you give an example? I'm not sure I understand how you would prefer me
to use the array of bits.

Thank you,
Claudiu Beznea

> Based on the bit info, you have that details and check against frequency defined in DT.
> 
> Cheers,
> Biju

RE: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support

[Biju Das]

> -----Original Message-----
> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> Sent: Friday, June 21, 2024 2:06 PM
 Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support
> 
> 
> 
> On 21.06.2024 15:56, Biju Das wrote:
> >
> > Hi claudiu,
> >
> >> -----Original Message-----
> >> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >> Sent: Friday, June 21, 2024 1:55 PM
> >> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document
> >> the R9A08G045 support
> >>
> >>
> >>
> >> On 21.06.2024 15:34, Biju Das wrote:
> >>> Hi Claudiu,
> >>>
> >>>> -----Original Message-----
> >>>> From: Claudiu <claudiu.beznea@tuxon.dev>
> >>>> Sent: Friday, June 21, 2024 12:23 PM
> >>>> Subject: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the
> >>>> R9A08G045 support
> >>>>
> >>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>>
> >>>> Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is compatible
> >>>> with the version available on Renesas RZ/V2H (R9A09G075). Most of
> >>>> the IP variants that the RIIC driver is working with supports fast mode plus.
> >>>> However, it happens that on the same SoC to have IP instatiations
> >>>> that support fast mode plus as well as IP instantiation that
> >>>> doesn't support it. For this, introduced the renesas,riic-no-fast- mode-plus property.
> >>>>
> >>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>> ---
> >>>>  Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 8
> >>>> ++++++++
> >>>>  1 file changed, 8 insertions(+)
> >>>>
> >>>> diff --git
> >>>> a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>> b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>> index 91ecf17b7a81..c0964edbca69 100644
> >>>> --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>> +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>> @@ -25,6 +25,10 @@ properties:
> >>>>                - renesas,riic-r9a07g054  # RZ/V2L
> >>>>            - const: renesas,riic-rz      # RZ/A or RZ/G2L
> >>>>
> >>>> +      - items:
> >>>> +          - const: renesas,riic-r9a08g045   # RZ/G3S
> >>>> +          - const: renesas,riic-r9a09g057
> >>>> +
> >>>>        - const: renesas,riic-r9a09g057   # RZ/V2H(P)
> >>>>
> >>>>    reg:
> >>>> @@ -66,6 +70,10 @@ properties:
> >>>>    resets:
> >>>>      maxItems: 1
> >>>>
> >>>> +  renesas,riic-no-fast-mode-plus:
> >>>> +    description: specifies if fast mode plus is not supported
> >>>> +    type: Boolean
> >>>
> >>> Can't this info, as part of device data?? Based on frequency and
> >>> device data is enough to derive this info??
> >>
> >> We can't rely completely on device data because on RZ/G3S we have 2
> >> RIIC channels that support fast mode plus and 2 that doesn't support it.
> >
> > Can't array of bits for this channels won't help??
> 
> Can you give an example? I'm not sure I understand how you would prefer me to use the array of
> bits.

struct riic_of_data {
	u8 regs[RIIC_REG_END];
	u16 fast_mode_info info; /* 1 means fast mode plus supported, starting with channel 0*/
};

.info = 0x3, means channel 0 and 1 has fast mode plus supported
.info = 0x0, none of the channel supported fast mode plus.

Cheers,
Biju

Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support

[claudiu beznea]

On 21.06.2024 16:10, Biju Das wrote:
> 
> 
>> -----Original Message-----
>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>> Sent: Friday, June 21, 2024 2:06 PM
>  Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support
>>
>>
>>
>> On 21.06.2024 15:56, Biju Das wrote:
>>>
>>> Hi claudiu,
>>>
>>>> -----Original Message-----
>>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>>>> Sent: Friday, June 21, 2024 1:55 PM
>>>> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document
>>>> the R9A08G045 support
>>>>
>>>>
>>>>
>>>> On 21.06.2024 15:34, Biju Das wrote:
>>>>> Hi Claudiu,
>>>>>
>>>>>> -----Original Message-----
>>>>>> From: Claudiu <claudiu.beznea@tuxon.dev>
>>>>>> Sent: Friday, June 21, 2024 12:23 PM
>>>>>> Subject: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the
>>>>>> R9A08G045 support
>>>>>>
>>>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>>>
>>>>>> Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is compatible
>>>>>> with the version available on Renesas RZ/V2H (R9A09G075). Most of
>>>>>> the IP variants that the RIIC driver is working with supports fast mode plus.
>>>>>> However, it happens that on the same SoC to have IP instatiations
>>>>>> that support fast mode plus as well as IP instantiation that
>>>>>> doesn't support it. For this, introduced the renesas,riic-no-fast- mode-plus property.
>>>>>>
>>>>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>>> ---
>>>>>>  Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 8
>>>>>> ++++++++
>>>>>>  1 file changed, 8 insertions(+)
>>>>>>
>>>>>> diff --git
>>>>>> a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>>>>>> b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>>>>>> index 91ecf17b7a81..c0964edbca69 100644
>>>>>> --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>>>>>> +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>>>>>> @@ -25,6 +25,10 @@ properties:
>>>>>>                - renesas,riic-r9a07g054  # RZ/V2L
>>>>>>            - const: renesas,riic-rz      # RZ/A or RZ/G2L
>>>>>>
>>>>>> +      - items:
>>>>>> +          - const: renesas,riic-r9a08g045   # RZ/G3S
>>>>>> +          - const: renesas,riic-r9a09g057
>>>>>> +
>>>>>>        - const: renesas,riic-r9a09g057   # RZ/V2H(P)
>>>>>>
>>>>>>    reg:
>>>>>> @@ -66,6 +70,10 @@ properties:
>>>>>>    resets:
>>>>>>      maxItems: 1
>>>>>>
>>>>>> +  renesas,riic-no-fast-mode-plus:
>>>>>> +    description: specifies if fast mode plus is not supported
>>>>>> +    type: Boolean
>>>>>
>>>>> Can't this info, as part of device data?? Based on frequency and
>>>>> device data is enough to derive this info??
>>>>
>>>> We can't rely completely on device data because on RZ/G3S we have 2
>>>> RIIC channels that support fast mode plus and 2 that doesn't support it.
>>>
>>> Can't array of bits for this channels won't help??
>>
>> Can you give an example? I'm not sure I understand how you would prefer me to use the array of
>> bits.
> 
> struct riic_of_data {
> 	u8 regs[RIIC_REG_END];
> 	u16 fast_mode_info info; /* 1 means fast mode plus supported, starting with channel 0*/
> };
> 
> .info = 0x3, means channel 0 and 1 has fast mode plus supported
> .info = 0x0, none of the channel supported fast mode plus.

If I understand the proposal correctly, a match b/w struct
riic_of_data::info bit + frequency and the nodes in device tree is still
needed, right? As the RZ/G3S RIIC channels are using the same compatible.
W/o a match how I cannot detect in the driver who is, e.g., channel 1 that
supports FMP w/o hardcoding some RIIC channel data in the driver (e.g. RIIC
channel address)?

Also, for future SoCs that will suffer the same symptom but for different
channels (and channels with different addresses) the driver will have to be
adapted to match b/w the channel bit in struct riic_of_data::info and
channel node from DT.

> 
> Cheers,
> Biju

RE: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support

[Biju Das]

Hi Claudiu,

> -----Original Message-----
> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> Sent: Friday, June 21, 2024 2:30 PM
> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support
> 
> 
> 
> On 21.06.2024 16:10, Biju Das wrote:
> >
> >
> >> -----Original Message-----
> >> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >> Sent: Friday, June 21, 2024 2:06 PM
> >  Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document
> > the R9A08G045 support
> >>
> >>
> >>
> >> On 21.06.2024 15:56, Biju Das wrote:
> >>>
> >>> Hi claudiu,
> >>>
> >>>> -----Original Message-----
> >>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >>>> Sent: Friday, June 21, 2024 1:55 PM
> >>>> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document
> >>>> the R9A08G045 support
> >>>>
> >>>>
> >>>>
> >>>> On 21.06.2024 15:34, Biju Das wrote:
> >>>>> Hi Claudiu,
> >>>>>
> >>>>>> -----Original Message-----
> >>>>>> From: Claudiu <claudiu.beznea@tuxon.dev>
> >>>>>> Sent: Friday, June 21, 2024 12:23 PM
> >>>>>> Subject: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document
> >>>>>> the
> >>>>>> R9A08G045 support
> >>>>>>
> >>>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>>>>
> >>>>>> Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is
> >>>>>> compatible with the version available on Renesas RZ/V2H
> >>>>>> (R9A09G075). Most of the IP variants that the RIIC driver is working with supports fast mode
> plus.
> >>>>>> However, it happens that on the same SoC to have IP instatiations
> >>>>>> that support fast mode plus as well as IP instantiation that
> >>>>>> doesn't support it. For this, introduced the renesas,riic-no-fast- mode-plus property.
> >>>>>>
> >>>>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>>>> ---
> >>>>>>  Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 8
> >>>>>> ++++++++
> >>>>>>  1 file changed, 8 insertions(+)
> >>>>>>
> >>>>>> diff --git
> >>>>>> a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>>>> b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>>>> index 91ecf17b7a81..c0964edbca69 100644
> >>>>>> --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>>>> +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>>>> @@ -25,6 +25,10 @@ properties:
> >>>>>>                - renesas,riic-r9a07g054  # RZ/V2L
> >>>>>>            - const: renesas,riic-rz      # RZ/A or RZ/G2L
> >>>>>>
> >>>>>> +      - items:
> >>>>>> +          - const: renesas,riic-r9a08g045   # RZ/G3S
> >>>>>> +          - const: renesas,riic-r9a09g057
> >>>>>> +
> >>>>>>        - const: renesas,riic-r9a09g057   # RZ/V2H(P)
> >>>>>>
> >>>>>>    reg:
> >>>>>> @@ -66,6 +70,10 @@ properties:
> >>>>>>    resets:
> >>>>>>      maxItems: 1
> >>>>>>
> >>>>>> +  renesas,riic-no-fast-mode-plus:
> >>>>>> +    description: specifies if fast mode plus is not supported
> >>>>>> +    type: Boolean
> >>>>>
> >>>>> Can't this info, as part of device data?? Based on frequency and
> >>>>> device data is enough to derive this info??
> >>>>
> >>>> We can't rely completely on device data because on RZ/G3S we have 2
> >>>> RIIC channels that support fast mode plus and 2 that doesn't support it.
> >>>
> >>> Can't array of bits for this channels won't help??
> >>
> >> Can you give an example? I'm not sure I understand how you would
> >> prefer me to use the array of bits.
> >
> > struct riic_of_data {
> > 	u8 regs[RIIC_REG_END];
> > 	u16 fast_mode_info info; /* 1 means fast mode plus supported,
> > starting with channel 0*/ };
> >
> > .info = 0x3, means channel 0 and 1 has fast mode plus supported .info
> > = 0x0, none of the channel supported fast mode plus.
> 
> If I understand the proposal correctly, a match b/w struct riic_of_data::info bit + frequency and
> the nodes in device tree is still needed, right? As the RZ/G3S RIIC channels are using the same
> compatible.
> W/o a match how I cannot detect in the driver who is, e.g., channel 1 that supports FMP w/o
> hardcoding some RIIC channel data in the driver (e.g. RIIC channel address)?

bit array gives the capability info on various channels.

If someone define fast_mode_plus frequency in DT node and channel is not fast_mode_plus(from the capability info)
then you should return error.

Here you need to use SoC specific compatible as each SoC has different capabilities.

Cheers,
Biju


> 
> Also, for future SoCs that will suffer the same symptom but for different channels (and channels
> with different addresses) the driver will have to be adapted to match b/w the channel bit in struct
> riic_of_data::info and channel node from DT.
> 
> >
> > Cheers,
> > Biju

Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support

[claudiu beznea]

On 21.06.2024 17:06, Biju Das wrote:
> Hi Claudiu,
> 
>> -----Original Message-----
>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>> Sent: Friday, June 21, 2024 2:30 PM
>> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support
>>
>>
>>
>> On 21.06.2024 16:10, Biju Das wrote:
>>>
>>>
>>>> -----Original Message-----
>>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>>>> Sent: Friday, June 21, 2024 2:06 PM
>>>  Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document
>>> the R9A08G045 support
>>>>
>>>>
>>>>
>>>> On 21.06.2024 15:56, Biju Das wrote:
>>>>>
>>>>> Hi claudiu,
>>>>>
>>>>>> -----Original Message-----
>>>>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>>>>>> Sent: Friday, June 21, 2024 1:55 PM
>>>>>> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document
>>>>>> the R9A08G045 support
>>>>>>
>>>>>>
>>>>>>
>>>>>> On 21.06.2024 15:34, Biju Das wrote:
>>>>>>> Hi Claudiu,
>>>>>>>
>>>>>>>> -----Original Message-----
>>>>>>>> From: Claudiu <claudiu.beznea@tuxon.dev>
>>>>>>>> Sent: Friday, June 21, 2024 12:23 PM
>>>>>>>> Subject: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document
>>>>>>>> the
>>>>>>>> R9A08G045 support
>>>>>>>>
>>>>>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>>>>>
>>>>>>>> Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is
>>>>>>>> compatible with the version available on Renesas RZ/V2H
>>>>>>>> (R9A09G075). Most of the IP variants that the RIIC driver is working with supports fast mode
>> plus.
>>>>>>>> However, it happens that on the same SoC to have IP instatiations
>>>>>>>> that support fast mode plus as well as IP instantiation that
>>>>>>>> doesn't support it. For this, introduced the renesas,riic-no-fast- mode-plus property.
>>>>>>>>
>>>>>>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>>>>> ---
>>>>>>>>  Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 8
>>>>>>>> ++++++++
>>>>>>>>  1 file changed, 8 insertions(+)
>>>>>>>>
>>>>>>>> diff --git
>>>>>>>> a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>>>>>>>> b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>>>>>>>> index 91ecf17b7a81..c0964edbca69 100644
>>>>>>>> --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>>>>>>>> +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>>>>>>>> @@ -25,6 +25,10 @@ properties:
>>>>>>>>                - renesas,riic-r9a07g054  # RZ/V2L
>>>>>>>>            - const: renesas,riic-rz      # RZ/A or RZ/G2L
>>>>>>>>
>>>>>>>> +      - items:
>>>>>>>> +          - const: renesas,riic-r9a08g045   # RZ/G3S
>>>>>>>> +          - const: renesas,riic-r9a09g057
>>>>>>>> +
>>>>>>>>        - const: renesas,riic-r9a09g057   # RZ/V2H(P)
>>>>>>>>
>>>>>>>>    reg:
>>>>>>>> @@ -66,6 +70,10 @@ properties:
>>>>>>>>    resets:
>>>>>>>>      maxItems: 1
>>>>>>>>
>>>>>>>> +  renesas,riic-no-fast-mode-plus:
>>>>>>>> +    description: specifies if fast mode plus is not supported
>>>>>>>> +    type: Boolean
>>>>>>>
>>>>>>> Can't this info, as part of device data?? Based on frequency and
>>>>>>> device data is enough to derive this info??
>>>>>>
>>>>>> We can't rely completely on device data because on RZ/G3S we have 2
>>>>>> RIIC channels that support fast mode plus and 2 that doesn't support it.
>>>>>
>>>>> Can't array of bits for this channels won't help??
>>>>
>>>> Can you give an example? I'm not sure I understand how you would
>>>> prefer me to use the array of bits.
>>>
>>> struct riic_of_data {
>>> 	u8 regs[RIIC_REG_END];
>>> 	u16 fast_mode_info info; /* 1 means fast mode plus supported,
>>> starting with channel 0*/ };
>>>
>>> .info = 0x3, means channel 0 and 1 has fast mode plus supported .info
>>> = 0x0, none of the channel supported fast mode plus.
>>
>> If I understand the proposal correctly, a match b/w struct riic_of_data::info bit + frequency and
>> the nodes in device tree is still needed, right? As the RZ/G3S RIIC channels are using the same
>> compatible.
>> W/o a match how I cannot detect in the driver who is, e.g., channel 1 that supports FMP w/o
>> hardcoding some RIIC channel data in the driver (e.g. RIIC channel address)?
> 
> bit array gives the capability info on various channels.
> 
> If someone define fast_mode_plus frequency in DT node and channel is not fast_mode_plus(from the capability info)
> then you should return error.
> 
> Here you need to use SoC specific compatible as each SoC has different capabilities.

And I would add, as it is in this case: there are multiple instantiation of
the RIIC in RZ/G3S SoC. RIIC 0 and 1 supports FMP, RIIC 2 and 3 does not.

For all RIICs (0, 1, 2, 3) we use the same compatible (as all are part of
the same SoC). How to do the match b/w DT RIIC channel and driver with the
solution you propose w/o hardcoding some RIIC channel data in the driver?

> 
> Cheers,
> Biju
> 
> 
>>
>> Also, for future SoCs that will suffer the same symptom but for different channels (and channels
>> with different addresses) the driver will have to be adapted to match b/w the channel bit in struct
>> riic_of_data::info and channel node from DT.
>>
>>>
>>> Cheers,
>>> Biju

RE: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support

[Biju Das]

> -----Original Message-----
> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> Sent: Friday, June 21, 2024 3:31 PM
> To: Biju Das <biju.das.jz@bp.renesas.com>; Chris Brandt <Chris.Brandt@renesas.com>;
> andi.shyti@kernel.org; robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> geert+renesas@glider.be; magnus.damm@gmail.com; mturquette@baylibre.com; sboyd@kernel.org;
> p.zabel@pengutronix.de; wsa+renesas@sang-engineering.com
> Cc: linux-renesas-soc@vger.kernel.org; linux-i2c@vger.kernel.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux-clk@vger.kernel.org; Claudiu Beznea
> <claudiu.beznea.uj@bp.renesas.com>
> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support
> 
> 
> 
> On 21.06.2024 17:06, Biju Das wrote:
> > Hi Claudiu,
> >
> >> -----Original Message-----
> >> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >> Sent: Friday, June 21, 2024 2:30 PM
> >> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document
> >> the R9A08G045 support
> >>
> >>
> >>
> >> On 21.06.2024 16:10, Biju Das wrote:
> >>>
> >>>
> >>>> -----Original Message-----
> >>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >>>> Sent: Friday, June 21, 2024 2:06 PM
> >>>  Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document
> >>> the R9A08G045 support
> >>>>
> >>>>
> >>>>
> >>>> On 21.06.2024 15:56, Biju Das wrote:
> >>>>>
> >>>>> Hi claudiu,
> >>>>>
> >>>>>> -----Original Message-----
> >>>>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >>>>>> Sent: Friday, June 21, 2024 1:55 PM
> >>>>>> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic:
> >>>>>> Document the R9A08G045 support
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>> On 21.06.2024 15:34, Biju Das wrote:
> >>>>>>> Hi Claudiu,
> >>>>>>>
> >>>>>>>> -----Original Message-----
> >>>>>>>> From: Claudiu <claudiu.beznea@tuxon.dev>
> >>>>>>>> Sent: Friday, June 21, 2024 12:23 PM
> >>>>>>>> Subject: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document
> >>>>>>>> the
> >>>>>>>> R9A08G045 support
> >>>>>>>>
> >>>>>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>>>>>>
> >>>>>>>> Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is
> >>>>>>>> compatible with the version available on Renesas RZ/V2H
> >>>>>>>> (R9A09G075). Most of the IP variants that the RIIC driver is
> >>>>>>>> working with supports fast mode
> >> plus.
> >>>>>>>> However, it happens that on the same SoC to have IP
> >>>>>>>> instatiations that support fast mode plus as well as IP
> >>>>>>>> instantiation that doesn't support it. For this, introduced the renesas,riic-no-fast-
> mode-plus property.
> >>>>>>>>
> >>>>>>>> Signed-off-by: Claudiu Beznea
> >>>>>>>> <claudiu.beznea.uj@bp.renesas.com>
> >>>>>>>> ---
> >>>>>>>>  Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 8
> >>>>>>>> ++++++++
> >>>>>>>>  1 file changed, 8 insertions(+)
> >>>>>>>>
> >>>>>>>> diff --git
> >>>>>>>> a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>>>>>> b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>>>>>> index 91ecf17b7a81..c0964edbca69 100644
> >>>>>>>> --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>>>>>> +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>>>>>> @@ -25,6 +25,10 @@ properties:
> >>>>>>>>                - renesas,riic-r9a07g054  # RZ/V2L
> >>>>>>>>            - const: renesas,riic-rz      # RZ/A or RZ/G2L
> >>>>>>>>
> >>>>>>>> +      - items:
> >>>>>>>> +          - const: renesas,riic-r9a08g045   # RZ/G3S
> >>>>>>>> +          - const: renesas,riic-r9a09g057
> >>>>>>>> +
> >>>>>>>>        - const: renesas,riic-r9a09g057   # RZ/V2H(P)
> >>>>>>>>
> >>>>>>>>    reg:
> >>>>>>>> @@ -66,6 +70,10 @@ properties:
> >>>>>>>>    resets:
> >>>>>>>>      maxItems: 1
> >>>>>>>>
> >>>>>>>> +  renesas,riic-no-fast-mode-plus:
> >>>>>>>> +    description: specifies if fast mode plus is not supported
> >>>>>>>> +    type: Boolean
> >>>>>>>
> >>>>>>> Can't this info, as part of device data?? Based on frequency and
> >>>>>>> device data is enough to derive this info??
> >>>>>>
> >>>>>> We can't rely completely on device data because on RZ/G3S we have
> >>>>>> 2 RIIC channels that support fast mode plus and 2 that doesn't support it.
> >>>>>
> >>>>> Can't array of bits for this channels won't help??
> >>>>
> >>>> Can you give an example? I'm not sure I understand how you would
> >>>> prefer me to use the array of bits.
> >>>
> >>> struct riic_of_data {
> >>> 	u8 regs[RIIC_REG_END];
> >>> 	u16 fast_mode_info info; /* 1 means fast mode plus supported,
> >>> starting with channel 0*/ };
> >>>
> >>> .info = 0x3, means channel 0 and 1 has fast mode plus supported
> >>> .info = 0x0, none of the channel supported fast mode plus.
> >>
> >> If I understand the proposal correctly, a match b/w struct
> >> riic_of_data::info bit + frequency and the nodes in device tree is
> >> still needed, right? As the RZ/G3S RIIC channels are using the same compatible.
> >> W/o a match how I cannot detect in the driver who is, e.g., channel 1
> >> that supports FMP w/o hardcoding some RIIC channel data in the driver (e.g. RIIC channel
> address)?
> >
> > bit array gives the capability info on various channels.
> >
> > If someone define fast_mode_plus frequency in DT node and channel is
> > not fast_mode_plus(from the capability info) then you should return error.
> >
> > Here you need to use SoC specific compatible as each SoC has different capabilities.
> 
> And I would add, as it is in this case: there are multiple instantiation of the RIIC in RZ/G3S SoC.
> RIIC 0 and 1 supports FMP, RIIC 2 and 3 does not.
> 
> For all RIICs (0, 1, 2, 3) we use the same compatible (as all are part of the same SoC). How to do
> the match b/w DT RIIC channel and driver with the solution you propose w/o hardcoding some RIIC
> channel data in the driver?

.info =0x3, so you know from the capability, for this soc, bus 0 and 1 supports FMP.

Cheers,
Biju


> 
> >
> > Cheers,
> > Biju
> >
> >
> >>
> >> Also, for future SoCs that will suffer the same symptom but for
> >> different channels (and channels with different addresses) the driver
> >> will have to be adapted to match b/w the channel bit in struct riic_of_data::info and channel
> node from DT.
> >>
> >>>
> >>> Cheers,
> >>> Biju

Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support

[claudiu beznea]

On 21.06.2024 17:37, Biju Das wrote:
> 
> 
>> -----Original Message-----
>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>> Sent: Friday, June 21, 2024 3:31 PM
>> To: Biju Das <biju.das.jz@bp.renesas.com>; Chris Brandt <Chris.Brandt@renesas.com>;
>> andi.shyti@kernel.org; robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
>> geert+renesas@glider.be; magnus.damm@gmail.com; mturquette@baylibre.com; sboyd@kernel.org;
>> p.zabel@pengutronix.de; wsa+renesas@sang-engineering.com
>> Cc: linux-renesas-soc@vger.kernel.org; linux-i2c@vger.kernel.org; devicetree@vger.kernel.org;
>> linux-kernel@vger.kernel.org; linux-clk@vger.kernel.org; Claudiu Beznea
>> <claudiu.beznea.uj@bp.renesas.com>
>> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support
>>
>>
>>
>> On 21.06.2024 17:06, Biju Das wrote:
>>> Hi Claudiu,
>>>
>>>> -----Original Message-----
>>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>>>> Sent: Friday, June 21, 2024 2:30 PM
>>>> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document
>>>> the R9A08G045 support
>>>>
>>>>
>>>>
>>>> On 21.06.2024 16:10, Biju Das wrote:
>>>>>
>>>>>
>>>>>> -----Original Message-----
>>>>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>>>>>> Sent: Friday, June 21, 2024 2:06 PM
>>>>>  Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document
>>>>> the R9A08G045 support
>>>>>>
>>>>>>
>>>>>>
>>>>>> On 21.06.2024 15:56, Biju Das wrote:
>>>>>>>
>>>>>>> Hi claudiu,
>>>>>>>
>>>>>>>> -----Original Message-----
>>>>>>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>>>>>>>> Sent: Friday, June 21, 2024 1:55 PM
>>>>>>>> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic:
>>>>>>>> Document the R9A08G045 support
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> On 21.06.2024 15:34, Biju Das wrote:
>>>>>>>>> Hi Claudiu,
>>>>>>>>>
>>>>>>>>>> -----Original Message-----
>>>>>>>>>> From: Claudiu <claudiu.beznea@tuxon.dev>
>>>>>>>>>> Sent: Friday, June 21, 2024 12:23 PM
>>>>>>>>>> Subject: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document
>>>>>>>>>> the
>>>>>>>>>> R9A08G045 support
>>>>>>>>>>
>>>>>>>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>>>>>>>
>>>>>>>>>> Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is
>>>>>>>>>> compatible with the version available on Renesas RZ/V2H
>>>>>>>>>> (R9A09G075). Most of the IP variants that the RIIC driver is
>>>>>>>>>> working with supports fast mode
>>>> plus.
>>>>>>>>>> However, it happens that on the same SoC to have IP
>>>>>>>>>> instatiations that support fast mode plus as well as IP
>>>>>>>>>> instantiation that doesn't support it. For this, introduced the renesas,riic-no-fast-
>> mode-plus property.
>>>>>>>>>>
>>>>>>>>>> Signed-off-by: Claudiu Beznea
>>>>>>>>>> <claudiu.beznea.uj@bp.renesas.com>
>>>>>>>>>> ---
>>>>>>>>>>  Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 8
>>>>>>>>>> ++++++++
>>>>>>>>>>  1 file changed, 8 insertions(+)
>>>>>>>>>>
>>>>>>>>>> diff --git
>>>>>>>>>> a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>>>>>>>>>> b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>>>>>>>>>> index 91ecf17b7a81..c0964edbca69 100644
>>>>>>>>>> --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>>>>>>>>>> +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>>>>>>>>>> @@ -25,6 +25,10 @@ properties:
>>>>>>>>>>                - renesas,riic-r9a07g054  # RZ/V2L
>>>>>>>>>>            - const: renesas,riic-rz      # RZ/A or RZ/G2L
>>>>>>>>>>
>>>>>>>>>> +      - items:
>>>>>>>>>> +          - const: renesas,riic-r9a08g045   # RZ/G3S
>>>>>>>>>> +          - const: renesas,riic-r9a09g057
>>>>>>>>>> +
>>>>>>>>>>        - const: renesas,riic-r9a09g057   # RZ/V2H(P)
>>>>>>>>>>
>>>>>>>>>>    reg:
>>>>>>>>>> @@ -66,6 +70,10 @@ properties:
>>>>>>>>>>    resets:
>>>>>>>>>>      maxItems: 1
>>>>>>>>>>
>>>>>>>>>> +  renesas,riic-no-fast-mode-plus:
>>>>>>>>>> +    description: specifies if fast mode plus is not supported
>>>>>>>>>> +    type: Boolean
>>>>>>>>>
>>>>>>>>> Can't this info, as part of device data?? Based on frequency and
>>>>>>>>> device data is enough to derive this info??
>>>>>>>>
>>>>>>>> We can't rely completely on device data because on RZ/G3S we have
>>>>>>>> 2 RIIC channels that support fast mode plus and 2 that doesn't support it.
>>>>>>>
>>>>>>> Can't array of bits for this channels won't help??
>>>>>>
>>>>>> Can you give an example? I'm not sure I understand how you would
>>>>>> prefer me to use the array of bits.
>>>>>
>>>>> struct riic_of_data {
>>>>> 	u8 regs[RIIC_REG_END];
>>>>> 	u16 fast_mode_info info; /* 1 means fast mode plus supported,
>>>>> starting with channel 0*/ };
>>>>>
>>>>> .info = 0x3, means channel 0 and 1 has fast mode plus supported
>>>>> .info = 0x0, none of the channel supported fast mode plus.
>>>>
>>>> If I understand the proposal correctly, a match b/w struct
>>>> riic_of_data::info bit + frequency and the nodes in device tree is
>>>> still needed, right? As the RZ/G3S RIIC channels are using the same compatible.
>>>> W/o a match how I cannot detect in the driver who is, e.g., channel 1
>>>> that supports FMP w/o hardcoding some RIIC channel data in the driver (e.g. RIIC channel
>> address)?
>>>
>>> bit array gives the capability info on various channels.
>>>
>>> If someone define fast_mode_plus frequency in DT node and channel is
>>> not fast_mode_plus(from the capability info) then you should return error.
>>>
>>> Here you need to use SoC specific compatible as each SoC has different capabilities.
>>
>> And I would add, as it is in this case: there are multiple instantiation of the RIIC in RZ/G3S SoC.
>> RIIC 0 and 1 supports FMP, RIIC 2 and 3 does not.
>>
>> For all RIICs (0, 1, 2, 3) we use the same compatible (as all are part of the same SoC). How to do
>> the match b/w DT RIIC channel and driver with the solution you propose w/o hardcoding some RIIC
>> channel data in the driver?
> 
> .info =0x3, so you know from the capability, for this soc, bus 0 and 1 supports FMP.

I understand this part. What I don't understand is: when probing the driver
for, e.g., bus 0, how do I know I probe the driver for bus 0? compatible is
the same for all buses.

> 
> Cheers,
> Biju
> 
> 
>>
>>>
>>> Cheers,
>>> Biju
>>>
>>>
>>>>
>>>> Also, for future SoCs that will suffer the same symptom but for
>>>> different channels (and channels with different addresses) the driver
>>>> will have to be adapted to match b/w the channel bit in struct riic_of_data::info and channel
>> node from DT.
>>>>
>>>>>
>>>>> Cheers,
>>>>> Biju

RE: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support

[Biju Das]

> -----Original Message-----
> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> Sent: Friday, June 21, 2024 3:59 PM
> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support
> 
> 
> 
> On 21.06.2024 17:37, Biju Das wrote:
> >
> >
> >> -----Original Message-----
> >> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >> Sent: Friday, June 21, 2024 3:31 PM
> >> To: Biju Das <biju.das.jz@bp.renesas.com>; Chris Brandt
> >> <Chris.Brandt@renesas.com>; andi.shyti@kernel.org; robh@kernel.org;
> >> krzk+dt@kernel.org; conor+dt@kernel.org;
> >> geert+renesas@glider.be; magnus.damm@gmail.com;
> >> geert+mturquette@baylibre.com; sboyd@kernel.org;
> >> p.zabel@pengutronix.de; wsa+renesas@sang-engineering.com
> >> Cc: linux-renesas-soc@vger.kernel.org; linux-i2c@vger.kernel.org;
> >> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> >> linux-clk@vger.kernel.org; Claudiu Beznea
> >> <claudiu.beznea.uj@bp.renesas.com>
> >> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document
> >> the R9A08G045 support
> >>
> >>
> >>
> >> On 21.06.2024 17:06, Biju Das wrote:
> >>> Hi Claudiu,
> >>>
> >>>> -----Original Message-----
> >>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >>>> Sent: Friday, June 21, 2024 2:30 PM
> >>>> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document
> >>>> the R9A08G045 support
> >>>>
> >>>>
> >>>>
> >>>> On 21.06.2024 16:10, Biju Das wrote:
> >>>>>
> >>>>>
> >>>>>> -----Original Message-----
> >>>>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >>>>>> Sent: Friday, June 21, 2024 2:06 PM
> >>>>>  Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic:
> >>>>> Document the R9A08G045 support
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>> On 21.06.2024 15:56, Biju Das wrote:
> >>>>>>>
> >>>>>>> Hi claudiu,
> >>>>>>>
> >>>>>>>> -----Original Message-----
> >>>>>>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >>>>>>>> Sent: Friday, June 21, 2024 1:55 PM
> >>>>>>>> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic:
> >>>>>>>> Document the R9A08G045 support
> >>>>>>>>
> >>>>>>>>
> >>>>>>>>
> >>>>>>>> On 21.06.2024 15:34, Biju Das wrote:
> >>>>>>>>> Hi Claudiu,
> >>>>>>>>>
> >>>>>>>>>> -----Original Message-----
> >>>>>>>>>> From: Claudiu <claudiu.beznea@tuxon.dev>
> >>>>>>>>>> Sent: Friday, June 21, 2024 12:23 PM
> >>>>>>>>>> Subject: [PATCH 08/12] dt-bindings: i2c: renesas,riic:
> >>>>>>>>>> Document the
> >>>>>>>>>> R9A08G045 support
> >>>>>>>>>>
> >>>>>>>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>>>>>>>>
> >>>>>>>>>> Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is
> >>>>>>>>>> compatible with the version available on Renesas RZ/V2H
> >>>>>>>>>> (R9A09G075). Most of the IP variants that the RIIC driver is
> >>>>>>>>>> working with supports fast mode
> >>>> plus.
> >>>>>>>>>> However, it happens that on the same SoC to have IP
> >>>>>>>>>> instatiations that support fast mode plus as well as IP
> >>>>>>>>>> instantiation that doesn't support it. For this, introduced
> >>>>>>>>>> the renesas,riic-no-fast-
> >> mode-plus property.
> >>>>>>>>>>
> >>>>>>>>>> Signed-off-by: Claudiu Beznea
> >>>>>>>>>> <claudiu.beznea.uj@bp.renesas.com>
> >>>>>>>>>> ---
> >>>>>>>>>>  Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 8
> >>>>>>>>>> ++++++++
> >>>>>>>>>>  1 file changed, 8 insertions(+)
> >>>>>>>>>>
> >>>>>>>>>> diff --git
> >>>>>>>>>> a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>>>>>>>> b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>>>>>>>> index 91ecf17b7a81..c0964edbca69 100644
> >>>>>>>>>> --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>>>>>>>> +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>>>>>>>> @@ -25,6 +25,10 @@ properties:
> >>>>>>>>>>                - renesas,riic-r9a07g054  # RZ/V2L
> >>>>>>>>>>            - const: renesas,riic-rz      # RZ/A or RZ/G2L
> >>>>>>>>>>
> >>>>>>>>>> +      - items:
> >>>>>>>>>> +          - const: renesas,riic-r9a08g045   # RZ/G3S
> >>>>>>>>>> +          - const: renesas,riic-r9a09g057
> >>>>>>>>>> +
> >>>>>>>>>>        - const: renesas,riic-r9a09g057   # RZ/V2H(P)
> >>>>>>>>>>
> >>>>>>>>>>    reg:
> >>>>>>>>>> @@ -66,6 +70,10 @@ properties:
> >>>>>>>>>>    resets:
> >>>>>>>>>>      maxItems: 1
> >>>>>>>>>>
> >>>>>>>>>> +  renesas,riic-no-fast-mode-plus:
> >>>>>>>>>> +    description: specifies if fast mode plus is not supported
> >>>>>>>>>> +    type: Boolean
> >>>>>>>>>
> >>>>>>>>> Can't this info, as part of device data?? Based on frequency
> >>>>>>>>> and device data is enough to derive this info??
> >>>>>>>>
> >>>>>>>> We can't rely completely on device data because on RZ/G3S we
> >>>>>>>> have
> >>>>>>>> 2 RIIC channels that support fast mode plus and 2 that doesn't support it.
> >>>>>>>
> >>>>>>> Can't array of bits for this channels won't help??
> >>>>>>
> >>>>>> Can you give an example? I'm not sure I understand how you would
> >>>>>> prefer me to use the array of bits.
> >>>>>
> >>>>> struct riic_of_data {
> >>>>> 	u8 regs[RIIC_REG_END];
> >>>>> 	u16 fast_mode_info info; /* 1 means fast mode plus supported,
> >>>>> starting with channel 0*/ };
> >>>>>
> >>>>> .info = 0x3, means channel 0 and 1 has fast mode plus supported
> >>>>> .info = 0x0, none of the channel supported fast mode plus.
> >>>>
> >>>> If I understand the proposal correctly, a match b/w struct
> >>>> riic_of_data::info bit + frequency and the nodes in device tree is
> >>>> still needed, right? As the RZ/G3S RIIC channels are using the same compatible.
> >>>> W/o a match how I cannot detect in the driver who is, e.g., channel
> >>>> 1 that supports FMP w/o hardcoding some RIIC channel data in the
> >>>> driver (e.g. RIIC channel
> >> address)?
> >>>
> >>> bit array gives the capability info on various channels.
> >>>
> >>> If someone define fast_mode_plus frequency in DT node and channel is
> >>> not fast_mode_plus(from the capability info) then you should return error.
> >>>
> >>> Here you need to use SoC specific compatible as each SoC has different capabilities.
> >>
> >> And I would add, as it is in this case: there are multiple instantiation of the RIIC in RZ/G3S
> SoC.
> >> RIIC 0 and 1 supports FMP, RIIC 2 and 3 does not.
> >>
> >> For all RIICs (0, 1, 2, 3) we use the same compatible (as all are
> >> part of the same SoC). How to do the match b/w DT RIIC channel and
> >> driver with the solution you propose w/o hardcoding some RIIC channel data in the driver?
> >
> > .info =0x3, so you know from the capability, for this soc, bus 0 and 1 supports FMP.
> 
> I understand this part. What I don't understand is: when probing the driver for, e.g., bus 0, how
> do I know I probe the driver for bus 0? compatible is the same for all buses.

You are right. I missed this point.

Cheers,
biju

RE: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support

[Biju Das]

Hi Claudiu,

> -----Original Message-----
> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> Sent: Friday, June 21, 2024 3:59 PM
> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support
> 
> 
> 
> On 21.06.2024 17:37, Biju Das wrote:
> >
> >
> >> -----Original Message-----
> >> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >> Sent: Friday, June 21, 2024 3:31 PM
> >> To: Biju Das <biju.das.jz@bp.renesas.com>; Chris Brandt
> >> <Chris.Brandt@renesas.com>; andi.shyti@kernel.org; robh@kernel.org;
> >> krzk+dt@kernel.org; conor+dt@kernel.org;
> >> geert+renesas@glider.be; magnus.damm@gmail.com;
> >> geert+mturquette@baylibre.com; sboyd@kernel.org;
> >> p.zabel@pengutronix.de; wsa+renesas@sang-engineering.com
> >> Cc: linux-renesas-soc@vger.kernel.org; linux-i2c@vger.kernel.org;
> >> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> >> linux-clk@vger.kernel.org; Claudiu Beznea
> >> <claudiu.beznea.uj@bp.renesas.com>
> >> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document
> >> the R9A08G045 support
> >>
> >>
> >>
> >> On 21.06.2024 17:06, Biju Das wrote:
> >>> Hi Claudiu,
> >>>
> >>>> -----Original Message-----
> >>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >>>> Sent: Friday, June 21, 2024 2:30 PM
> >>>> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document
> >>>> the R9A08G045 support
> >>>>
> >>>>
> >>>>
> >>>> On 21.06.2024 16:10, Biju Das wrote:
> >>>>>
> >>>>>
> >>>>>> -----Original Message-----
> >>>>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >>>>>> Sent: Friday, June 21, 2024 2:06 PM
> >>>>>  Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic:
> >>>>> Document the R9A08G045 support
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>> On 21.06.2024 15:56, Biju Das wrote:
> >>>>>>>
> >>>>>>> Hi claudiu,
> >>>>>>>
> >>>>>>>> -----Original Message-----
> >>>>>>>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >>>>>>>> Sent: Friday, June 21, 2024 1:55 PM
> >>>>>>>> Subject: Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic:
> >>>>>>>> Document the R9A08G045 support
> >>>>>>>>
> >>>>>>>>
> >>>>>>>>
> >>>>>>>> On 21.06.2024 15:34, Biju Das wrote:
> >>>>>>>>> Hi Claudiu,
> >>>>>>>>>
> >>>>>>>>>> -----Original Message-----
> >>>>>>>>>> From: Claudiu <claudiu.beznea@tuxon.dev>
> >>>>>>>>>> Sent: Friday, June 21, 2024 12:23 PM
> >>>>>>>>>> Subject: [PATCH 08/12] dt-bindings: i2c: renesas,riic:
> >>>>>>>>>> Document the
> >>>>>>>>>> R9A08G045 support
> >>>>>>>>>>
> >>>>>>>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>>>>>>>>
> >>>>>>>>>> Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is
> >>>>>>>>>> compatible with the version available on Renesas RZ/V2H
> >>>>>>>>>> (R9A09G075). Most of the IP variants that the RIIC driver is
> >>>>>>>>>> working with supports fast mode
> >>>> plus.
> >>>>>>>>>> However, it happens that on the same SoC to have IP
> >>>>>>>>>> instatiations that support fast mode plus as well as IP
> >>>>>>>>>> instantiation that doesn't support it. For this, introduced
> >>>>>>>>>> the renesas,riic-no-fast-
> >> mode-plus property.
> >>>>>>>>>>
> >>>>>>>>>> Signed-off-by: Claudiu Beznea
> >>>>>>>>>> <claudiu.beznea.uj@bp.renesas.com>
> >>>>>>>>>> ---
> >>>>>>>>>>  Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 8
> >>>>>>>>>> ++++++++
> >>>>>>>>>>  1 file changed, 8 insertions(+)
> >>>>>>>>>>
> >>>>>>>>>> diff --git
> >>>>>>>>>> a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>>>>>>>> b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>>>>>>>> index 91ecf17b7a81..c0964edbca69 100644
> >>>>>>>>>> --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>>>>>>>> +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> >>>>>>>>>> @@ -25,6 +25,10 @@ properties:
> >>>>>>>>>>                - renesas,riic-r9a07g054  # RZ/V2L
> >>>>>>>>>>            - const: renesas,riic-rz      # RZ/A or RZ/G2L
> >>>>>>>>>>
> >>>>>>>>>> +      - items:
> >>>>>>>>>> +          - const: renesas,riic-r9a08g045   # RZ/G3S
> >>>>>>>>>> +          - const: renesas,riic-r9a09g057
> >>>>>>>>>> +
> >>>>>>>>>>        - const: renesas,riic-r9a09g057   # RZ/V2H(P)
> >>>>>>>>>>
> >>>>>>>>>>    reg:
> >>>>>>>>>> @@ -66,6 +70,10 @@ properties:
> >>>>>>>>>>    resets:
> >>>>>>>>>>      maxItems: 1
> >>>>>>>>>>
> >>>>>>>>>> +  renesas,riic-no-fast-mode-plus:
> >>>>>>>>>> +    description: specifies if fast mode plus is not supported
> >>>>>>>>>> +    type: Boolean
> >>>>>>>>>
> >>>>>>>>> Can't this info, as part of device data?? Based on frequency
> >>>>>>>>> and device data is enough to derive this info??
> >>>>>>>>
> >>>>>>>> We can't rely completely on device data because on RZ/G3S we
> >>>>>>>> have
> >>>>>>>> 2 RIIC channels that support fast mode plus and 2 that doesn't support it.
> >>>>>>>
> >>>>>>> Can't array of bits for this channels won't help??
> >>>>>>
> >>>>>> Can you give an example? I'm not sure I understand how you would
> >>>>>> prefer me to use the array of bits.
> >>>>>
> >>>>> struct riic_of_data {
> >>>>> 	u8 regs[RIIC_REG_END];
> >>>>> 	u16 fast_mode_info info; /* 1 means fast mode plus supported,
> >>>>> starting with channel 0*/ };
> >>>>>
> >>>>> .info = 0x3, means channel 0 and 1 has fast mode plus supported
> >>>>> .info = 0x0, none of the channel supported fast mode plus.
> >>>>
> >>>> If I understand the proposal correctly, a match b/w struct
> >>>> riic_of_data::info bit + frequency and the nodes in device tree is
> >>>> still needed, right? As the RZ/G3S RIIC channels are using the same compatible.
> >>>> W/o a match how I cannot detect in the driver who is, e.g., channel
> >>>> 1 that supports FMP w/o hardcoding some RIIC channel data in the
> >>>> driver (e.g. RIIC channel
> >> address)?
> >>>
> >>> bit array gives the capability info on various channels.
> >>>
> >>> If someone define fast_mode_plus frequency in DT node and channel is
> >>> not fast_mode_plus(from the capability info) then you should return error.
> >>>
> >>> Here you need to use SoC specific compatible as each SoC has different capabilities.
> >>
> >> And I would add, as it is in this case: there are multiple instantiation of the RIIC in RZ/G3S
> SoC.
> >> RIIC 0 and 1 supports FMP, RIIC 2 and 3 does not.
> >>
> >> For all RIICs (0, 1, 2, 3) we use the same compatible (as all are
> >> part of the same SoC). How to do the match b/w DT RIIC channel and
> >> driver with the solution you propose w/o hardcoding some RIIC channel data in the driver?
> >
> > .info =0x3, so you know from the capability, for this soc, bus 0 and 1 supports FMP.
> 
> I understand this part. What I don't understand is: when probing the driver for, e.g., bus 0, how
> do I know I probe the driver for bus 0? compatible is the same for all buses.

I am not a DT expert.

Another option is maybe a different compatible for "renesas,riic- r9a08g045-fmp"
to describe buses with fmp and "renesas,riic- r9a08g045" for buses that don't support fmp

and maybe you can validate at dt-binding level to check against frequencies??

If non-fmp bus, dt-binding check should check the frequency and if it is greater the fast mode frequency
Then the check should fail, not sure the dt-binding check allows (x > y) comparison ??

Cheers,
Biju

Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1659 bytes --]

On Fri, Jun 21, 2024 at 02:22:59PM +0300, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is compatible with
> the version available on Renesas RZ/V2H (R9A09G075). Most of the IP
> variants that the RIIC driver is working with supports fast mode plus.
> However, it happens that on the same SoC to have IP instatiations that
> support fast mode plus as well as IP instantiation that doesn't support
> it. For this, introduced the renesas,riic-no-fast-mode-plus property.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> index 91ecf17b7a81..c0964edbca69 100644
> --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> @@ -25,6 +25,10 @@ properties:
>                - renesas,riic-r9a07g054  # RZ/V2L
>            - const: renesas,riic-rz      # RZ/A or RZ/G2L
>  
> +      - items:
> +          - const: renesas,riic-r9a08g045   # RZ/G3S
> +          - const: renesas,riic-r9a09g057
> +
>        - const: renesas,riic-r9a09g057   # RZ/V2H(P)
>  
>    reg:
> @@ -66,6 +70,10 @@ properties:
>    resets:
>      maxItems: 1
>  
> +  renesas,riic-no-fast-mode-plus:
> +    description: specifies if fast mode plus is not supported
> +    type: boolean

The correct type here is "flag", not boolean.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support

[Geert Uytterhoeven]

Hi Claudiu,

On Fri, Jun 21, 2024 at 1:23 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is compatible with
> the version available on Renesas RZ/V2H (R9A09G075). Most of the IP
> variants that the RIIC driver is working with supports fast mode plus.
> However, it happens that on the same SoC to have IP instatiations that
> support fast mode plus as well as IP instantiation that doesn't support
> it. For this, introduced the renesas,riic-no-fast-mode-plus property.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Thanks for your patch!

> --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> @@ -25,6 +25,10 @@ properties:
>                - renesas,riic-r9a07g054  # RZ/V2L
>            - const: renesas,riic-rz      # RZ/A or RZ/G2L
>
> +      - items:
> +          - const: renesas,riic-r9a08g045   # RZ/G3S
> +          - const: renesas,riic-r9a09g057
> +

LGTM.

>        - const: renesas,riic-r9a09g057   # RZ/V2H(P)
>
>    reg:
> @@ -66,6 +70,10 @@ properties:
>    resets:
>      maxItems: 1
>
> +  renesas,riic-no-fast-mode-plus:
> +    description: specifies if fast mode plus is not supported
> +    type: boolean
> +

Do you really need this?
The bus' clock-frequency property should take into account the combined
capabilities of all of controller, target, and wiring.  It is up to the
DTS writer to validate that all timing conditions are met.

>  required:
>    - compatible
>    - reg

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 08/12] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support

[claudiu beznea]

Hi, Geert,

On 24.06.2024 18:40, Geert Uytterhoeven wrote:
> Hi Claudiu,
> 
> On Fri, Jun 21, 2024 at 1:23 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is compatible with
>> the version available on Renesas RZ/V2H (R9A09G075). Most of the IP
>> variants that the RIIC driver is working with supports fast mode plus.
>> However, it happens that on the same SoC to have IP instatiations that
>> support fast mode plus as well as IP instantiation that doesn't support
>> it. For this, introduced the renesas,riic-no-fast-mode-plus property.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Thanks for your patch!
> 
>> --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>> +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
>> @@ -25,6 +25,10 @@ properties:
>>                - renesas,riic-r9a07g054  # RZ/V2L
>>            - const: renesas,riic-rz      # RZ/A or RZ/G2L
>>
>> +      - items:
>> +          - const: renesas,riic-r9a08g045   # RZ/G3S
>> +          - const: renesas,riic-r9a09g057
>> +
> 
> LGTM.
> 
>>        - const: renesas,riic-r9a09g057   # RZ/V2H(P)
>>
>>    reg:
>> @@ -66,6 +70,10 @@ properties:
>>    resets:
>>      maxItems: 1
>>
>> +  renesas,riic-no-fast-mode-plus:
>> +    description: specifies if fast mode plus is not supported
>> +    type: boolean
>> +
> 
> Do you really need this?
> The bus' clock-frequency property should take into account the combined
> capabilities of all of controller, target, and wiring.  It is up to the
> DTS writer to validate that all timing conditions are met.

On a second thought, I tend to agree with you on this.

I added it to comply with "chapter 47.5.15 I2C Bus Interface Access
Timing, note 7, Tfmin cannot meet the specification in fast-mode plus for
the RIIC ch2 and ch3" statement from hw manual.

Thank you,
Claudiu Beznea

> 
>>  required:
>>    - compatible
>>    - reg
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 

[PATCH 09/12] i2c: riic: Add support for fast mode plus

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Fast mode plus is available on most of the IP variants that RIIC driver
is working with. The exception is (according to HW manuals of the SoCs
where this IP is available) the Renesas RZ/A1H. Along with it,
according to the RZ/G3S HW manual, chapter 47.5.15 I2C Bus Interface Access
Timing, note 7, Tfmin cannot meet the specification in fast-mode plus for
the RIIC ch2 and ch3.

Due to these limitations:
- the struct riic_of_data::fast_mode_plus was introduced to address the
  Renesas RZ/A1H use case
- the renesas,riic-no-fast-mode-plus was introduced to address the Renesas
  RZ/G3S limitation.

Fast mode plus was tested on RZ/G3S, RZ/G2{L,UL,LC}, RZ/Five by
instantiating the RIIC frequency to 1MHz and issuing i2c reads on the
fast mode plus capable devices (and the i2c clock frequency was checked on
RZ/G3S).

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/i2c/busses/i2c-riic.c | 36 +++++++++++++++++++++++++++++++----
 1 file changed, 32 insertions(+), 4 deletions(-)

diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
index 46070f323810..d246143a1037 100644
--- a/drivers/i2c/busses/i2c-riic.c
+++ b/drivers/i2c/busses/i2c-riic.c
@@ -63,6 +63,8 @@
 #define ICMR3_ACKWP	0x10
 #define ICMR3_ACKBT	0x08
 
+#define ICFER_FMPE	0x80
+
 #define ICIER_TIE	0x80
 #define ICIER_TEIE	0x40
 #define ICIER_RIE	0x20
@@ -80,6 +82,7 @@ enum riic_reg_list {
 	RIIC_ICCR2,
 	RIIC_ICMR1,
 	RIIC_ICMR3,
+	RIIC_ICFER,
 	RIIC_ICSER,
 	RIIC_ICIER,
 	RIIC_ICSR2,
@@ -92,6 +95,7 @@ enum riic_reg_list {
 
 struct riic_of_data {
 	const u8 *regs;
+	bool fast_mode_plus;
 };
 
 struct riic_dev {
@@ -107,6 +111,7 @@ struct riic_dev {
 	struct clk *clk;
 	struct reset_control *rstc;
 	struct i2c_timings i2c_t;
+	bool fast_mode_plus;
 };
 
 struct riic_irq_desc {
@@ -316,10 +321,11 @@ static int riic_init_hw(struct riic_dev *riic)
 	struct i2c_timings *t = &riic->i2c_t;
 	struct device *dev = riic->adapter.dev.parent;
 
-	if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) {
-		dev_err(dev,
-			"unsupported bus speed (%dHz). %d max\n",
-			t->bus_freq_hz, I2C_MAX_FAST_MODE_FREQ);
+	if ((!riic->fast_mode_plus && t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) ||
+	    (riic->fast_mode_plus && t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)) {
+		dev_err(dev, "unsupported bus speed (%dHz). %d max\n", t->bus_freq_hz,
+			riic->fast_mode_plus ? I2C_MAX_FAST_MODE_PLUS_FREQ :
+			I2C_MAX_FAST_MODE_FREQ);
 		return -EINVAL;
 	}
 
@@ -407,6 +413,9 @@ static int riic_init_hw(struct riic_dev *riic)
 	riic_writeb(riic, 0, RIIC_ICSER);
 	riic_writeb(riic, ICMR3_ACKWP | ICMR3_RDRFS, RIIC_ICMR3);
 
+	if (riic->fast_mode_plus && t->bus_freq_hz == I2C_MAX_FAST_MODE_PLUS_FREQ)
+		riic_clear_set_bit(riic, 0, ICFER_FMPE, RIIC_ICFER);
+
 	riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
 
 	pm_runtime_mark_last_busy(dev);
@@ -487,6 +496,14 @@ static int riic_i2c_probe(struct platform_device *pdev)
 	init_completion(&riic->msg_done);
 
 	i2c_parse_fw_timings(dev, &riic->i2c_t, true);
+	if (riic->info->fast_mode_plus) {
+		/*
+		 * On the same SoC it may happen to have IP variants that support
+		 * fast mode plus as well as IP variants that doesn't support it.
+		 */
+		riic->fast_mode_plus = !of_property_read_bool(dev->of_node,
+							      "renesas,riic-no-fast-mode-plus");
+	}
 
 	pm_runtime_set_autosuspend_delay(dev, 0);
 	pm_runtime_use_autosuspend(dev);
@@ -535,6 +552,7 @@ static const u8 riic_rz_a_regs[RIIC_REG_END] = {
 	[RIIC_ICCR2] = 0x04,
 	[RIIC_ICMR1] = 0x08,
 	[RIIC_ICMR3] = 0x10,
+	[RIIC_ICFER] = 0x14,
 	[RIIC_ICSER] = 0x18,
 	[RIIC_ICIER] = 0x1c,
 	[RIIC_ICSR2] = 0x24,
@@ -548,11 +566,17 @@ static const struct riic_of_data riic_rz_a_info = {
 	.regs = riic_rz_a_regs,
 };
 
+static const struct riic_of_data riic_rz_g2_info = {
+	.regs = riic_rz_a_regs,
+	.fast_mode_plus = true,
+};
+
 static const u8 riic_rz_v2h_regs[RIIC_REG_END] = {
 	[RIIC_ICCR1] = 0x00,
 	[RIIC_ICCR2] = 0x01,
 	[RIIC_ICMR1] = 0x02,
 	[RIIC_ICMR3] = 0x04,
+	[RIIC_ICFER] = 0x05,
 	[RIIC_ICSER] = 0x06,
 	[RIIC_ICIER] = 0x07,
 	[RIIC_ICSR2] = 0x09,
@@ -564,6 +588,7 @@ static const u8 riic_rz_v2h_regs[RIIC_REG_END] = {
 
 static const struct riic_of_data riic_rz_v2h_info = {
 	.regs = riic_rz_v2h_regs,
+	.fast_mode_plus = true,
 };
 
 static int riic_i2c_suspend(struct device *dev)
@@ -610,6 +635,9 @@ static const struct dev_pm_ops riic_i2c_pm_ops = {
 
 static const struct of_device_id riic_i2c_dt_ids[] = {
 	{ .compatible = "renesas,riic-rz", .data = &riic_rz_a_info },
+	{ .compatible = "renesas,riic-r9a07g043", .data =  &riic_rz_g2_info, },
+	{ .compatible = "renesas,riic-r9a07g044", .data =  &riic_rz_g2_info, },
+	{ .compatible = "renesas,riic-r9a07g054", .data =  &riic_rz_g2_info, },
 	{ .compatible = "renesas,riic-r9a09g057", .data = &riic_rz_v2h_info },
 	{ /* Sentinel */ },
 };
-- 
2.39.2

[PATCH 10/12] arm64: dts: renesas: r9a08g045: Add I2C nodes

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

The Renesas RZ/G3S has 4 I2C channels. Add DT nodes for it.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 90 ++++++++++++++++++++++
 1 file changed, 90 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 2162c247d6de..cc5beed37ae8 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -72,6 +72,96 @@ scif0: serial@1004b800 {
 			status = "disabled";
 		};
 
+		i2c0: i2c@10090000 {
+			compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
+			reg = <0 0x10090000 0 0x400>;
+			interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD R9A08G045_I2C0_PCLK>;
+			clock-frequency = <100000>;
+			resets = <&cpg R9A08G045_I2C0_MRST>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@10090400 {
+			compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
+			reg = <0 0x10090400 0 0x400>;
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD R9A08G045_I2C1_PCLK>;
+			clock-frequency = <100000>;
+			resets = <&cpg R9A08G045_I2C1_MRST>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@10090800 {
+			compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
+			reg = <0 0x10090800 0 0x400>;
+			interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD R9A08G045_I2C2_PCLK>;
+			clock-frequency = <100000>;
+			resets = <&cpg R9A08G045_I2C2_MRST>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			renesas,riic-no-fast-mode-plus;
+			status = "disabled";
+		};
+
+		i2c3: i2c@10090c00 {
+			compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
+			reg = <0 0x10090c00 0 0x400>;
+			interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD R9A08G045_I2C3_PCLK>;
+			clock-frequency = <100000>;
+			resets = <&cpg R9A08G045_I2C3_MRST>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			renesas,riic-no-fast-mode-plus;
+			status = "disabled";
+		};
+
 		cpg: clock-controller@11010000 {
 			compatible = "renesas,r9a08g045-cpg";
 			reg = <0 0x11010000 0 0x10000>;
-- 
2.39.2

[PATCH 11/12] arm64: dts: renesas: rzg3s-smarc: Enable i2c0 node

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Enable i2c0 node.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
index deb2ad37bb2e..7945d44e6ee1 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
@@ -11,6 +11,7 @@
 
 / {
 	aliases {
+		i2c0 = &i2c0;
 		serial0 = &scif0;
 		mmc1 = &sdhi1;
 	};
@@ -66,6 +67,12 @@ vccq_sdhi1: regulator-vccq-sdhi1 {
 	};
 };
 
+&i2c0 {
+	status = "okay";
+
+	clock-frequency = <1000000>;
+};
+
 &pinctrl {
 	key-1-gpio-hog {
 		gpio-hog;
-- 
2.39.2

[PATCH 12/12] arm64: dts: renesas: rzg3s-smarc-som: Enable i2c1 node

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Enable i2c1 node.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index 8a3d302f1535..21bfa4e03972 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -32,6 +32,7 @@ / {
 	compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
 
 	aliases {
+		i2c1 = &i2c1;
 		mmc0 = &sdhi0;
 #if SW_CONFIG3 == SW_OFF
 		mmc2 = &sdhi2;
@@ -150,6 +151,10 @@ &extal_clk {
 	clock-frequency = <24000000>;
 };
 
+&i2c1 {
+	status = "okay";
+};
+
 #if SW_CONFIG2 == SW_ON
 /* SD0 slot */
 &sdhi0 {
-- 
2.39.2