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From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Linus Walleij <linus.walleij@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@vger.kernel.org>,
	Takeshi Kihara <takeshi.kihara.df@renesas.com>
Subject: Re: [PATCH 3/6] pinctrl: sh-pfc: r8a77990: Add bias pinconf support
Date: Tue, 15 May 2018 10:40:55 +0200	[thread overview]
Message-ID: <CAMuHMdURM9oRi6BEWgmXhkEwBQYvm+7ORnqkQCOSmvQaM9_xwQ@mail.gmail.com> (raw)
In-Reply-To: <CAMuHMdWEzRic5dy_Daj-JDkwCjn7mPTmWbVb7zTPLbuxcQ22Fg@mail.gmail.com>

On Mon, May 14, 2018 at 10:13 PM, Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> On Fri, May 11, 2018 at 5:22 AM, Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
>> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>>
>> This patch implements control of pull-up and pull-down. On this SoC there
>> is no simple mapping of GP pins to bias register bits, so we need a table.
>>
>> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> Thanks for your patch!
>
>> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
>> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
>
>> @@ -1227,10 +1248,55 @@ enum {
>>
>>         PINMUX_IPSR_GPSR(IP15_31_28,            USB30_OVC),
>>         PINMUX_IPSR_MSEL(IP15_31_28,            USB0_OVC_A,     SEL_USB_20_CH0_0),
>> +
>> +/*
>> + * Static pins can not be muxed between different functions but
>> + * still needs a mark entry in the pinmux list. Add each static
>
> need mark entries
>
>> + * pin to the list without an associated function. The sh-pfc
>> + * core will do the right thing and skip trying to mux then pin
>
> mux the pin
>
>> + * while still applying configuration to it
>
> period
>
> I have just sent a patch to fix the other copies, in the hope these grammar
> atrocities will stop spreading ;-)
>
>> @@ -1708,8 +1774,263 @@ enum {
>>         { },
>>  };
>>
>> +static const struct pinmux_bias_reg pinmux_bias_regs[] = {
>
> The register definitions look OK to me.
> I'll review the actual pin mappings later.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in sh-pfc-for-v4.18 with the comments fixed.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

  reply	other threads:[~2018-05-15  8:40 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-11  3:22 [PATCH 0/6] pinctrl: sh-pfc: Initial R8A77990 PFC support Yoshihiro Shimoda
2018-05-11  3:22 ` [PATCH 1/6] pinctrl: sh-pfc: Add PORT_GP_11 helper macro Yoshihiro Shimoda
2018-05-14 15:23   ` Geert Uytterhoeven
2018-05-11  3:22 ` [PATCH 2/6] pinctrl: sh-pfc: Initial R8A77990 PFC support Yoshihiro Shimoda
2018-05-14 15:32   ` Geert Uytterhoeven
2018-05-11  3:22 ` [PATCH 3/6] pinctrl: sh-pfc: r8a77990: Add bias pinconf support Yoshihiro Shimoda
2018-05-14 20:13   ` Geert Uytterhoeven
2018-05-15  8:40     ` Geert Uytterhoeven [this message]
2018-05-11  3:22 ` [PATCH 4/6] pinctrl: sh-pfc: r8a77990: Add SCIF pins, groups and functions Yoshihiro Shimoda
2018-05-15  8:55   ` Geert Uytterhoeven
2018-05-11  3:22 ` [PATCH 5/6] pinctrl: sh-pfc: r8a77990: Add I2C{1,2,4,5,6,7} " Yoshihiro Shimoda
2018-05-15  9:11   ` Geert Uytterhoeven
2018-05-11  3:22 ` [PATCH 6/6] pinctrl: sh-pfc: r8a77990: Add EthernetAVB " Yoshihiro Shimoda
2018-05-15  9:18   ` Geert Uytterhoeven

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