[PATCH 00/12] Add r8a77470/iW-RainboW-G23S single board computer support

[PATCH 00/12] Add r8a77470/iW-RainboW-G23S single board computer support

[Biju Das]

Hello, 

This series adds support for Rensas RZ/G1C (r8a77470) SoC and
RZ/G1C based iW-RainboW-G23S single board computer.

The series introduces a cpg-mssr clock/power gating module, a power/reset
controller for the SoC.

power areas for RZ/G1C are similar to RZ/G1E.

Few functionalities have currently been enabled in DTS and tested: serial
boot console.

This patch series tested against linux-next tag next-20180327 and
renesas-dev branch tag "renesas-dev-20180326v2-v4.16-rc7

Biju Das (12):
  soc: renesas: rcar-sysc: Add r8a77470 support
  soc: renesas: Identify RZ/G1C
  soc: renesas: rcar-rst: Add support for RZ/G1C
  serial: sh-sci: Document r8a77470 bindings
  clk: renesas: Add r8a77470 CPG Core Clock Definitions
  clk: renesas: cpg-mssr: Add r8a77470 support
  ARM: shmobile: r8a77470: basic SoC support
  ARM: dts: r8a77470: Initial SoC device tree
  ARM: shmobile: Document iW-RainboW-G23S single board computer
  ARM: dts: iwg23s-sbc: Add support for iWave G23S-SBC based on RZ/G1C
  ARM: shmobile: defconfig: Enable r8a77470 SoC
  ARM: multi_v7_defconfig: Enable r8a77470 SoC

 Documentation/devicetree/bindings/arm/shmobile.txt |   4 +
 .../devicetree/bindings/clock/renesas,cpg-mssr.txt |   9 +-
 .../bindings/power/renesas,rcar-sysc.txt           |   1 +
 .../devicetree/bindings/reset/renesas,rst.txt      |   1 +
 .../bindings/serial/renesas,sci-serial.txt         |   2 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts          |  30 +++
 arch/arm/boot/dts/r8a77470.dtsi                    | 156 ++++++++++++++
 arch/arm/configs/multi_v7_defconfig                |   1 +
 arch/arm/configs/shmobile_defconfig                |   1 +
 arch/arm/mach-shmobile/Kconfig                     |   4 +
 arch/arm/mach-shmobile/setup-rcar-gen2.c           |   2 +
 drivers/clk/renesas/Kconfig                        |   5 +
 drivers/clk/renesas/Makefile                       |   1 +
 drivers/clk/renesas/r8a7747x-cpg-mssr.c            | 229 +++++++++++++++++++++
 drivers/clk/renesas/rcar-gen2-cpg.c                |  34 ++-
 drivers/clk/renesas/renesas-cpg-mssr.c             |   6 +
 drivers/clk/renesas/renesas-cpg-mssr.h             |   1 +
 drivers/soc/renesas/Kconfig                        |   5 +
 drivers/soc/renesas/Makefile                       |   1 +
 drivers/soc/renesas/r8a7747x-sysc.c                |  29 +++
 drivers/soc/renesas/rcar-rst.c                     |   1 +
 drivers/soc/renesas/rcar-sysc.c                    |   3 +
 drivers/soc/renesas/rcar-sysc.h                    |   1 +
 drivers/soc/renesas/renesas-soc.c                  |   8 +
 include/dt-bindings/clock/r8a7747x-cpg-mssr.h      |  36 ++++
 include/dt-bindings/power/r8a7747x-sysc.h          |  22 ++
 27 files changed, 587 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
 create mode 100644 arch/arm/boot/dts/r8a77470.dtsi
 create mode 100644 drivers/clk/renesas/r8a7747x-cpg-mssr.c
 create mode 100644 drivers/soc/renesas/r8a7747x-sysc.c
 create mode 100644 include/dt-bindings/clock/r8a7747x-cpg-mssr.h
 create mode 100644 include/dt-bindings/power/r8a7747x-sysc.h

-- 
2.7.4

[PATCH 01/12] soc: renesas: rcar-sysc: Add r8a77470 support

[Biju Das]

Add support for RZ/G1C (R8A77470) SoC power areas to the R-Car SYSC
driver.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 .../bindings/power/renesas,rcar-sysc.txt           |  1 +
 drivers/soc/renesas/Kconfig                        |  5 ++++
 drivers/soc/renesas/Makefile                       |  1 +
 drivers/soc/renesas/r8a7747x-sysc.c                | 29 ++++++++++++++++++++++
 drivers/soc/renesas/rcar-sysc.c                    |  3 +++
 drivers/soc/renesas/rcar-sysc.h                    |  1 +
 include/dt-bindings/power/r8a7747x-sysc.h          | 22 ++++++++++++++++
 7 files changed, 62 insertions(+)
 create mode 100644 drivers/soc/renesas/r8a7747x-sysc.c
 create mode 100644 include/dt-bindings/power/r8a7747x-sysc.h

diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
index ab399e5..3e91d20 100644
--- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
@@ -9,6 +9,7 @@ Required properties:
   - compatible: Must contain exactly one of the following:
       - "renesas,r8a7743-sysc" (RZ/G1M)
       - "renesas,r8a7745-sysc" (RZ/G1E)
+      - "renesas,r8a77470-sysc" (RZ/G1C)
       - "renesas,r8a7779-sysc" (R-Car H1)
       - "renesas,r8a7790-sysc" (R-Car H2)
       - "renesas,r8a7791-sysc" (R-Car M2-W)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 3bbe611..96dd936 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -7,6 +7,7 @@ config SOC_RENESAS
 			   ARCH_R8A77970 || ARCH_R8A77980 || ARCH_R8A77995
 	select SYSC_R8A7743 if ARCH_R8A7743
 	select SYSC_R8A7745 if ARCH_R8A7745
+	select SYSC_R8A77470 if ARCH_R8A77470
 	select SYSC_R8A7779 if ARCH_R8A7779
 	select SYSC_R8A7790 if ARCH_R8A7790
 	select SYSC_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
@@ -30,6 +31,10 @@ config SYSC_R8A7745
 	bool "RZ/G1E System Controller support" if COMPILE_TEST
 	select SYSC_RCAR
 
+config SYSC_R8A77470
+	bool "RZ/G1C System Controller support" if COMPILE_TEST
+	select SYSC_RCAR
+
 config SYSC_R8A7779
 	bool "R-Car H1 System Controller support" if COMPILE_TEST
 	select SYSC_RCAR
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index ccb5ec5..3dd6c41 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_SOC_RENESAS)	+= renesas-soc.o
 # SoC
 obj-$(CONFIG_SYSC_R8A7743)	+= r8a7743-sysc.o
 obj-$(CONFIG_SYSC_R8A7745)	+= r8a7745-sysc.o
+obj-$(CONFIG_SYSC_R8A77470)	+= r8a7747x-sysc.o
 obj-$(CONFIG_SYSC_R8A7779)	+= r8a7779-sysc.o
 obj-$(CONFIG_SYSC_R8A7790)	+= r8a7790-sysc.o
 obj-$(CONFIG_SYSC_R8A7791)	+= r8a7791-sysc.o
diff --git a/drivers/soc/renesas/r8a7747x-sysc.c b/drivers/soc/renesas/r8a7747x-sysc.c
new file mode 100644
index 0000000..2306680
--- /dev/null
+++ b/drivers/soc/renesas/r8a7747x-sysc.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G1C System Controller
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include <linux/bug.h>
+#include <linux/kernel.h>
+
+#include <dt-bindings/power/r8a7747x-sysc.h>
+
+#include "rcar-sysc.h"
+
+static const struct rcar_sysc_area r8a77470_areas[] __initconst = {
+	{ "always-on",	    0, 0, R8A77470_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
+	{ "ca7-scu",	0x100, 0, R8A77470_PD_CA7_SCU,	R8A77470_PD_ALWAYS_ON,
+	  PD_SCU },
+	{ "ca7-cpu0",	0x1c0, 0, R8A77470_PD_CA7_CPU0,	R8A77470_PD_CA7_SCU,
+	  PD_CPU_NOCR },
+	{ "ca7-cpu1",	0x1c0, 1, R8A77470_PD_CA7_CPU1,	R8A77470_PD_CA7_SCU,
+	  PD_CPU_NOCR },
+	{ "sgx",	 0xc0, 0, R8A77470_PD_SGX, R8A77470_PD_ALWAYS_ON },
+};
+
+const struct rcar_sysc_info r8a77470_sysc_info __initconst = {
+	.areas = r8a77470_areas,
+	.num_areas = ARRAY_SIZE(r8a77470_areas),
+};
diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index faf20e7..99203bd 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -261,6 +261,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = {
 #ifdef CONFIG_SYSC_R8A7745
 	{ .compatible = "renesas,r8a7745-sysc", .data = &r8a7745_sysc_info },
 #endif
+#ifdef CONFIG_SYSC_R8A77470
+	{ .compatible = "renesas,r8a77470-sysc", .data = &r8a77470_sysc_info },
+#endif
 #ifdef CONFIG_SYSC_R8A7779
 	{ .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
 #endif
diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h
index dcdc9ec..9b24e3a 100644
--- a/drivers/soc/renesas/rcar-sysc.h
+++ b/drivers/soc/renesas/rcar-sysc.h
@@ -51,6 +51,7 @@ struct rcar_sysc_info {
 
 extern const struct rcar_sysc_info r8a7743_sysc_info;
 extern const struct rcar_sysc_info r8a7745_sysc_info;
+extern const struct rcar_sysc_info r8a77470_sysc_info;
 extern const struct rcar_sysc_info r8a7779_sysc_info;
 extern const struct rcar_sysc_info r8a7790_sysc_info;
 extern const struct rcar_sysc_info r8a7791_sysc_info;
diff --git a/include/dt-bindings/power/r8a7747x-sysc.h b/include/dt-bindings/power/r8a7747x-sysc.h
new file mode 100644
index 0000000..5f701df
--- /dev/null
+++ b/include/dt-bindings/power/r8a7747x-sysc.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7747x_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7747x_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A77470_PD_CA7_CPU0		 5
+#define R8A77470_PD_CA7_CPU1		 6
+#define R8A77470_PD_SGX			20
+#define R8A77470_PD_CA7_SCU		21
+
+/* Always-on power area */
+#define R8A77470_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7747x_SYSC_H__ */
-- 
2.7.4

Re: [PATCH 01/12] soc: renesas: rcar-sysc: Add r8a77470 support

[Geert Uytterhoeven]

Hi Biju,

On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> Add support for RZ/G1C (R8A77470) SoC power areas to the R-Car SYSC
> driver.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Thanks for your patch!

>  drivers/soc/renesas/r8a7747x-sysc.c                | 29 ++++++++++++++++++++++

While using "x" in drivers doesn't hurt, as it can be changed at any
time later...

>  include/dt-bindings/power/r8a7747x-sysc.h          | 22 ++++++++++++++++

... this is not true for DT bindings.

I know you do this to anticipate the use of this header file for r8a77471,
which is also called RZ/G1C, and identical to r8a77470, modulo a few on-SoC
devices. But using wildcards in DT bindings is a bad idea, as you cannot
predict what e.g. r8a77477 will be ;-)

So I'd settle for r8a77470-sysc.h. The actual defines in the file use
R8A77470_PD_* anyway.

BTW, I'm considering dropping all R8A*_PD_* definitions, as we can easily
use the numbers directly, cfr. module clock and interrupt numbers. That
would be one step closer to more .dtsi sharing.
The only thing that is keeping me back is that the value "32" (for the
always-on area) is not defined in the datasheet.

With the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 01/12] soc: renesas: rcar-sysc: Add r8a77470 support

[Biju Das]

Hi Geert,

Thanks for the feedback.

> On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> > Add support for RZ/G1C (R8A77470) SoC power areas to the R-Car SYSC
> > driver.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Thanks for your patch!
>
> >  drivers/soc/renesas/r8a7747x-sysc.c                | 29
> ++++++++++++++++++++++
>
> While using "x" in drivers doesn't hurt, as it can be changed at any time later...
>
> >  include/dt-bindings/power/r8a7747x-sysc.h          | 22 ++++++++++++++++
>
> ... this is not true for DT bindings.
>
> I know you do this to anticipate the use of this header file for r8a77471, which is
> also called RZ/G1C, and identical to r8a77470, modulo a few on-SoC devices.
> But using wildcards in DT bindings is a bad idea, as you cannot predict what e.g.
> r8a77477 will be ;-)
>
> So I'd settle for r8a77470-sysc.h. The actual defines in the file use
> R8A77470_PD_* anyway.

 Will send V2 with the file name changed to r8a77470-sysc.h

> BTW, I'm considering dropping all R8A*_PD_* definitions, as we can easily use
> the numbers directly, cfr. module clock and interrupt numbers. That would be
> one step closer to more .dtsi sharing.
> The only thing that is keeping me back is that the value "32" (for the always-on
> area) is not defined in the datasheet.
>
> With the above fixed:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But when
> I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

[PATCH 03/12] soc: renesas: rcar-rst: Add support for RZ/G1C

[Biju Das]

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 +
 drivers/soc/renesas/rcar-rst.c                          | 1 +
 2 files changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt
index 294a0da..7be61ef 100644
--- a/Documentation/devicetree/bindings/reset/renesas,rst.txt
+++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt
@@ -17,6 +17,7 @@ Required properties:
 		Examples with soctypes are:
 		  - "renesas,r8a7743-rst" (RZ/G1M)
 		  - "renesas,r8a7745-rst" (RZ/G1E)
+		  - "renesas,r8a77470-rst" (RZ/G1C)
 		  - "renesas,r8a7778-reset-wdt" (R-Car M1A)
 		  - "renesas,r8a7779-reset-wdt" (R-Car H1)
 		  - "renesas,r8a7790-rst" (R-Car H2)
diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
index 8e9cb79..66d7dba 100644
--- a/drivers/soc/renesas/rcar-rst.c
+++ b/drivers/soc/renesas/rcar-rst.c
@@ -44,6 +44,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
 	/* RZ/G is handled like R-Car Gen2 */
 	{ .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
 	{ .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },
+	{ .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 },
 	/* R-Car Gen1 */
 	{ .compatible = "renesas,r8a7778-reset-wdt", .data = &rcar_rst_gen1 },
 	{ .compatible = "renesas,r8a7779-reset-wdt", .data = &rcar_rst_gen1 },
-- 
2.7.4

Re: [PATCH 03/12] soc: renesas: rcar-rst: Add support for RZ/G1C

[Geert Uytterhoeven]

Hi Biju,

On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 03/12] soc: renesas: rcar-rst: Add support for RZ/G1C

[Simon Horman]

On Wed, Mar 28, 2018 at 10:00:49AM +0200, Geert Uytterhoeven wrote:
> Hi Biju,
> 
> On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thanks, applied.

[PATCH 04/12] serial: sh-sci: Document r8a77470 bindings

[Biju Das]

RZ/G1C (R8A77470) SoC also has the R-Car gen2 compatible SCIF and HSCIF
ports, so document the SoC specific bindings.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index ad962f4..a006ea4 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -17,6 +17,8 @@ Required properties:
     - "renesas,scifa-r8a7745" for R8A7745 (RZ/G1E) SCIFA compatible UART.
     - "renesas,scifb-r8a7745" for R8A7745 (RZ/G1E) SCIFB compatible UART.
     - "renesas,hscif-r8a7745" for R8A7745 (RZ/G1E) HSCIF compatible UART.
+    - "renesas,scif-r8a77470" for R8A77470 (RZ/G1C) SCIF compatible UART.
+    - "renesas,hscif-r8a77470" for R8A77470 (RZ/G1C) HSCIF compatible UART.
     - "renesas,scif-r8a7778" for R8A7778 (R-Car M1) SCIF compatible UART.
     - "renesas,scif-r8a7779" for R8A7779 (R-Car H1) SCIF compatible UART.
     - "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART.
-- 
2.7.4

Re: [PATCH 04/12] serial: sh-sci: Document r8a77470 bindings

[Geert Uytterhoeven]

On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> RZ/G1C (R8A77470) SoC also has the R-Car gen2 compatible SCIF and HSCIF
> ports, so document the SoC specific bindings.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 04/12] serial: sh-sci: Document r8a77470 bindings

[Simon Horman]

On Wed, Mar 28, 2018 at 10:03:27AM +0200, Geert Uytterhoeven wrote:
> On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> > RZ/G1C (R8A77470) SoC also has the R-Car gen2 compatible SCIF and HSCIF
> > ports, so document the SoC specific bindings.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

[PATCH 05/12] clk: renesas: Add r8a77470 CPG Core Clock Definitions

[Biju Das]

Add all RZ/G1C Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2 ("List of Clocks [RZ/G1C]") of the RZ/G1C Hardware User's
Manual.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 include/dt-bindings/clock/r8a7747x-cpg-mssr.h | 36 +++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 include/dt-bindings/clock/r8a7747x-cpg-mssr.h

diff --git a/include/dt-bindings/clock/r8a7747x-cpg-mssr.h b/include/dt-bindings/clock/r8a7747x-cpg-mssr.h
new file mode 100644
index 0000000..57a4de3
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7747x-cpg-mssr.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A7747X_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7747X_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77470 CPG Core Clocks */
+#define R8A77470_CLK_Z2		0
+#define R8A77470_CLK_ZTR	2
+#define R8A77470_CLK_ZTRD2	3
+#define R8A77470_CLK_ZT		4
+#define R8A77470_CLK_ZX		5
+#define R8A77470_CLK_ZS		6
+#define R8A77470_CLK_HP		7
+#define R8A77470_CLK_B		9
+#define R8A77470_CLK_LB		10
+#define R8A77470_CLK_P		11
+#define R8A77470_CLK_CL		12
+#define R8A77470_CLK_CP		13
+#define R8A77470_CLK_M2		14
+#define R8A77470_CLK_ZB3	16
+#define R8A77470_CLK_SDH	19
+#define R8A77470_CLK_SD0	20
+#define R8A77470_CLK_SD1	21
+#define R8A77470_CLK_SD2	22
+#define R8A77470_CLK_MP		24
+#define R8A77470_CLK_QSPI	25
+#define R8A77470_CLK_CPEX	26
+#define R8A77470_CLK_RCAN	27
+#define R8A77470_CLK_R		28
+#define R8A77470_CLK_OSC	29
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7747X_CPG_MSSR_H__ */
-- 
2.7.4

Re: [PATCH 05/12] clk: renesas: Add r8a77470 CPG Core Clock Definitions

[Geert Uytterhoeven]

Hi Biju,

On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> Add all RZ/G1C Clock Pulse Generator Core Clock Outputs, as listed in
> Table 7.2 ("List of Clocks [RZ/G1C]") of the RZ/G1C Hardware User's
> Manual.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Thanks for your patch!

>  include/dt-bindings/clock/r8a7747x-cpg-mssr.h | 36 +++++++++++++++++++++++++++

Same comment as for r8a7747x-sysc.h: Please use 0 instead of x.

With that fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 05/12] clk: renesas: Add r8a77470 CPG Core Clock Definitions

[Biju Das]

Hi Geert,

Thanks for the feedback.

> On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> > Add all RZ/G1C Clock Pulse Generator Core Clock Outputs, as listed in
> > Table 7.2 ("List of Clocks [RZ/G1C]") of the RZ/G1C Hardware User's
> > Manual.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Thanks for your patch!
>
> >  include/dt-bindings/clock/r8a7747x-cpg-mssr.h | 36
> > +++++++++++++++++++++++++++
>
> Same comment as for r8a7747x-sysc.h: Please use 0 instead of x.

Will send V2 with the file name changed to r8a77470-cpg-mssr.h

> With that fixed:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But when
> I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

[PATCH 06/12] clk: renesas: cpg-mssr: Add r8a77470 support

[Biju Das]

Add RZ/G1C (R8A77470) Clock Pulse Generator / Module Standby and Software
Reset support.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 .../devicetree/bindings/clock/renesas,cpg-mssr.txt |   9 +-
 drivers/clk/renesas/Kconfig                        |   5 +
 drivers/clk/renesas/Makefile                       |   1 +
 drivers/clk/renesas/r8a7747x-cpg-mssr.c            | 229 +++++++++++++++++++++
 drivers/clk/renesas/rcar-gen2-cpg.c                |  34 ++-
 drivers/clk/renesas/renesas-cpg-mssr.c             |   6 +
 drivers/clk/renesas/renesas-cpg-mssr.h             |   1 +
 7 files changed, 278 insertions(+), 7 deletions(-)
 create mode 100644 drivers/clk/renesas/r8a7747x-cpg-mssr.c

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
index 773a522..c3473df 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -15,6 +15,7 @@ Required Properties:
   - compatible: Must be one of:
       - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
       - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
+      - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
       - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
       - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
       - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
@@ -33,10 +34,12 @@ Required Properties:
   - clocks: References to external parent clocks, one entry for each entry in
     clock-names
   - clock-names: List of external parent clock names. Valid names are:
-      - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
-		 r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77995)
+      - "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792,
+		 r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970,
+		 r8a77980, r8a77995)
       - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
-      - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
+      - "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793,
+		     r8a7794)
 
   - #clock-cells: Must be 2
       - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index ef76c86..f32896fa 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -7,6 +7,7 @@ config CLK_RENESAS
 	select CLK_R8A7740 if ARCH_R8A7740
 	select CLK_R8A7743 if ARCH_R8A7743
 	select CLK_R8A7745 if ARCH_R8A7745
+	select CLK_R8A77470 if ARCH_R8A77470
 	select CLK_R8A7778 if ARCH_R8A7778
 	select CLK_R8A7779 if ARCH_R8A7779
 	select CLK_R8A7790 if ARCH_R8A7790
@@ -60,6 +61,10 @@ config CLK_R8A7745
 	bool "RZ/G1E clock support" if COMPILE_TEST
 	select CLK_RCAR_GEN2_CPG
 
+config CLK_R8A77470
+	bool "RZ/G1C clock support" if COMPILE_TEST
+	select CLK_RCAR_GEN2_CPG
+
 config CLK_R8A7778
 	bool "R-Car M1A clock support" if COMPILE_TEST
 	select CLK_RENESAS_CPG_MSTP
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 6c0f196..59c65d0 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_CLK_R8A73A4)		+= clk-r8a73a4.o
 obj-$(CONFIG_CLK_R8A7740)		+= clk-r8a7740.o
 obj-$(CONFIG_CLK_R8A7743)		+= r8a7743-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A7745)		+= r8a7745-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77470)		+= r8a7747x-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A7778)		+= clk-r8a7778.o
 obj-$(CONFIG_CLK_R8A7779)		+= clk-r8a7779.o
 obj-$(CONFIG_CLK_R8A7790)		+= r8a7790-cpg-mssr.o
diff --git a/drivers/clk/renesas/r8a7747x-cpg-mssr.c b/drivers/clk/renesas/r8a7747x-cpg-mssr.c
new file mode 100644
index 0000000..b6ff95f
--- /dev/null
+++ b/drivers/clk/renesas/r8a7747x-cpg-mssr.c
@@ -0,0 +1,229 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a7747 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/soc/renesas/rcar-rst.h>
+
+#include <dt-bindings/clock/r8a7747x-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen2-cpg.h"
+
+enum clk_ids {
+	/* Core Clock Outputs exported to DT */
+	LAST_DT_CORE_CLK = R8A77470_CLK_OSC,
+
+	/* External Input Clocks */
+	CLK_EXTAL,
+	CLK_USB_EXTAL,
+
+	/* Internal Core Clocks */
+	CLK_MAIN,
+	CLK_PLL0,
+	CLK_PLL1,
+	CLK_PLL3,
+	CLK_PLL1_DIV2,
+
+	/* Module Clocks */
+	MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a77470_core_clks[] __initconst = {
+	/* External Clock Inputs */
+	DEF_INPUT("extal",	CLK_EXTAL),
+	DEF_INPUT("usb_extal",	CLK_USB_EXTAL),
+
+	/* Internal Core Clocks */
+	DEF_BASE(".main",	CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
+	DEF_BASE(".pll0",	CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
+	DEF_BASE(".pll1",	CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
+	DEF_BASE(".pll3",	CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
+
+	DEF_FIXED(".pll1_div2",	CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+
+	/* Core Clock Outputs */
+	DEF_BASE("lb",   R8A77470_CLK_LB,   CLK_TYPE_GEN2_LB,	CLK_PLL1),
+	DEF_BASE("sdh",  R8A77470_CLK_SDH,  CLK_TYPE_GEN2_SDH,	CLK_PLL1),
+	DEF_BASE("sd0",  R8A77470_CLK_SD0,  CLK_TYPE_GEN2_SD0,	CLK_PLL1),
+	DEF_BASE("sd1",  R8A77470_CLK_SD1,  CLK_TYPE_GEN2_SD1,	CLK_PLL1),
+	DEF_BASE("qspi", R8A77470_CLK_QSPI, CLK_TYPE_GEN2_QSPI,	CLK_PLL1_DIV2),
+	DEF_BASE("rcan", R8A77470_CLK_RCAN, CLK_TYPE_GEN2_RCAN,	CLK_USB_EXTAL),
+
+	DEF_FIXED("z2",    R8A77470_CLK_Z2,	CLK_PLL0,	    1, 1),
+	DEF_FIXED("zx",    R8A77470_CLK_ZX,	CLK_PLL1,	    3, 1),
+	DEF_FIXED("zs",    R8A77470_CLK_ZS,	CLK_PLL1,	    6, 1),
+	DEF_FIXED("hp",    R8A77470_CLK_HP,	CLK_PLL1,	   12, 1),
+	DEF_FIXED("b",     R8A77470_CLK_B,	CLK_PLL1,	   12, 1),
+	DEF_FIXED("p",     R8A77470_CLK_P,	CLK_PLL1,	   24, 1),
+	DEF_FIXED("cl",    R8A77470_CLK_CL,	CLK_PLL1,	   48, 1),
+	DEF_FIXED("cp",    R8A77470_CLK_CP,	CLK_PLL1,	   48, 1),
+	DEF_FIXED("m2",    R8A77470_CLK_M2,	CLK_PLL1,	    8, 1),
+	DEF_FIXED("zb3",   R8A77470_CLK_ZB3,	CLK_PLL3,	    4, 1),
+	DEF_FIXED("mp",    R8A77470_CLK_MP,	CLK_PLL1_DIV2,	   15, 1),
+	DEF_FIXED("cpex",  R8A77470_CLK_CPEX,	CLK_EXTAL,	    2, 1),
+	DEF_FIXED("r",     R8A77470_CLK_R,	CLK_PLL1,	49152, 1),
+	DEF_FIXED("osc",   R8A77470_CLK_OSC,	CLK_PLL1,	12288, 1),
+
+	DEF_DIV6P1("sd2",  R8A77470_CLK_SD2,	CLK_PLL1_DIV2,	0x078),
+};
+
+static const struct mssr_mod_clk r8a77470_mod_clks[] __initconst = {
+	DEF_MOD("msiof0",		   0,	R8A77470_CLK_MP),
+	DEF_MOD("vcp0",			 101,	R8A77470_CLK_ZS),
+	DEF_MOD("vpc0",			 103,	R8A77470_CLK_ZS),
+	DEF_MOD("tmu1",			 111,	R8A77470_CLK_P),
+	DEF_MOD("3dg",			 112,	R8A77470_CLK_ZS),
+	DEF_MOD("2d-dmac",		 115,	R8A77470_CLK_ZS),
+	DEF_MOD("fdp1-0",		 119,	R8A77470_CLK_ZS),
+	DEF_MOD("tmu3",			 121,	R8A77470_CLK_P),
+	DEF_MOD("tmu2",			 122,	R8A77470_CLK_P),
+	DEF_MOD("cmt0",			 124,	R8A77470_CLK_R),
+	DEF_MOD("vsp1du0",		 128,	R8A77470_CLK_ZS),
+	DEF_MOD("vsp1-sy",		 131,	R8A77470_CLK_ZS),
+	DEF_MOD("msiof2",		 205,	R8A77470_CLK_MP),
+	DEF_MOD("msiof1",		 208,	R8A77470_CLK_MP),
+	DEF_MOD("sys-dmac1",		 218,	R8A77470_CLK_ZS),
+	DEF_MOD("sys-dmac0",		 219,	R8A77470_CLK_ZS),
+	DEF_MOD("sdhi2",		 312,	R8A77470_CLK_SD2),
+	DEF_MOD("sdhi1",		 313,	R8A77470_CLK_SD1),
+	DEF_MOD("sdhi0",		 314,	R8A77470_CLK_SD0),
+	DEF_MOD("usbhs-dmac0-ch1",	 326,	R8A77470_CLK_HP),
+	DEF_MOD("usbhs-dmac1-ch1",	 327,	R8A77470_CLK_HP),
+	DEF_MOD("cmt1",			 329,	R8A77470_CLK_R),
+	DEF_MOD("usbhs-dmac0-ch0",	 330,	R8A77470_CLK_HP),
+	DEF_MOD("usbhs-dmac1-ch0",	 331,	R8A77470_CLK_HP),
+	DEF_MOD("rwdt",			 402,	R8A77470_CLK_R),
+	DEF_MOD("irqc",			 407,	R8A77470_CLK_CP),
+	DEF_MOD("intc-sys",		 408,	R8A77470_CLK_ZS),
+	DEF_MOD("audio-dmac0",		 502,	R8A77470_CLK_HP),
+	DEF_MOD("pwm",			 523,	R8A77470_CLK_P),
+	DEF_MOD("usb-ehci-0",		 703,	R8A77470_CLK_MP),
+	DEF_MOD("usbhs-0",		 704,	R8A77470_CLK_HP),
+	DEF_MOD("usb-ehci-1",		 705,	R8A77470_CLK_MP),
+	DEF_MOD("usbhs-1",		 706,	R8A77470_CLK_HP),
+	DEF_MOD("hscif2",		 713,	R8A77470_CLK_ZS),
+	DEF_MOD("scif5",		 714,	R8A77470_CLK_P),
+	DEF_MOD("scif4",		 715,	R8A77470_CLK_P),
+	DEF_MOD("hscif1",		 716,	R8A77470_CLK_ZS),
+	DEF_MOD("hscif0",		 717,	R8A77470_CLK_ZS),
+	DEF_MOD("scif3",		 718,	R8A77470_CLK_P),
+	DEF_MOD("scif2",		 719,	R8A77470_CLK_P),
+	DEF_MOD("scif1",		 720,	R8A77470_CLK_P),
+	DEF_MOD("scif0",		 721,	R8A77470_CLK_P),
+	DEF_MOD("du1",			 723,	R8A77470_CLK_ZX),
+	DEF_MOD("du0",			 724,	R8A77470_CLK_ZX),
+	DEF_MOD("ipmmu-sgx",		 800,	R8A77470_CLK_ZX),
+	DEF_MOD("etheravb",		 812,	R8A77470_CLK_HP),
+	DEF_MOD("ether",		 813,	R8A77470_CLK_P),
+	DEF_MOD("gpio5",		 907,	R8A77470_CLK_CP),
+	DEF_MOD("gpio4",		 908,	R8A77470_CLK_CP),
+	DEF_MOD("gpio3",		 909,	R8A77470_CLK_CP),
+	DEF_MOD("gpio2",		 910,	R8A77470_CLK_CP),
+	DEF_MOD("gpio1",		 911,	R8A77470_CLK_CP),
+	DEF_MOD("gpio0",		 912,	R8A77470_CLK_CP),
+	DEF_MOD("can1",			 915,	R8A77470_CLK_P),
+	DEF_MOD("can0",			 916,	R8A77470_CLK_P),
+	DEF_MOD("qspi_mod-1",		 917,	R8A77470_CLK_QSPI),
+	DEF_MOD("qspi_mod-0",		 918,	R8A77470_CLK_QSPI),
+	DEF_MOD("i2c4",			 927,	R8A77470_CLK_HP),
+	DEF_MOD("i2c3",			 928,	R8A77470_CLK_HP),
+	DEF_MOD("i2c2",			 929,	R8A77470_CLK_HP),
+	DEF_MOD("i2c1",			 930,	R8A77470_CLK_HP),
+	DEF_MOD("i2c0",			 931,	R8A77470_CLK_HP),
+	DEF_MOD("ssi-all",		1005,	R8A77470_CLK_P),
+	DEF_MOD("ssi9",			1006,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi8",			1007,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi7",			1008,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi6",			1009,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi5",			1010,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi4",			1011,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi3",			1012,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi2",			1013,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi1",			1014,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi0",			1015,	MOD_CLK_ID(1005)),
+	DEF_MOD("scu-all",		1017,	R8A77470_CLK_P),
+	DEF_MOD("scu-dvc1",		1018,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-dvc0",		1019,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-ctu1-mix1",	1020,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-ctu0-mix0",	1021,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src6",		1025,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src5",		1026,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src4",		1027,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src3",		1028,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src2",		1029,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src1",		1030,	MOD_CLK_ID(1017)),
+};
+
+static const unsigned int r8a77470_crit_mod_clks[] __initconst = {
+	MOD_CLK_ID(402),	/* RWDT */
+	MOD_CLK_ID(408),	/* INTC-SYS (GIC) */
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ *    MD	EXTAL		PLL0	PLL1	PLL3
+ * 14 13	(MHz)		*1	*2
+ *---------------------------------------------------
+ * 0  0		20		x80/2	x78	x50
+ * 0  1		26		x60/2	x60	x56
+ * 1  0		Prohibitted setting
+ * 1  1		30		x52/2	x52	x50
+ *
+ * *1 :	Table 7.4 indicates VCO output (PLL0 = VCO/2)
+ * *2 :	Table 7.4 indicates VCO output (PLL1 = VCO)
+ */
+#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 13) | \
+					 (((md) & BIT(13)) >> 13))
+
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
+	/* EXTAL div	PLL1 mult	PLL3 mult */
+	{ 1,		78,		50,	},
+	{ 1,		60,		56,	},
+	{ /* Invalid*/				},
+	{ 1,		52,		50,	},
+};
+
+static int __init r8a7747x_cpg_mssr_init(struct device *dev)
+{
+	const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
+	u32 cpg_mode;
+	int error;
+
+	error = rcar_rst_read_mode_pins(&cpg_mode);
+	if (error)
+		return error;
+
+	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+
+	return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
+}
+
+const struct cpg_mssr_info r8a77470_cpg_mssr_info __initconst = {
+	/* Core Clocks */
+	.core_clks = r8a77470_core_clks,
+	.num_core_clks = ARRAY_SIZE(r8a77470_core_clks),
+	.last_dt_core_clk = LAST_DT_CORE_CLK,
+	.num_total_core_clks = MOD_CLK_BASE,
+
+	/* Module Clocks */
+	.mod_clks = r8a77470_mod_clks,
+	.num_mod_clks = ARRAY_SIZE(r8a77470_mod_clks),
+	.num_hw_mod_clks = 12 * 32,
+
+	/* Critical Module Clocks */
+	.crit_mod_clks = r8a77470_crit_mod_clks,
+	.num_crit_mod_clks = ARRAY_SIZE(r8a77470_crit_mod_clks),
+
+	/* Callbacks */
+	.init = r8a7747x_cpg_mssr_init,
+	.cpg_clk_register = rcar_gen2_cpg_clk_register,
+};
diff --git a/drivers/clk/renesas/rcar-gen2-cpg.c b/drivers/clk/renesas/rcar-gen2-cpg.c
index feb1457..dcc2447 100644
--- a/drivers/clk/renesas/rcar-gen2-cpg.c
+++ b/drivers/clk/renesas/rcar-gen2-cpg.c
@@ -16,6 +16,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/sys_soc.h>
 
 #include "renesas-cpg-mssr.h"
 #include "rcar-gen2-cpg.h"
@@ -257,10 +258,21 @@ static const struct clk_div_table cpg_sd01_div_table[] = {
 	{  0,  0 },
 };
 
+static const struct clk_div_table rz_g1c_cpg_sd01_div_table[] = {
+	{  5, 12 }, {  6, 16 }, {  7, 18 }, {  8, 24 },
+	{ 10, 36 }, { 11, 48 }, { 12, 10 }, {  0,  0 },
+};
+
+
 static const struct rcar_gen2_cpg_pll_config *cpg_pll_config __initdata;
 static unsigned int cpg_pll0_div __initdata;
 static u32 cpg_mode __initdata;
 
+static const struct soc_device_attribute r8a7747xes[] = {
+	{ .soc_id = "r8a77470", .revision = "ES2.*" },
+	{ /* sentinel */ }
+};
+
 struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
 	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
 	struct clk **clks, void __iomem *base,
@@ -303,7 +315,10 @@ struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
 		break;
 
 	case CLK_TYPE_GEN2_PLL1:
-		mult = cpg_pll_config->pll1_mult / 2;
+		if (soc_device_match(r8a7747xes))
+			mult = cpg_pll_config->pll1_mult;
+		else
+			mult = cpg_pll_config->pll1_mult / 2;
 		break;
 
 	case CLK_TYPE_GEN2_PLL3:
@@ -314,7 +329,10 @@ struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
 		return cpg_z_clk_register(core->name, parent_name, base);
 
 	case CLK_TYPE_GEN2_LB:
-		div = cpg_mode & BIT(18) ? 36 : 24;
+		if (soc_device_match(r8a7747xes))
+			div = 24;
+		else
+			div = cpg_mode & BIT(18) ? 36 : 24;
 		break;
 
 	case CLK_TYPE_GEN2_ADSP:
@@ -326,12 +344,20 @@ struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
 		break;
 
 	case CLK_TYPE_GEN2_SD0:
-		table = cpg_sd01_div_table;
+		if (soc_device_match(r8a7747xes))
+			table = rz_g1c_cpg_sd01_div_table;
+		else
+			table = cpg_sd01_div_table;
+
 		shift = 4;
 		break;
 
 	case CLK_TYPE_GEN2_SD1:
-		table = cpg_sd01_div_table;
+		if (soc_device_match(r8a7747xes))
+			table = rz_g1c_cpg_sd01_div_table;
+		else
+			table = cpg_sd01_div_table;
+
 		shift = 0;
 		break;
 
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 4e88e98..2c467f9 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -652,6 +652,12 @@ static const struct of_device_id cpg_mssr_match[] = {
 		.data = &r8a7745_cpg_mssr_info,
 	},
 #endif
+#ifdef CONFIG_CLK_R8A77470
+	{
+		.compatible = "renesas,r8a77470-cpg-mssr",
+		.data = &r8a77470_cpg_mssr_info,
+	},
+#endif
 #ifdef CONFIG_CLK_R8A7790
 	{
 		.compatible = "renesas,r8a7790-cpg-mssr",
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 97ccb09..efe2a14 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -133,6 +133,7 @@ struct cpg_mssr_info {
 
 extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
+extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
-- 
2.7.4

Re: [PATCH 06/12] clk: renesas: cpg-mssr: Add r8a77470 support

[Geert Uytterhoeven]

Hi Biju,

On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> Add RZ/G1C (R8A77470) Clock Pulse Generator / Module Standby and Software
> Reset support.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/drivers/clk/renesas/r8a7747x-cpg-mssr.c

For consistency, I'd call this r8a77470-cpg-mssr.c.

> @@ -0,0 +1,229 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * r8a7747 Clock Pulse Generator / Module Standby and Software Reset

r8a77470

> +static const struct cpg_core_clk r8a77470_core_clks[] __initconst = {
> +       /* External Clock Inputs */
> +       DEF_INPUT("extal",      CLK_EXTAL),
> +       DEF_INPUT("usb_extal",  CLK_USB_EXTAL),
> +
> +       /* Internal Core Clocks */
> +       DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
> +       DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
> +       DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
> +       DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
> +
> +       DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
> +
> +       /* Core Clock Outputs */
> +       DEF_BASE("lb",   R8A77470_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),

DEF_FIXED("lb", R8A77470_CLK_LB, CLK_PLL1, 24, 1)
and move it down between "b" and "p".

Note: apparently the dependency on MD18 is true for R-Car H2 only, so
I will fix this in the other clock drivers.

> +/*
> + * CPG Clock Data
> + */
> +
> +/*
> + *    MD       EXTAL           PLL0    PLL1    PLL3
> + * 14 13       (MHz)           *1      *2
> + *---------------------------------------------------
> + * 0  0                20              x80/2   x78     x50
> + * 0  1                26              x60/2   x60     x56
> + * 1  0                Prohibitted setting
> + * 1  1                30              x52/2   x52     x50

It looks like all PLL0/PLL1/PLL3 values are already the predivided values,
unlike in other clock drivers? ...

> + *
> + * *1 :        Table 7.4 indicates VCO output (PLL0 = VCO/2)
> + * *2 :        Table 7.4 indicates VCO output (PLL1 = VCO)
> + */
> +#define CPG_PLL_CONFIG_INDEX(md)       ((((md) & BIT(14)) >> 13) | \
> +                                        (((md) & BIT(13)) >> 13))
> +
> +static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {

cpg_pll_configs[4]

> +       /* EXTAL div    PLL1 mult       PLL3 mult */
> +       { 1,            78,             50,     },
> +       { 1,            60,             56,     },
> +       { /* Invalid*/                          },
> +       { 1,            52,             50,     },

... so I think these should be multiplied by the predivider, which will allow
to drop the corresponding test for RZ/G1C in rcar_gen2_cpg_clk_register.


> +};
> +
> +static int __init r8a7747x_cpg_mssr_init(struct device *dev)

r8a77470_cpg_mssr_init

> --- a/drivers/clk/renesas/rcar-gen2-cpg.c
> +++ b/drivers/clk/renesas/rcar-gen2-cpg.c
> @@ -16,6 +16,7 @@
>  #include <linux/init.h>
>  #include <linux/io.h>
>  #include <linux/slab.h>
> +#include <linux/sys_soc.h>
>
>  #include "renesas-cpg-mssr.h"
>  #include "rcar-gen2-cpg.h"
> @@ -257,10 +258,21 @@ static const struct clk_div_table cpg_sd01_div_table[] = {
>         {  0,  0 },
>  };
>
> +static const struct clk_div_table rz_g1c_cpg_sd01_div_table[] = {
> +       {  5, 12 }, {  6, 16 }, {  7, 18 }, {  8, 24 },
> +       { 10, 36 }, { 11, 48 }, { 12, 10 }, {  0,  0 },
> +};

This table is identical to cpg_sd01_div_table[], except for the missing first
entry. So perhaps you could just use &cpg_sd01_div_table[1] instead?

> +
> +
>  static const struct rcar_gen2_cpg_pll_config *cpg_pll_config __initdata;
>  static unsigned int cpg_pll0_div __initdata;
>  static u32 cpg_mode __initdata;
>
> +static const struct soc_device_attribute r8a7747xes[] = {
> +       { .soc_id = "r8a77470", .revision = "ES2.*" },

So this does not apply to ES3.0 and later?
What about ES1.*?

> +       { /* sentinel */ }
> +};

> @@ -303,7 +315,10 @@ struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
>                 break;
>
>         case CLK_TYPE_GEN2_PLL1:
> -               mult = cpg_pll_config->pll1_mult / 2;
> +               if (soc_device_match(r8a7747xes))
> +                       mult = cpg_pll_config->pll1_mult;
> +               else
> +                       mult = cpg_pll_config->pll1_mult / 2;

If think this can be dropped if the values in cpg_pll_configs[] are
multiplied by 2.

> @@ -314,7 +329,10 @@ struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
>                 return cpg_z_clk_register(core->name, parent_name, base);
>
>         case CLK_TYPE_GEN2_LB:
> -               div = cpg_mode & BIT(18) ? 36 : 24;
> +               if (soc_device_match(r8a7747xes))
> +                       div = 24;
> +               else
> +                       div = cpg_mode & BIT(18) ? 36 : 24;

Can be dropped if LB is modeled as a fixed clock instead.

>                 break;
>
>         case CLK_TYPE_GEN2_ADSP:
> @@ -326,12 +344,20 @@ struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
>                 break;
>
>         case CLK_TYPE_GEN2_SD0:
> -               table = cpg_sd01_div_table;
> +               if (soc_device_match(r8a7747xes))
> +                       table = rz_g1c_cpg_sd01_div_table;
> +               else
> +                       table = cpg_sd01_div_table;

table = cpg_sd01_div_table;
if (soc_device_match(r8a7747xes))
        table++;

> +
>                 shift = 4;
>                 break;
>
>         case CLK_TYPE_GEN2_SD1:
> -               table = cpg_sd01_div_table;
> +               if (soc_device_match(r8a7747xes))
> +                       table = rz_g1c_cpg_sd01_div_table;
> +               else
> +                       table = cpg_sd01_div_table;

Likewise.

> +
>                 shift = 0;
>                 break;

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 06/12] clk: renesas: cpg-mssr: Add r8a77470 support

[Biju Das]

Hi Geert,

Thanks for the review.

> Hi Biju,
>
> On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> > Add RZ/G1C (R8A77470) Clock Pulse Generator / Module Standby and
> > Software Reset support.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/drivers/clk/renesas/r8a7747x-cpg-mssr.c
>
> For consistency, I'd call this r8a77470-cpg-mssr.c.
>
> > @@ -0,0 +1,229 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * r8a7747 Clock Pulse Generator / Module Standby and Software Reset
>
> r8a77470

Will do
> > +static const struct cpg_core_clk r8a77470_core_clks[] __initconst = {
> > +       /* External Clock Inputs */
> > +       DEF_INPUT("extal",      CLK_EXTAL),
> > +       DEF_INPUT("usb_extal",  CLK_USB_EXTAL),
> > +
> > +       /* Internal Core Clocks */
> > +       DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
> > +       DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
> > +       DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
> > +       DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
> > +
> > +       DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
> > +
> > +       /* Core Clock Outputs */
> > +       DEF_BASE("lb",   R8A77470_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
>
> DEF_FIXED("lb", R8A77470_CLK_LB, CLK_PLL1, 24, 1) and move it down
> between "b" and "p".

Will do.

> Note: apparently the dependency on MD18 is true for R-Car H2 only, so I will fix
> this in the other clock drivers.
>
> > +/*
> > + * CPG Clock Data
> > + */
> > +
> > +/*
> > + *    MD       EXTAL           PLL0    PLL1    PLL3
> > + * 14 13       (MHz)           *1      *2
> > + *---------------------------------------------------
> > + * 0  0                20              x80/2   x78     x50
> > + * 0  1                26              x60/2   x60     x56
> > + * 1  0                Prohibitted setting
> > + * 1  1                30              x52/2   x52     x50
>
> It looks like all PLL0/PLL1/PLL3 values are already the predivided values, unlike
> in other clock drivers? ...

Yes, you are correct. will correct this table.

> > + *
> > + * *1 :        Table 7.4 indicates VCO output (PLL0 = VCO/2)
> > + * *2 :        Table 7.4 indicates VCO output (PLL1 = VCO)
> > + */
> > +#define CPG_PLL_CONFIG_INDEX(md)       ((((md) & BIT(14)) >> 13) | \
> > +                                        (((md) & BIT(13)) >> 13))
> > +
> > +static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8]
> > +__initconst = {
>
> cpg_pll_configs[4]
>
> > +       /* EXTAL div    PLL1 mult       PLL3 mult */
> > +       { 1,            78,             50,     },
> > +       { 1,            60,             56,     },
> > +       { /* Invalid*/                          },
> > +       { 1,            52,             50,     },
>
> ... so I think these should be multiplied by the predivider, which will allow to
> drop the corresponding test for RZ/G1C in rcar_gen2_cpg_clk_register.

Will correct this.

> > +};
> > +
> > +static int __init r8a7747x_cpg_mssr_init(struct device *dev)
>
> r8a77470_cpg_mssr_init

Will correct this

> > --- a/drivers/clk/renesas/rcar-gen2-cpg.c
> > +++ b/drivers/clk/renesas/rcar-gen2-cpg.c
> > @@ -16,6 +16,7 @@
> >  #include <linux/init.h>
> >  #include <linux/io.h>
> >  #include <linux/slab.h>
> > +#include <linux/sys_soc.h>
> >
> >  #include "renesas-cpg-mssr.h"
> >  #include "rcar-gen2-cpg.h"
> > @@ -257,10 +258,21 @@ static const struct clk_div_table
> cpg_sd01_div_table[] = {
> >         {  0,  0 },
> >  };
> >
> > +static const struct clk_div_table rz_g1c_cpg_sd01_div_table[] = {
> > +       {  5, 12 }, {  6, 16 }, {  7, 18 }, {  8, 24 },
> > +       { 10, 36 }, { 11, 48 }, { 12, 10 }, {  0,  0 }, };
>
> This table is identical to cpg_sd01_div_table[], except for the missing first entry.
> So perhaps you could just use &cpg_sd01_div_table[1] instead?

Will take out this table.

> > +
> > +
> >  static const struct rcar_gen2_cpg_pll_config *cpg_pll_config
> > __initdata;  static unsigned int cpg_pll0_div __initdata;  static u32
> > cpg_mode __initdata;
> >
> > +static const struct soc_device_attribute r8a7747xes[] = {
> > +       { .soc_id = "r8a77470", .revision = "ES2.*" },
>
> So this does not apply to ES3.0 and later?
> What about ES1.*?

Will take out the revision field. Currently we got only ES2.0 version,
As per my knowledge, there is no ES1.0 version.It is basically derived from R-Car E2X.

> > +       { /* sentinel */ }
> > +};
>
> > @@ -303,7 +315,10 @@ struct clk * __init
> rcar_gen2_cpg_clk_register(struct device *dev,
> >                 break;
> >
> >         case CLK_TYPE_GEN2_PLL1:
> > -               mult = cpg_pll_config->pll1_mult / 2;
> > +               if (soc_device_match(r8a7747xes))
> > +                       mult = cpg_pll_config->pll1_mult;
> > +               else
> > +                       mult = cpg_pll_config->pll1_mult / 2;
>
> If think this can be dropped if the values in cpg_pll_configs[] are multiplied by 2.

Will do

> > @@ -314,7 +329,10 @@ struct clk * __init
> rcar_gen2_cpg_clk_register(struct device *dev,
> >                 return cpg_z_clk_register(core->name, parent_name,
> > base);
> >
> >         case CLK_TYPE_GEN2_LB:
> > -               div = cpg_mode & BIT(18) ? 36 : 24;
> > +               if (soc_device_match(r8a7747xes))
> > +                       div = 24;
> > +               else
> > +                       div = cpg_mode & BIT(18) ? 36 : 24;
>
> Can be dropped if LB is modeled as a fixed clock instead.

Will do.
> >                 break;
> >
> >         case CLK_TYPE_GEN2_ADSP:
> > @@ -326,12 +344,20 @@ struct clk * __init
> rcar_gen2_cpg_clk_register(struct device *dev,
> >                 break;
> >
> >         case CLK_TYPE_GEN2_SD0:
> > -               table = cpg_sd01_div_table;
> > +               if (soc_device_match(r8a7747xes))
> > +                       table = rz_g1c_cpg_sd01_div_table;
> > +               else
> > +                       table = cpg_sd01_div_table;
>
> table = cpg_sd01_div_table;
> if (soc_device_match(r8a7747xes))
>         table++;
Will do
> > +
> >                 shift = 4;
> >                 break;
> >
> >         case CLK_TYPE_GEN2_SD1:
> > -               table = cpg_sd01_div_table;
> > +               if (soc_device_match(r8a7747xes))
> > +                       table = rz_g1c_cpg_sd01_div_table;
> > +               else
> > +                       table = cpg_sd01_div_table;
>
> Likewise.
>
> > +
> >                 shift = 0;
> >                 break;
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But when
> I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

[PATCH 07/12] ARM: shmobile: r8a77470: basic SoC support

[Biju Das]

Add minimal support for the RZ/G1C (R8A77470) SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
 arch/arm/mach-shmobile/Kconfig                     | 4 ++++
 arch/arm/mach-shmobile/setup-rcar-gen2.c           | 2 ++
 3 files changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index d3d1df9..86ac320 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -21,6 +21,8 @@ SoCs:
     compatible = "renesas,r8a7744"
   - RZ/G1E (R8A77450)
     compatible = "renesas,r8a7745"
+  - RZ/G1C (R8A77470)
+    compatible = "renesas,r8a77470"
   - R-Car M1A (R8A77781)
     compatible = "renesas,r8a7778"
   - R-Car H1 (R8A77790)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 280e731..6b91114 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -75,6 +75,10 @@ config ARCH_R8A7745
 	bool "RZ/G1E (R8A77450)"
 	select ARCH_RCAR_GEN2
 
+config ARCH_R8A77470
+	bool "RZ/G1C (R8A77470)"
+	select ARCH_RCAR_GEN2
+
 config ARCH_R8A7778
 	bool "R-Car M1A (R8A77781)"
 	select ARCH_RCAR_GEN1
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 5561dbe..80de6be 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -73,6 +73,7 @@ void __init rcar_gen2_timer_init(void)
 	shmobile_init_cntvoff();
 
 	if (of_machine_is_compatible("renesas,r8a7745") ||
+	    of_machine_is_compatible("renesas,r8a77470") ||
 	    of_machine_is_compatible("renesas,r8a7792") ||
 	    of_machine_is_compatible("renesas,r8a7794")) {
 		freq = 260000000 / 8;	/* ZS / 8 */
@@ -205,6 +206,7 @@ MACHINE_END
 static const char * const rz_g1_boards_compat_dt[] __initconst = {
 	"renesas,r8a7743",
 	"renesas,r8a7745",
+	"renesas,r8a77470",
 	NULL,
 };
 
-- 
2.7.4

Re: [PATCH 07/12] ARM: shmobile: r8a77470: basic SoC support

[Geert Uytterhoeven]

On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> Add minimal support for the RZ/G1C (R8A77470) SoC.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 08/12] ARM: dts: r8a77470: Initial SoC device tree

[Biju Das]

The initial R8A77470 SoC device tree including CPU0, GIC, timer, SYSC, RST,
CPG, and the required clock descriptions.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm/boot/dts/r8a77470.dtsi | 156 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 156 insertions(+)
 create mode 100644 arch/arm/boot/dts/r8a77470.dtsi

diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
new file mode 100644
index 0000000..24e3da6
--- /dev/null
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a77470 SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r8a7747x-cpg-mssr.h>
+#include <dt-bindings/power/r8a7747x-sysc.h>
+/ {
+	compatible = "renesas,r8a77470";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0>;
+			clock-frequency = <1000000000>;
+			clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
+			power-domains = <&sysc R8A77470_PD_CA7_CPU0>;
+			next-level-cache = <&L2_CA7>;
+		};
+
+
+		L2_CA7: cache-controller-0 {
+			compatible = "cache";
+			cache-unified;
+			cache-level = <2>;
+			power-domains = <&sysc R8A77470_PD_CA7_SCU>;
+		};
+	};
+
+	/* External root clock */
+	extal_clk: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board. */
+		clock-frequency = <0>;
+	};
+
+	/* External SCIF clock */
+	scif_clk: scif {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board. */
+		clock-frequency = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cpg: clock-controller@e6150000 {
+			compatible = "renesas,r8a77470-cpg-mssr";
+			reg = <0 0xe6150000 0 0x1000>;
+			clocks = <&extal_clk>, <&usb_extal_clk>;
+			clock-names = "extal", "usb_extal";
+			#clock-cells = <2>;
+			#power-domain-cells = <0>;
+			#reset-cells = <1>;
+		};
+
+		rst: reset-controller@e6160000 {
+			compatible = "renesas,r8a77470-rst";
+			reg = <0 0xe6160000 0 0x100>;
+		};
+
+		sysc: system-controller@e6180000 {
+			compatible = "renesas,r8a77470-sysc";
+			reg = <0 0xe6180000 0 0x200>;
+			#power-domain-cells = <1>;
+		};
+
+		icram0:	sram@e63a0000 {
+			compatible = "mmio-sram";
+			reg = <0 0xe63a0000 0 0x12000>;
+		};
+
+		icram1:	sram@e63c0000 {
+			compatible = "mmio-sram";
+			reg = <0 0xe63c0000 0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0xe63c0000 0x1000>;
+
+			smp-sram@0 {
+				compatible = "renesas,smp-sram";
+				reg = <0 0x100>;
+			};
+		};
+
+		icram2:	sram@e6300000 {
+			compatible = "mmio-sram";
+			reg = <0 0xe6300000 0 0x40000>;
+		};
+
+		scif1: serial@e6e68000 {
+			compatible = "renesas,scif-r8a77470",
+				     "renesas,rcar-gen2-scif", "renesas,scif";
+			reg = <0 0xe6e68000 0 0x40>;
+			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cpg CPG_MOD 720>,
+				 <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+			resets = <&cpg 720>;
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@f1001000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
+			      <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+			clocks = <&cpg CPG_MOD 408>;
+			clock-names = "clk";
+			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+			resets = <&cpg 408>;
+		};
+
+	};
+
+	prr: chipid@ff000044 {
+		compatible = "renesas,prr";
+		reg = <0 0xff000044 0 4>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	/* External USB clock - can be overridden by the board */
+	usb_extal_clk: usb_extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <48000000>;
+	};
+};
-- 
2.7.4

Re: [PATCH 08/12] ARM: dts: r8a77470: Initial SoC device tree

[Geert Uytterhoeven]

Hi Biju,

On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> The initial R8A77470 SoC device tree including CPU0, GIC, timer, SYSC, RST,
> CPG, and the required clock descriptions.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/arm/boot/dts/r8a77470.dtsi
> @@ -0,0 +1,156 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the r8a77470 SoC
> + *
> + * Copyright (C) 2018 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/r8a7747x-cpg-mssr.h>
> +#include <dt-bindings/power/r8a7747x-sysc.h>

It is better to use numerical values for the initial submission, as
the dt-bindings
headers and the DTS files go upstream through different maintainer paths.

> +/ {
> +       compatible = "renesas,r8a77470";

> +       soc {

> +               icram2: sram@e6300000 {
> +                       compatible = "mmio-sram";
> +                       reg = <0 0xe6300000 0 0x40000>;

Size should be 0x20000 (half of other members in the RZ/G1 family)?

> +               };

With the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 08/12] ARM: dts: r8a77470: Initial SoC device tree

[Biju Das]

Hi Geert,

Thanks for the feedback.

> On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> > The initial R8A77470 SoC device tree including CPU0, GIC, timer, SYSC,
> > RST, CPG, and the required clock descriptions.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/r8a77470.dtsi
> > @@ -0,0 +1,156 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Device Tree Source for the r8a77470 SoC
> > + *
> > + * Copyright (C) 2018 Renesas Electronics Corp.
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/clock/r8a7747x-cpg-mssr.h>
> > +#include <dt-bindings/power/r8a7747x-sysc.h>
>
> It is better to use numerical values for the initial submission, as the dt-bindings
> headers and the DTS files go upstream through different maintainer paths.
>
> > +/ {
> > +       compatible = "renesas,r8a77470";
>
> > +       soc {
>
> > +               icram2: sram@e6300000 {
> > +                       compatible = "mmio-sram";
> > +                       reg = <0 0xe6300000 0 0x40000>;
>
> Size should be 0x20000 (half of other members in the RZ/G1 family)?

Yes, you are correct. Will be fixed in V2.

> With the above fixed:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But when
> I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

[PATCH 09/12] ARM: shmobile: Document iW-RainboW-G23S single board computer

[Biju Das]

Document the iW-RainboW-G23S single board computer device tree bindings,
listing it as a supported board.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 86ac320..4401369 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -80,6 +80,8 @@ Boards:
     compatible = "renesas,h3ulcb", "renesas,r8a7795"
   - Henninger
     compatible = "renesas,henninger", "renesas,r8a7791"
+  - iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S)
+    compatible = "iwave,g23s", "renesas,r8a77470"
   - iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D)
     compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"
   - iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM)
-- 
2.7.4

Re: [PATCH 09/12] ARM: shmobile: Document iW-RainboW-G23S single board computer

[Geert Uytterhoeven]

On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
>
> Document the iW-RainboW-G23S single board computer device tree bindings,
> listing it as a supported board.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 09/12] ARM: shmobile: Document iW-RainboW-G23S single board computer

[Simon Horman]

On Wed, Mar 28, 2018 at 09:36:10AM +0200, Geert Uytterhoeven wrote:
> On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> >
> > Document the iW-RainboW-G23S single board computer device tree bindings,
> > listing it as a supported board.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thanks, applied with the subject updated to:

dt-bindings: arm:: Document iW-RainboW-G23S single board computer

RE: [PATCH 09/12] ARM: shmobile: Document iW-RainboW-G23S single board computer

[Fabrizio Castro]

Hello Simon,

thank you for reworking the subject.

> Subject: Re: [PATCH 09/12] ARM: shmobile: Document iW-RainboW-G23S single board computer
>
> On Wed, Mar 28, 2018 at 09:36:10AM +0200, Geert Uytterhoeven wrote:
> > On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> > >
> > > Document the iW-RainboW-G23S single board computer device tree bindings,
> > > listing it as a supported board.
> > >
> > > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Thanks, applied with the subject updated to:
>
> dt-bindings: arm:: Document iW-RainboW-G23S single board computer

There is an extra : in the new subject, is it too late for fixing this?

Thanks,
Fab



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

Re: [PATCH 09/12] ARM: shmobile: Document iW-RainboW-G23S single board computer

[Simon Horman]

On Thu, Mar 29, 2018 at 10:00:15AM +0000, Fabrizio Castro wrote:
> Hello Simon,
> 
> thank you for reworking the subject.
> 
> > Subject: Re: [PATCH 09/12] ARM: shmobile: Document iW-RainboW-G23S single board computer
> >
> > On Wed, Mar 28, 2018 at 09:36:10AM +0200, Geert Uytterhoeven wrote:
> > > On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> > > >
> > > > Document the iW-RainboW-G23S single board computer device tree bindings,
> > > > listing it as a supported board.
> > > >
> > > > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > > > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > >
> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > Thanks, applied with the subject updated to:
> >
> > dt-bindings: arm:: Document iW-RainboW-G23S single board computer
> 
> There is an extra : in the new subject, is it too late for fixing this?

Thanks, I will fix that.

[PATCH 10/12] ARM: dts: iwg23s-sbc: Add support for iWave G23S-SBC based on RZ/G1C

[Biju Das]

Add support for iWave iW-RainboW-G23S single board computer based on
 RZ/G1C.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm/boot/dts/Makefile                |  1 +
 arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 30 ++++++++++++++++++++++++++++++
 2 files changed, 31 insertions(+)
 create mode 100644 arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 3b4cc1b..3e4df0d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -795,6 +795,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
 	r8a7745-iwg22d-sodimm.dtb \
 	r8a7745-iwg22d-sodimm-dbhd-ca.dtb \
 	r8a7745-sk-rzg1e.dtb \
+	r8a77470-iwg23s-sbc.dtb \
 	r8a7778-bockw.dtb \
 	r8a7779-marzen.dtb \
 	r8a7790-lager.dtb \
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
new file mode 100644
index 0000000..ebbfb36
--- /dev/null
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the iWave-RZ/G1C single board computer
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a77470.dtsi"
+/ {
+	model = "iWave iW-RainboW-G23S single board computer based on RZ/G1C";
+	compatible = "iwave,g23s", "renesas,r8a77470";
+
+	aliases {
+		serial1 = &scif1;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0 0x40000000 0 0x20000000>;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <20000000>;
+};
+
+&scif1 {
+	status = "okay";
+};
-- 
2.7.4

Re: [PATCH 10/12] ARM: dts: iwg23s-sbc: Add support for iWave G23S-SBC based on RZ/G1C

[Geert Uytterhoeven]

Hi Biju,

On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> Add support for iWave iW-RainboW-G23S single board computer based on
>  RZ/G1C.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Thanks for your patch!

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

One question below.

> --- /dev/null
> +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the iWave-RZ/G1C single board computer
> + *
> + * Copyright (C) 2018 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +#include "r8a77470.dtsi"
> +/ {
> +       model = "iWave iW-RainboW-G23S single board computer based on RZ/G1C";
> +       compatible = "iwave,g23s", "renesas,r8a77470";
> +
> +       aliases {
> +               serial1 = &scif1;
> +       };

No chosen / stdout-path?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 10/12] ARM: dts: iwg23s-sbc: Add support for iWave G23S-SBC based on RZ/G1C

[Biju Das]

Hi Geert,

Thanks for the feedback.

> On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> > Add support for iWave iW-RainboW-G23S single board computer based on
> > RZ/G1C.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Thanks for your patch!
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> One question below.
>
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
> > @@ -0,0 +1,30 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Device Tree Source for the iWave-RZ/G1C single board computer
> > + *
> > + * Copyright (C) 2018 Renesas Electronics Corp.
> > + */
> > +
> > +/dts-v1/;
> > +#include "r8a77470.dtsi"
> > +/ {
> > +       model = "iWave iW-RainboW-G23S single board computer based on
> RZ/G1C";
> > +       compatible = "iwave,g23s", "renesas,r8a77470";
> > +
> > +       aliases {
> > +               serial1 = &scif1;
> > +       };
>
> No chosen / stdout-path?

I am planning this later as part of ethernet patch submission.





Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

Re: [PATCH 10/12] ARM: dts: iwg23s-sbc: Add support for iWave G23S-SBC based on RZ/G1C

[Geert Uytterhoeven]

Hi Biju,

On Wed, Mar 28, 2018 at 3:13 PM, Biju Das <biju.das@bp.renesas.com> wrote:
>> On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com> wrote:
>> > Add support for iWave iW-RainboW-G23S single board computer based on
>> > RZ/G1C.
>> >
>> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
>> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>>
>> Thanks for your patch!
>>
>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>
>> One question below.
>>
>> > --- /dev/null
>> > +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
>> > @@ -0,0 +1,30 @@
>> > +// SPDX-License-Identifier: GPL-2.0
>> > +/*
>> > + * Device Tree Source for the iWave-RZ/G1C single board computer
>> > + *
>> > + * Copyright (C) 2018 Renesas Electronics Corp.
>> > + */
>> > +
>> > +/dts-v1/;
>> > +#include "r8a77470.dtsi"
>> > +/ {
>> > +       model = "iWave iW-RainboW-G23S single board computer based on
>> RZ/G1C";
>> > +       compatible = "iwave,g23s", "renesas,r8a77470";
>> > +
>> > +       aliases {
>> > +               serial1 = &scif1;
>> > +       };
>>
>> No chosen / stdout-path?
>
> I am planning this later as part of ethernet patch submission.

But stdout-path is not related to Ethernet?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 10/12] ARM: dts: iwg23s-sbc: Add support for iWave G23S-SBC based on RZ/G1C

[Biju Das]

Hi Geert,

Thanks for the feedback.

> Hi Biju,
>
> On Wed, Mar 28, 2018 at 3:13 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> >> On Tue, Mar 27, 2018 at 4:37 PM, Biju Das <biju.das@bp.renesas.com>
> wrote:
> >> > Add support for iWave iW-RainboW-G23S single board computer based
> >> > on RZ/G1C.
> >> >
> >> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> >> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >>
> >> Thanks for your patch!
> >>
> >> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >>
> >> One question below.
> >>
> >> > --- /dev/null
> >> > +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
> >> > @@ -0,0 +1,30 @@
> >> > +// SPDX-License-Identifier: GPL-2.0
> >> > +/*
> >> > + * Device Tree Source for the iWave-RZ/G1C single board computer
> >> > + *
> >> > + * Copyright (C) 2018 Renesas Electronics Corp.
> >> > + */
> >> > +
> >> > +/dts-v1/;
> >> > +#include "r8a77470.dtsi"
> >> > +/ {
> >> > +       model = "iWave iW-RainboW-G23S single board computer based
> >> > +on
> >> RZ/G1C";
> >> > +       compatible = "iwave,g23s", "renesas,r8a77470";
> >> > +
> >> > +       aliases {
> >> > +               serial1 = &scif1;
> >> > +       };
> >>
> >> No chosen / stdout-path?
> >
> > I am planning this later as part of ethernet patch submission.
>
> But stdout-path is not related to Ethernet?

Ok. Will add stdout-path in V2.

> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But when
> I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.